DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 8/13/25. Claims 1, 4-6, 10-12, and 22-24.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4-8, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yen et al. (US PGPub 2017/0186837, hereinafter referred to as “Yen”) in view of Adusumilli et al. (US PGPub 2018/0286848, hereinafter referred to as “Adusumilli”) in further view of Park et al. (US PGPub 2015/0028450, hereinafter referred to as “Park”).
Yen discloses the semiconductor device substantially as claimed. See figures 1-14 and corresponding text, where Yen shows, in claim 1, a semiconductor structure, comprising: (figures 1-3; [0015-0027])
a substrate (102), comprising
a first doped region (104);
a first dielectric layer (110), located on the substrate;
multiple deep trench capacitors (106), extending from the first dielectric layer to an inside of the substrate, each of the deep trench capacitors penetrating through the first doped region and comprising a serrated inner wall (108);
multiple second doped regions, located in the substrate, each of the second doped regions surrounding a bottom of each deep trench capacitor and extending into the first doped region along an outer wall of the deep trench capacitor; and
a first metal layer (112), located on the first dielectric layer and connected with the multiple deep trench capacitors.
However, Yen fails to show, in claim 1, wherein an ion doping dose of the first doped region is less an ion doping dose that of the second doped region.
Adusumilli teaches, in claim 1, a similar device that includes doped regions having different concentrations (figure 6; [0048-0050]). In addition, Adusumilli provides the advantages of having high capacity deep trenches ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein an ion doping dose of the first doped region is less an ion doping dose that of the second doped region, in the device of Yen, according to the teachings of Adusumilli, with the motivation of having high capacity deep trenches within the semiconductor device.
However, Yen in view of Adusumilli fails to show, in claim 1, a through silicon via structure, wherein the through silicon via structure is located at a side of the first doped region the first doped region; wherein the multiple deep trench capacitors are located on a periphery of the through silicon via structure; wherein the first doped region is formed before the multiple second doped regions; and wherein an ion doping type of the first doped region is the same as an ion doping type of the second doped region.
Park teaches, in claim 1, a similar semiconductor device that includes a through silicon via structure that is decoupled with multiple deep trench capacitors that surround the TSV structure (figure 2; [0087-0094]). In addition, Park provides the advantages of decoupling capacitors can function as a filter with respect to irregular change in a circuit signal, thereby providing a stable operating characteristic and high reliability while further securing higher integration. In addition, preventing phenomenon in which metal ions diffuse from a metal plug with a TSV structure into a semiconductor substrate in the periphery of the TSV ([0004-0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate a through silicon via structure, wherein the through silicon via structure is located at a side of the first doped region the first doped region; wherein the multiple deep trench capacitors are located on a periphery of the through silicon via structure; wherein the first doped region is formed before the multiple second doped regions; and wherein an ion doping type of the first doped region is the same as an ion doping type of the second doped region, in the device of Yen in view of Adusumilli, according to the teachings of Park, with the motivation of having a filter to provide a stable operating characteristic and high reliability while further securing higher integration and preventing the phenomenon of metal ion diffusion from a metal plug of the TSV structure into a semiconductor substrate around the periphery of the TSV structure.
Yen in view of Adusumilli in further view of Park shows, in claim 2, wherein an ion doping type of the first doped region is the same as an ion doping type of the second doped region. (figures 1-3; [0015-0027])
Yen in view of Adusumilli in further view of Park shows, in claim 4, wherein the serrated inner wall comprises multiple recesses, a length of the recesses in a first direction ranges from 0.2 to 0.6 microns, and a length of the recesses in a second direction ranges from 0.1 to 0.4 microns. (figures 1-3; [0015-0027])
Yen in view of Adusumilli in further view of Park shows, in claim 5, wherein each of the deep trench capacitors comprises:
a first insulating layer, lining the serrated inner wall;
a first buffer layer, located on the first insulating layer; and
a first conductive layer, located on the first buffer layer, wherein the first conductive layer is connected with the first metal layer to form an internal electrode of the deep trench capacitor. (figures 1-3; [0015-0027])
Yen in view of Adusumilli in further view of Park shows, in claim 6, wherein a metal pad is included in the first dielectric layer, and the first metal layer is connected with the first doped region through the metal pad to form an external electrode of the deep trench capacitor. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 7, further comprising a through silicon via structure, wherein the through silicon via structure is located at a side of the first doped region or among the first doped region. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 8, wherein the multiple deep trench capacitors are located on a periphery of the through silicon via structure. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 9, wherein the first metal layer is connected with one end of the through silicon via structure, and another end of the through silicon via structure is connected with a metal bump. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 10, wherein the through silicon via structure comprises a serrated inner wall. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 11, wherein the through silicon via structure comprises: a second insulating layer, lining the serrated inner wall; a second buffer layer, located on the second insulating layer; and a second conductive layer, located on the second buffer layer and connected with the first metal layer. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 12, wherein a depth of the through silicon via structure ranges from 40 to 60 microns, and a depth of the deep trench capacitors ranges from 10 to 20 microns. (figures 5-7; [0032-0041])
Yen in view of Adusumilli in further view of Park shows, in claim 21, wherein the first doped region is formed before the multiple second doped regions (figures 5-7; [0032-0041]).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yen et al. (US PGPub 2017/0186837, hereinafter referred to as “Yen”) in view of Adusumilli et al. (US PGPub 2018/0286848, hereinafter referred to as “Adusumilli”) in further view of Park et al. (US PGPub 2015/0028450, hereinafter referred to as “Park”).
Yen discloses the semiconductor device as claimed. See figures 1-14 and corresponding text, where Yen teaches, in claim 22, a semiconductor structure, comprising: (figures 1-3; [0015-0027])
a substrate (102), comprising a first doped region (104);
a first dielectric layer (106), located on the substrate;
multiple deep trench capacitors, extending from the first dielectric layer to an inside of the substrate, each of the deep trench capacitors penetrating through the first doped region and comprising a serrated inner wall;
multiple second doped regions, located in the substrate, each of the second doped regions surrounding a bottom of each deep trench capacitor and extending into the first doped region along an outer wall of the deep trench capacitor; and
a first metal layer, located on the first dielectric layer and connected with the multiple deep trench capacitors;
a through silicon via structure, located in the substrate;
wherein the first metal layer is connected with one end of the through silicon via structure, and another end of the through silicon via structure is connected with a metal bump.
Adusumilli teaches, in claim 22, a similar device that includes doped regions having different concentrations (figure 6; [0048-0050]). In addition, Adusumilli provides the advantages of having high capacity deep trenches ([0004]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate wherein an ion doping dose of the first doped region is less an ion doping dose that of the second doped region, in the device of Yen, according to the teachings of Adusumilli, with the motivation of having high capacity deep trenches within the semiconductor device.
Yen in view of Adusumilli fails to show, wherein the multiple deep trench capacitors are located on a periphery of the through silicon via structure.
Park teaches, in claim 22, a similar semiconductor device that includes a through silicon via structure that is decoupled with multiple deep trench capacitors that surround the TSV structure (figure 2; [0087-0094]). In addition, Park provides the advantages of decoupling capacitors can function as a filter with respect to irregular change in a circuit signal, thereby providing a stable operating characteristic and high reliability while further securing higher integration. In addition, preventing phenomenon in which metal ions diffuse from a metal plug with a TSV structure into a semiconductor substrate in the periphery of the TSV ([0004-0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the multiple deep trench capacitors are located on a periphery of the through silicon via structure, in the device of Yen in view of Adusumilli, according to the teachings of Park, with the motivation of having a filter to provide a stable operating characteristic and high reliability while further securing higher integration and preventing the phenomenon of metal ion diffusion from a metal plug of the TSV structure into a semiconductor substrate around the periphery of the TSV structure.
Yen in view of Adusumilli in further view of Park shows, in claim 23, wherein a depth of a deep trench capacitor of the multiple deep trench capacitors is smaller than of a depth of the through silicon via structure (figure 2; [0087-0094]).
Yen in view of Adusumilli in further view of Park shows, in claim 24, wherein the through silicon via structure is located at a side of the first doped region or among the first doped region (figure 2; [0087-0094]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-6, 10-12, and 22-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 11-8.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 November 6, 2025
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898