DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the plurality of channel regions”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuchiaki (U.S. Patent No. 7,420,230).
Regarding to claim 1, Tsuchiaki teaches a gate-all-around transistor structure comprising:
a channel region surrounded on three sides by a gate conductor (Fig. 1, gate conductor 105 surrounds the top side, left sidewall and right sidewall of channel region of fin 102); and
a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor (Fig. 1, column 5, lines 39-40, salicide regions 122/leftside and 122/rightside extending from opposite ends of the channel region in direction parallel with the gate conductor 105).
Regarding to claim 5, Tsuchiaki teaches a thickness of channel region is equal to a thickness of each of the plurality of salicide regions (Fig. 1).
Regarding to claim 7, Tsuchiaki teaches a gate-all-around transistor structure comprising:
a plurality of channel regions surrounded on three sides by a gate conductor (Fig. 1, gate conductor 105 surrounds the top side, left sidewall and right sidewall of channel region of fin 102. Only one device is shown in the figure, large numbers of devices are fabrication on a wafer substrate); and
a plurality of salicide regions extending from opposite ends of the plurality of channel regions in a direction parallel with the gate conductor (Fig. 1, column 5, lines 39-40, salicide regions 122/leftside and 122/rightside extending from opposite ends of the channel region in a direction parallel with the gate conductor 105. Only one device is shown in the figure, large numbers of devices are fabrication on a wafer substrate).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tsushinki (U.S. Patent No. 7,420,230).
Regarding to claim 1, Tsuchiaki teaches a gate-all-around transistor structure (Fig. 1, Fig. 5P, Fig. 6) comprising:
a channel region surrounded on three sides by a gate conductor (Fig. 5P, Fig. 6, column 7, lines 50-51, gate conductor 205 surrounds the top side, left sidewall and right sidewall of channel region of fin 220); and
a pair of salicide regions extending in a direction parallel with the gate conductor (Fig. 5P, Fig. 6, column10, lines 46-47, salicide regions 233 on left side of the gate structure and 233 on right side of the gate structure extending in a direction parallel with the gate conductor 205).
Tsushinki does not clearly show in Fig. 5-6 that a pair of salicide regions extending from opposite ends of the channel region. However, in Fig. 1, Tsushinki clearly shows a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor (Fig. 1, column 5, lines 39-40, salicide regions 122/leftside and 122/rightside extending from opposite ends of the channel region in a direction parallel with the gate conductor 105). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend the pair of salicide regions from opposite ends of the channel region in order to reduce contact resistance for the source drain regions.
Regarding to claim 2, Tsuchiaki teaches a pair of contact structures contacting uppermost surfaces of the pair of salicide regions (column 14, lines 25-29).
Regarding to claim 3, Tsuchiaki teaches a gate cut region arranged between gate spacers (Fig. 6, element 207) and aligned with the gate conductor (Fig. 6, element 205), wherein the gate cut region directly contacts a sidewall of the channel region (Fig. 6).
Regarding to claim 4, Tsuchiaki teaches the pair of salicide regions are arranged above a pair of inner spacers (Fig. 5P, Fig. 6, note that the claim does not specify direction of “above”).
Regarding to claim 5, Tsuchiaki teaches a thickness of each of the plurality of channel regions is equal to a thickness of each of the plurality of salicide regions (Fig. 5P).
Regarding to claim 6, Tsuchiaki teaches each of the pair of salicide regions are arranged directly beneath a gate spacer (Fig. 6).
Regarding to claim 7, Tsuchiaki teaches a gate-all-around transistor structure (Fig. 1, Fig. 5P, Fig. 6) comprising:
a plurality of channel regions surrounded on three sides by a gate conductor (Fig. 5P, Fig. 6, column 7, lines 50-51, gate conductor 205 surrounds the top side, left sidewall and right sidewall of channel region of fin 210 and of channel region of fin 220); and
a plurality of salicide regions extending in a direction parallel with the gate conductor (Fig. 5P, Fig. 6, column10, lines 16-17, lines 46-47, salicide regions 233 on left side of the gate structure and 233 on right side of the gate structure, and salicide regions 213 on left side of the gate structure and 213 on right side of the gate structure, extending in a direction parallel with the gate conductor 205).
Tsushinki does not clearly show in Fig. 5-6 that a pair of salicide regions extending from opposite ends of the channel region. However, in Fig. 1, Tsushinki clearly shows a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor (Fig. 1, column 5, lines 39-40, salicide regions 122/leftside and 122/rightside extending from opposite ends of the channel region in a direction parallel with the gate conductor 105). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend the pair of salicide regions from opposite ends of the channel region in order to reduce contact resistance for the source drain regions.
Regarding to claim 8, Tsuchiaki teaches individual contact structures contacting uppermost surfaces of each of the plurality of salicide regions (column 14, lines 25-29).
Regarding to claim 10, Tsuchiaki teaches a gate cut region arranged between gate spacers (Fig. 6, element 207) and aligned with the gate conductor (Fig. 6, element 205), wherein the gate cut region directly contacts a sidewall of the channel region (Fig. 6).
Regarding to claim 11, Tsuchiaki teaches the pair of salicide regions are arranged above a pair of inner spacers (Fig. 5P, Fig. 6, note that the claim does not specify direction of “above”).
Regarding to claim 12, Tsuchiaki teaches a thickness of each of the plurality of channel regions is equal to a thickness of each of the plurality of salicide regions (Fig. 5P).
Claims 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (U.S. Patent No. 12,300,723) and view of Zhu (U.S. Patent No. 12,477,750).
Regarding to claim 14, Cheng teaches a gate-all-around transistor structure comprising:
a plurality of nanosheet channel regions surrounded on three sides by a gate conductor (Fig. 1); and
a pair of salicide regions extending from opposite ends of the plurality of channel regions in a direction parallel with the gate conductor (Fig. 1).
Cheng does not disclose each pair of salicide regions on the source/drain structures extend different distances from the opposite ends of each of the plurality of channel regions.
Zhu discloses silicide on the source/drain structure (column 15, lines 35-38), and each pair of source/drain regions extend different distances from the opposite ends of each of the plurality of channel regions (Figs. 24(a)-(b)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng in view of Zhu to extend each pair of salicide regions different distances from the opposite ends of each of the plurality of channel regions in order to make contact to each of the source/drain structure.
Regarding to claim 15, Zhu teaches a pair of contact structures contacting uppermost surfaces of the pair of salicide regions (Fig. 24(b)).
Regarding to claim 16, Zhu teaches at least two of the plurality of contact structures comprise different heights (Fig. 24(b)).
Regarding to claim 17, Cheng teaches a gate cut region arranged between gate spacers and aligned with the gate conductor (Fig. 1, gate cut region arranged between gate spacers 154 and aligned with the gate conductor).
Regarding to claim 18, Cheng teaches each of the plurality of silicide regions are arranged one above the other and separated by a plurality of inner spacers (Fig. 1).
Regarding to claim 20, Cheng teaches each of the plurality of channel regions are arranged vertically one above the other (Fig. 1).
Allowable Subject Matter
Claims 9, 13, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “at least two of the individual contact structures comprise different heights” in combination with the limitations recited in claims 7-8.
Regarding to claim 13, the prior art fails to anticipate or render obvious the claimed limitations including “each of the plurality of channel regions are arranged vertically one above the other” in combination with the limitations recited in claim 7.
Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “a thickness of each of the plurality of channel regions is equal to a thickness of each of the plurality of salicide regions” in combination with the limitations recited in claim 14.
Pertinent Art
For the benefits of the Applicant, US-9209302-B2, US-8716797-B2, US-7667271-B2, US-20230178435-A1, US-9252252-B2, and US-12096630-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to discloses the combination of limitations including “a plurality of nanosheet channel regions surrounded on three sides by a gate conductor and a pair of salicide regions extending from opposite ends of each of the plurality of channel regions in a direction parallel with the gate conductor, wherein each pair of salicide regions extend different distances from the opposite ends of each of the plurality of channel regions.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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