DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 2, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 8, 11 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the last line of claims 1 and 11 recite “the BEOL layer” but this phrase lacks antecedent basis and appears to be a reference to the “BEOL interconnect” but the Applicant’s intention is unclear in this regard. Further, claims 8 and 18 recite “the BEOL structure” which lacks antecedent basis because of the cancellation of claim 7. Finally, claim 18 depends from claim 17, but claim 17 was cancelled, so claim 18 will for purposes of examination be assumed to depend from claim 11 in the same way claim 8 was amended to depend from claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 11 and 18 are rejected under 35 U.S.C. 102(a)(2) as being obvious in view of US 2023/0036522 A1 to Chen et al. (hereinafter “Chen ‘522” – previously cited reference).
Regarding claim 1, as best understood, Chen ‘522 discloses a semiconductor device (inverter circuit 100; Fig. 1A; paragraph [0044]) comprising:
a back end of line (BEOL) interconnect (front-side and back-side conductive layers; Fig. 1A; paragraphs [0044], [0047]);
a first field effect transistor (FET) formed over the BEOL interconnect (p-type active region semiconductor structure 50p formed over conductive layer; Fig. 1A; paragraphs [0047], [0163]);
a second FET vertically stacked on top of the first FET (n-type active region semiconductor structure 50n vertically stacked on top of structure 50p; Fig. 1A; paragraph [0047]);
a backside contact (BSCA) connected to a backside power rail (BSPR) (source/drain terminals connected to back-side power rail 30B; Fig. 1A; paragraph [0046]); and
a via to backside power rail (VBPR), the VBPR contacting the BSCA (bottom via-connector VB, inter-connector VMD, and via-connector VT collectively contacting source/drain terminals; Fig. 1A; paragraph [0047]), wherein the second FET is vertically stacked over the first FET in a direction perpendicular to a main surface of the BEOL interconnect, the direction extending from the VBPR to the BEOL layer (structure 50n stacked vertically over structure 50p in a vertical direction extending from VB to conductive layer which is perpendicular to main surface of horizontal conductive layer; Fig 1A).
Chen ‘522 fails to explicitly disclose the VBPR extending from the first FET to the second FET.
However, Chen ‘522 discloses bottom via-connector VB, inter-connector VMD, and via-connector VT extending from underneath structure 50n, between structures 50n, 50p and above structure 50p, which arguably discloses the limitation at issue if the source/drain terminals are considered a part of the FET structures 50n, 50p, although the connectors do not appear to contact the FET structures 50n, 50p but rather only the source/drain terminals of the structures 50n, 50p.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to consider the source/drain terminals a part of the FET structures 50n, 50p or to have the source/drain terminals be integral to the FET structures 50n, 50p when depicted in Figs. 1A-1C given that source/drain terminals are commonly considered a part of a FET and not separate distinct structures therefrom. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to modify the connectors VB, VMD, VT to be a unitary structure running vertically adjacent and in contact with the FET structures 50n, 50p in order to reduce series resistance present at plural interfaces, reduces process complexity from multiple aligned formation steps to a single formation step, and improves device reliability by reducing the number of structurally distinct interfaces.
Regarding claim 8, as best understood, Chen ‘522 discloses the semiconductor device according to claim 1, wherein the VBPR connects to the BEOL structure (bottom via-connector VB connects to conductive layer; Fig. 1A).
Regarding claim 11, as best understood, Chen ‘522 discloses a method of manufacturing a semiconductor device (forming inverter circuit 100; Fig. 1A; paragraph [0044]), the method comprising:
forming a back end of line (BEOL) interconnect (front-side and back-side conductive layers; Fig. 1A; paragraphs [0044], [0047]);
forming a first field effect transistor (FET) over the BEOL interconnect (p-type active region semiconductor structure 50p formed over conductive layer; Fig. 1A; paragraphs [0047], [0163]);
forming a second FET that is vertically stacked over the first FET (n-type active region semiconductor structure 50n vertically stacked on top of structure 50p; Fig. 1A; paragraph [0047]);
forming a backside contact (BSCA) that is connected to a backside power rail (BSPR) (source/drain terminals connected to back-side power rail 30B; Fig. 1A; paragraph [0046]); and
forming a via to backside power rail (VBPR), the VBPR contacting the BSCA (bottom via-connector VB, inter-connector VMD, and via-connector VT collectively contacting source/drain terminals; Fig. 1A; paragraph [0047]), wherein the second FET is vertically stacked over the first FET in a direction perpendicular to a main surface of the BEOL interconnect, the direction extending from the VBPR to the BEOL layer (structure 50n stacked vertically over structure 50p in a vertical direction extending from VB to conductive layer which is perpendicular to main surface of horizontal conductive layer; Fig 1A).
Chen ‘522 fails to explicitly disclose the VBPR extending from the first FET to the second FET.
However, Chen ‘522 discloses bottom via-connector VB, inter-connector VMD, and via-connector VT extending from underneath structure 50n, between structures 50n, 50p and above structure 50p, which arguably discloses the limitation at issue if the source/drain terminals are considered a part of the FET structures 50n, 50p, although the connectors do not appear to contact the FET structures 50n, 50p but rather only the source/drain terminals of the structures 50n, 50p.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to consider the source/drain terminals a part of the FET structures 50n, 50p or to have the source/drain terminals be integral to the FET structures 50n, 50p when depicted in Figs. 1A-1C given that source/drain terminals are commonly considered a part of a FET and not separate distinct structures therefrom. Further, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to modify the connectors VB, VMD, VT to be a unitary structure running vertically adjacent and in contact with the FET structures 50n, 50p in order to reduce series resistance present at plural interfaces, reduces process complexity from multiple aligned formation steps to a single formation step, and improves device reliability by reducing the number of structurally distinct interfaces.
Regarding claim 18, as best understood, Chen ‘522 discloses the method according to claim 17, wherein the VBPR connects to the BEOL structure (see claim 8 above).
Claims 2-3, 6, 12-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘522 in further view of US 11,195,930 B1 to Chen et al. (hereinafter “Chen ‘930” – previously cited reference).
Regarding claims 2 and 12, Chen ‘522 discloses the semiconductor device and method of claims 1 and 11. Chen ‘522 fails to disclose wherein the first FET and the second FET include alternating layers of active semiconductor layers and high-κ metal gate layers.
However, Chen ‘930 discloses wherein the first FET and the second FET include alternating layers of active semiconductor layers and high-κ metal gate layers (adjacent transistor devices comprising alternating semiconductor layers 24 and gate electrode layers 84 surrounded by high-k gate dielectric layers 82; Fig. 27C; column 9, lines 41-64).
Chen ‘522 and Chen ‘930 are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Chen ‘930 in order to reduce leakage current, increase gate capacitance, and improve control over the channel which allows scaling down to smaller feature sizes.
Regarding claims 3 and 13, Chen ‘522 in view of Chen ‘930 discloses the semiconductor device and method according to claims 2 and 12. Chen ‘522 fails to disclose further comprising a gate spacer surrounding the high-κ metal gate layers.
However, Chen ‘930 discloses further comprising a gate spacer surrounding the high-κ metal gate layers (adjacent transistor devices comprising alternating semiconductor layers 24 and gate electrode layers 84 surrounded by high-k gate dielectric layers 82; Fig. 27C; column 9, lines 41-64).
Chen ‘522 and Chen ‘930 are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Chen ‘930 in order to improve the control of the electric field within the channel, leading to reduced leakage current while maintaining good on-current which provides better device performance and power efficiency.
Regarding claims 6 and 16, Chen ‘522 discloses the semiconductor device and method of claims 4 and 14. Chen ‘522 fails to disclose the BSCA connects to the BSPR through a backside via.
However, Chen ‘930 discloses wherein the BSCA connects to the BSPR through a backside via (backside contact 128 coupled to power rail via conductive feature 134 which may be an interconnect structure including metal lines and vias; Figs. 27A-27D; column 11, lines 42-60; column 15, lines 44-52).
Chen ‘522 and Chen ‘930 are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Chen ‘930 in order to utilize backside power delivery for reducing power consumption and chip form factor.
Claims 4-5, 9-10, 14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘522 in further view of US 2020/0411436 A1 to Xie et al. (hereinafter “Xie” – previously cited reference).
Regarding claim 4, Chen ‘522 discloses the semiconductor device according to claim 1. Chen ‘522 fails to disclose further comprising a bottom epitaxial layer and a top epitaxial layer.
However, Xie discloses further comprising a bottom epitaxial layer and a top epitaxial layer (top and bottom nanosheet layers 140, 150 formed by epitaxial growth; paragraphs [0038], [0094]).
Chen ‘522 and Xie are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Xie in order to potentially provide lower power-delivery resistance and IR drop, wider active-region structures for higher drive current and better density, and independent optimization of NFET and PFET performance.
Regarding claim 5 and 15, Chen ‘522 in view of Xie discloses the semiconductor device and method of claims 4 and 14. Chen ‘522 fails to disclose wherein the BSCA contacts the bottom epitaxial layer.
However, Xie discloses wherein the BSCA contacts the bottom epitaxial layer (conductive device contact 290 and buried contact 270 contact the nanosheet layers 140, 150 as shown in Figs. 15-16, 20; paragraphs [0094], [0102], [0106]).
Chen ‘522 and Xie are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Xie in order to potentially provide lower power-delivery resistance and IR drop, wider active-region structures for higher drive current and better density, and independent optimization of NFET and PFET performance.
Regarding claims 9 and 19, Chen ‘522 in view of Xie discloses the semiconductor device and method according to claims 4 and 14. Chen ‘522 fails to disclose further comprising a S/D contact in contact with the top epitaxial layer.
However, Xie discloses further comprising a S/D contact in contact with the top epitaxial layer (source/drain 240 epitaxially grown upon top of nanosheet layers 140, 150; Figs. 15-16; paragraph [0094]).
Chen ‘522 and Xie are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Xie in order to potentially provide lower power-delivery resistance and IR drop, wider active-region structures for higher drive current and better density, and independent optimization of NFET and PFET performance.
Regarding claims 10 and 20, Chen ‘522 discloses the semiconductor device and method according to claims 9 and 19. Chen ‘522 fails to disclose wherein the VBPR is formed in contact with the S/D contact.
However, Xie discloses wherein the VBPR is formed in contact with the S/D contact (metal via 295 connected to source/drain 240 via conductive device contact 290 as shown in Fig. 20; paragraph [0106]).
Chen ‘522 and Xie are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Xie in order to potentially provide lower power-delivery resistance and IR drop, wider active-region structures for higher drive current and better density, and independent optimization of NFET and PFET performance.
Regarding claim 14, Chen ‘522 discloses the method according to claim 11. Chen ‘522 fails to disclose further comprising: forming a bottom epitaxial layer and a top epitaxial layer; forming a backside contact placeholder that is under the bottom epitaxial layer; removing the backside contact placeholder; and forming the BSCA in an area where the backside contact placeholder was removed.
However, Xie discloses further comprising: forming a bottom epitaxial layer and a top epitaxial layer (top and bottom nanosheet layers 140, 150 formed by epitaxial growth; paragraphs [0038], [0094]); forming a backside contact placeholder that is under the bottom epitaxial layer (upper and lower fill layers 177, 250 formed at a lower level relative top and bottom nanosheet layers 140, 150 as shown in Figs. 15, 17, 20; paragraph [0104]); removing the backside contact placeholder (portion of upper fill layer 250 is removed as shown in Figs. 19-20; paragraph [0106]); and forming the BSCA in an area where the backside contact placeholder was removed (conductive device contact 290 formed in area where upper fill layer 250 was removed as shown in Figs. 19-20; paragraph [0106]).
Chen ‘522 and Xie are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with backside power rails. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Chen ‘522 to incorporate the teaching of Xie in order to potentially provide lower power-delivery resistance and IR drop, wider active-region structures for higher drive current and better density, and independent optimization of NFET and PFET performance.
Response to Arguments
Applicant's arguments filed May 4, 2026 have been fully considered. Applicant presents substantive amendments to claims 1 and 11 and corresponding arguments. Examiner agrees that amended claims 1 and 11 overcome the previous 35 USC 102 rejection using Chen ‘522. However, amended claims 1 and 11 have been rejected on new grounds of 35 USC 103 using Chen ‘522. Further, Examiner notes that Applicant did not correct the 35 USC 112(b) issues which appears to be merely an accidental oversight on the part of the Applicant. Additionally, Applicant lists claim 8 as being ‘currently amended’ but makes no amendments to this claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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