Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments in the appeal brief filed on 08/26/2025 with respect to claims 1 and 16 have been considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Okuda.
Response to Appeal Brief
In view of the appeal brief filed on 08/26/2025, PROSECUTION IS HEREBY REOPENED. A new ground of rejection is set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113 (if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
Allowable Subject Matter
Claims 2-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The reason for the allowance of the claim is the prior art of the record, alone or in combination does not explicitly teach, suggest, or render obvious the limitation of “wherein the diode region includes a plurality of trench gates provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer,
the at least one dummy active trench gate is provided so as to be interposed between two semi-trench gates,
the third semiconductor layer in a floating state is provided between the at least one dummy active trench gate and the two semi-trench gates,
each of the plurality of trench gates includes the third semiconductor layer applied with the first potential on both of two side surfaces,
each of the two semi-trench gates includes the third semiconductor layer in a floating state on one of two side surfaces that is closer to the at least one dummy active trench gate, and includes the third semiconductor layer applied with the first potential on the other side surface, and
the plurality of trench gates and the two semi-trench gates are applied with the first potential,” along with the other claimed features, as recited in claim 2.
Claim 3 is allowed for the same reasons as claim 2, from which they depend.
The reason for the allowance of the claim is the prior art of the record, alone or in combination does not explicitly teach, suggest, or render obvious the limitation of “wherein the diode region includes a plurality of trench gates provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer,
the at least one dummy active trench gate is provided as two dummy active semi-trench gates arranged to face each other,
each of the two dummy active semi-trench gates includes the third semiconductor layer in a floating state on one of two side surfaces that faces the other dummy active semi-trench gate, and includes the third semiconductor layer applied with the first potential on the other side surface,
each of the plurality of trench gates includes the third semiconductor layer applied with the first potential on both of two side surfaces,
the two dummy active semi-trench gates are applied with the gate potential of the transistor, and
the plurality of trench gates are applied with the first potential,” along with the other claimed features, as recited in claim 4.
The reason for the allowance of the claim is the prior art of the record, alone or in combination does not explicitly teach, suggest, or render obvious the limitation of “wherein the diode region includes a plurality of trench gates provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer,
the at least one dummy active trench gate is provided so as to be interposed between two dummy active semi-trench gates,
the third semiconductor layer in a floating state is provided between the at least one dummy active trench gate and the two dummy active semi-trench gates,
each of the plurality of trench gates includes the third semiconductor layer applied with the first potential on both of two side surfaces,
each of the two dummy active semi-trench gates includes the third semiconductor layer in a floating state on one of two side surfaces that is closer to the at least one dummy active trench gate, and includes the third semiconductor layer applied with the first potential on the other side surface,
the two dummy active semi-trench gates are applied with the gate potential of the transistor, and
the plurality of trench gates are applied with the first potential,” along with the other claimed features, as recited in claim 5.
Claim 6-8 are allowed for the same reasons as claim 5, from which they depend.
The reason for the allowance of the claim is the prior art of the record, alone or in combination does not explicitly teach, suggest, or render obvious the limitation of “wherein the diode region includes a plurality of active trench gates and a plurality of trench gates provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer,
the at least one dummy active trench gate is provided so as to be interposed between two dummy active semi-trench gates,
the third semiconductor layer in a floating state is provided between the at least one dummy active trench gate and the two dummy active semi-trench gates,
each of the plurality of active trench gates includes the third semiconductor layer applied with the first potential on both of two side surfaces,
each of the two dummy active semi-trench gates includes the third semiconductor layer in a floating state on one of two side surfaces that is closer to the at least one dummy active trench gate, and includes the third semiconductor layer applied with the first potential on the other side surface, and
the plurality of active trench gates and the two dummy active semi-trench gates are applied with the gate potential of the transistor,” along with the other claimed features, as recited in claim 9.
Claim 10-12 are allowed for the same reasons as claim 9, from which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 15- 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okuda et al. (U.S. 2018/0323294 A1, hereinafter refer to Okuda).
Regarding Claim 1: Okuda discloses a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate (11/10/8/7) (see Okuda, Fig.12 as shown below and ¶ [0001]),
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wherein the semiconductor substrate (11/10/8/7) (see Okuda, Fig.12 as shown above) includes:
a transistor region (note: the region where active gate trench 1 formed therein is equivalent to the claimed transistor region because active gate trench forms active IGBT element/transistor and the region where the active IGBT element/transistor formed therein called “transistor region”) in which the transistor is formed (see Okuda, Fig.12 as shown above); and
a diode region (note: the region where dummy trench gates 2 and 3 formed therein is equivalent to the claimed diode region because since n+ type emitter layer 6 is not formed in region where dummy trench gates 2 and 3 formed, there is no active transistor but pn diode necessarily formed by layers 7 and 8/10/11. Hence, it can be called diode region) in which the diode is formed (see Okuda, Fig.12 as shown above),
the diode region (see Okuda, Fig.12 as shown above) includes:
a first semiconductor layer (11) of a first conductivity type (n-type) provided on a second-main-surface side (note: the back-side surface of the prior art substrate is equivalent to the claimed limitation of “second-main-surface side”) in the semiconductor substrate (see Okuda, Fig.12 as shown above);
a second semiconductor layer (10/8) of the first conductivity type (n-type) provided on the first semiconductor layer (11) (see Okuda, Fig.12 as shown above);
a third semiconductor layer (7a and 7b) of a second conductivity type (p-type) provided closer to a first main surface (note: the front-side surface of the prior art substrate is equivalent to the claimed limitation of “first main surface”) of the semiconductor substrate than the second semiconductor layer (10/8) (see Okuda, Fig.12 as shown above);
a first main electrode (31) that applies a first potential to the diode (diode region) (see Okuda, Fig.12 as shown above and ¶ [0044]);
a second main electrode (32) that applies a second potential to the diode (diode region) (note: the first potential and the second potential can be the same or different because a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus since the prior art apparatus teaches all the structural limitations of the claim) (see Okuda, Fig.12 as shown above and ¶ [0044]); and
at least one dummy active trench gate (note: at least one of the dummy active trench gate 2 or 3 is equivalent to the claimed limitation of “at least one dummy active trench gate”) provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer (8/10) (see Okuda, Fig.12 as shown above),
the at least one dummy active trench gate (2/3) includes the third semiconductor layer (7a/7b) that is not applied with the first potential (31) (note: a portion of the third semiconductor layer such as 7b is not applied with the first potential (31)) to be in a floating state on at least one of two side surfaces (note: one side of dummy trench gate 2/3 not connected to the first potential 31 which results the dummy trench gate to be in floating state) (see Okuda, Fig.12 as shown above), and
the at least one dummy active trench gate (2/3) is applied with a gate potential of the transistor (1) (note: dummy trench gate 2/3 and active trench gate 1 are connected to the same potential 30) (see Okuda, Fig.12 as shown above).
Regarding Claim 15: Okuda discloses a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate as set forth in claim 1 as above. Okuda further teaches wherein the semiconductor substrate (11/10/8/7) is formed of a material selected from a group consisting of silicon, silicon carbide, a gallium nitride-based material, a gallium oxide-based material, and diamond (silicon, gallium nitride, silicon carbide, aluminum nitride, diamond, and gallium oxide) (see Okuda, Fig.12 as shown above and ¶ [0099]).
Regarding Claim 16: Okuda discloses a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate (11/10/8/7) (see Okuda, Fig.12 as shown above and ¶ [0001]),
wherein the semiconductor substrate (11/10/8/7) (see Okuda, Fig.12 as shown above) includes:
a transistor region (note: the region where active gate trench 1 formed therein is equivalent to the claimed transistor region because forms active IGBT element/transistor and the region which the active IGBT element/transistor formed therein called “transistor region”) in which the transistor is formed (see Okuda, Fig.12 as shown above); and
a diode region (note: the region where dummy trench gates 2 and 3 formed therein is equivalent to the claimed diode region because since n+ type emitter layer 6 is not formed in region where dummy trench gates 2 and 3 formed, there is no active transistor but pn diode necessarily formed by layers 7 and 8/10/11. Hence, it can be called diode region) in which the diode is formed (see Okuda, Fig.12 as shown above),
the diode region (see Okuda, Fig.12 as shown above) includes:
a first semiconductor layer (11) of a first conductivity type (n-type) provided on a second-main-surface side (note: the back-side surface of the prior art substrate is equivalent to the claimed limitation of “second-main-surface side”) in the semiconductor substrate (see Okuda, Fig.12 as shown above);
a second semiconductor layer (8/10) of the first conductivity type (n-type) provided on the first semiconductor layer (11) (see Okuda, Fig.12 as shown above);
a third semiconductor layer (7a and 7b) of a second conductivity type (p-type) provided closer to a first main surface (note: the front-side surface of the prior art substrate is equivalent to the claimed limitation of “first main surface”) of the semiconductor substrate than the second semiconductor layer (8/10) (see Okuda, Fig.12 as shown above);
a first main electrode (31) that applies a first potential to the diode (diode region) (see Okuda, Fig.12 as shown above and ¶ [0044]);
a second main electrode (32) that applies a second potential to the diode (diode region) (note: the first potential and the second potential can be the same or different because a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus since the prior art apparatus teaches all the structural limitations of the claim) (see Okuda, Fig.12 as shown above and ¶ [0044]); and
at least one dummy active trench gate (2 and 3) provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer (8/10) () (see Okuda, Fig.12 as shown above),
the at least one dummy active trench gate (2/3) includes the second semiconductor layer (8/10) that is not applied with the first potential to be in a floating state on at least one of two side surfaces (note: one side of dummy trench gate 2/3 not connected to the first potential 31 which results the dummy trench gate to be in floating state) (see Okuda, Fig.12 as shown above), and
the at least one dummy active trench gate (2/3) is applied with a gate potential (30) of the transistor (1) (note: dummy trench gate 2/3 and active trench gate 1 are connected to the same potential 30) (see Okuda, Fig.12 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (U.S. 2018/0323294 A1, hereinafter refer to Okuda) as applied to claim 1 above, and further in view of Soneda et al. (U.S. 2021/0265491 A1, hereinafter refer to Soneda).
Regarding Claim 13: Okuda discloses a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate as applied claim 1 above. Okuda further teaches wherein the transistor region and the diode region are arranged so as to alternate with each other along an extending direction of a trench gate (1/2/3) (note: see the annotating Fig.12 as shown above) (see Okuda, Fig.12 as shown above),
the at least one dummy active trench gate (2/3) is provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer (8/10) and is provided so as to be continuous with an active trench gate (1) applied with the gate potential (30) of the transistor, in the transistor region (see Okuda, Fig.12 as shown above).
Okuda is silent upon explicitly disclosing wherein the trench gate is provided so as to penetrate the transistor region and the diode region in plan view.
For support see Soneda, which teaches a semiconductor device wherein the trench gate (11/12/21/22) is provided so as to penetrate the transistor region (10) and the diode region (20) in plan view (see Soneda, Figs.3, 6, 17, and 20-21 and ¶ [0006]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Okuda and Soneda to enable the Okuda trench gate to be provided so as to penetrate the transistor region and the diode region in plan view as taught by Soneda in order to obtain a semiconductor device that suppresses electric field concentration in end portions of first and second trench gates which are disposed adjacent to each other in the direction of extension of the trench gates.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Okuda et al. (U.S. 2018/0323294 A1, hereinafter refer to Okuda) as applied to claim 1 above, and further in view of Kamibaba et al. (U.S. 2020/0287028 A1, hereinafter refer to Kamibaba).
Regarding Claim 14: Okuda discloses a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate as applied claim 1 above. Okuda further teaches wherein the transistor region and the diode region are arranged so as to alternate with each other along an extending direction of a trench gate (1/2/3) (see Okuda, Fig.12 as shown above),
the at least one dummy active trench gate (3/2) and the at least one active trench gate (1) are provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer (8/10) and are provided so as to be continuous with an active trench gate (1) applied with the gate potential (30) of the transistor, in the transistor region (see Okuda, Fig.12 as shown above).
Okuda is silent upon explicitly disclosing wherein the trench gate is provided so as to penetrate the transistor region and the diode region in plan view,
the diode region includes a region where the at least one dummy active trench gate is provided and a region where at least one active trench gate provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer is provided, the regions being arranged so as to alternate with each other.
For support see Kamibaba, which teaches a semiconductor device wherein the trench gate (19/27) is provided so as to penetrate the transistor region (11) and the diode region (12/13) in plan view (see Kamibaba, Fig.2 as shown below and ¶ [0009]),
the diode region (12/13) includes a region where the at least one dummy active trench gate (19) is provided and a region where at least one active trench gate (19) provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer (50) is provided, the regions being arranged so as to alternate with each other (see Kamibaba, Fig.1 as shown below and ¶ [0009]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Okuda and Kamibaba to enable the trench gate of the Okuda to be provided so as to penetrate the transistor region and the diode region in plan view and the diode region of Okuda to include a region where the at least one dummy active trench gate to be provided and a region where at least one active trench gate provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer is provided, the regions being arranged so as to alternate with each other as taught by Kamibaba in order to obtain a semiconductor device having excellent electrical characteristics at lower manufacturing cost.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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BITEW A DINKE/Primary Examiner, Art Unit 2812