Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1,2,7,8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al (PG Pub 2020/0303266 A1).
Regarding claim 1, Jeong teaches a ion implanting method for fabricating a semiconductor device structure, comprising: executing a first implanting recipe on a first wafer (test wafer, S174, fig. 10B) to turn a first wafer state of the first wafer to a second wafer state (wafer with implanted ions); collecting (S174) the second wafer state of the first wafer to generate a first set of data; and analyzing (S176) the first set of data by artificial intelligence module (machine learning, paragraph [0029]) and determining whether the first set of data is within or not within a predetermined range; updating and adjusting the first implanting recipe (when the process return from S178 in fig. 10B to S150 for the second time in fig. 1, a new recipe is obtain at S150 this time around, which is a different from the recipe that obtained at S150 the first time), with the artificial intelligence module (machine learning, fig. 1), to generate a second implanting recipe according to the analyzed first set of data (at S110 in fig. 10B before returning to fig. 1) and apply the second implanting recipe on a second wafer (another test wafer, S172, fig. 10B, when the process in fig. 10B starts all over after reinforcement learning in fig. 1) to be processed after the first wafer when the first set of data is not within the predetermined range (return to S110 in fig. 1 from fig. 10B; also see claim 13 of Jeong); and applying the first implanting recipe on the second wafer (device wafer, S178) when the first set of data is within the predetermined range (S178), wherein the second implanting recipe is generated with the artificial intelligence module (actual wafer, 500, tilting angle shown in fig. 7A; and reinforced learning of wafer angle in fig. 7B, paragraph [0080]) taking into consideration at least one of an implanting rate of the second wafer (dose of ion controlled by controller, paragraph [0054]), a rate of rotation of the second wafer, a tilt angle of the second wafer (figs. 7A and 7B, paragraphs [0081] to [0084]), an etching recipe of the first wafer, and a deposition recipe of the first wafer.
Regarding claim 2, Jeong teaches the implanting method of claim 1, further comprising: feeding forward at least one parameter (“criterion”, abstract; S110, paragraph [0025]) of the first implanting recipe to the artificial intelligence module before executing the first implanting recipe on the first wafer.
Regarding claim 7, Jeong teaches the implanting method of claim 1, further comprising: collecting data related to a profile of the second wafer state of the first wafer (paragraphs [0039][0040]).
Regarding claim 8, Jeong teaches the implanting method of claim 1, further comprising: generating the second implanting recipe taking into consideration a feature profile of the second wafer state of the first wafer (paragraphs [0039][0040]).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (PG Pub 2020/0303266 A1) as applied to claim 1 above, and further in view of Bhattacharyya (US Patent 7,457,454 B1).
Regarding claim 3, Jeong remains as applied in claim 1.
Jeong does not teach the implanting method of claim 1, further comprising: collecting the first wafer state of the first wafer to generate a second set of data.
In the same field of endeavor, Bhattacharyya teaches collecting the first wafer state (before ion implantation, column 8, lines 54-57) of the first wafer to generate a second set of data (gray scale value, column 8, lines 54-57), for the benefit of determining if a process has been done correctly and completely (column 1, lines 63-67 and column 2, lines 1-12).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to collect the first wafer state of the first wafer to generate a second set of data for the benefit of determining if a process has been done correctly and completely.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (PG Pub 2020/0303266 A1) as applied to claim 1 above, and further in view of Lee et al (PG Pub 2005/0176225 A1).
Regarding claim 4, Jeong remains as applied in claim 1.
Jeong does not teach measuring a critical dimension of the semiconductor.
In the same field of endeavor, Lee teaches implanting method of claim 1, further comprising: measuring a critical dimension of the semiconductor (a critical dimension of the gate electrode on the semiconductor, paragraph [0011]) for the benefit of adjusting the ion implantation recipe accordingly (paragraph [0011]) to control the static and dynamic performance of a device (paragraph [0005]).
Thus, it would have been obvious to measure a critical dimension of the semiconductor for the benefit of adjusting the ion implantation recipe accordingly to control the static and dynamic performance of a device.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (PG Pub 2020/0303266 A1) as applied to claim 1 above, and further in view of Lee et al (PG Pub 2005/0176225 A1).
Regarding claim 5, Jeong remains as applied in claim 1.
Jeong does not teach collecting electrical characteristics of the second wafer state of the first wafer.
In the same field of endeavor, Steeples teaches collecting electrical characteristics of the second wafer state of the first wafer (paragraphs [0019][0020]), for the benefit of catching errors early to reduce costs of mistakes (paragraph [0004]).
Thus, it would have been obvious to collect electrical characteristics of the second wafer state of the first wafer, for the benefit of catching errors early to reduce costs of mistakes.
Regarding claim 6, Jeong remains as applied in claim 1.
Jeong does not teach collecting electrical characteristics of the second state of the first wafer.
In the same field of endeavor, Steeples teaches collecting electrical characteristics of the second state of the first wafer (paragraphs [0019][0020]), for the benefit of catching errors early to reduce costs of mistakes (paragraph [0004]).
Thus, it would have been obvious to collect electrical characteristics of the second state of the first wafer, for the benefit of catching errors early to reduce costs of mistakes.
Response to Arguments
Applicant's arguments filed August 13, 2025 have been fully considered but they are not persuasive. Applicants argues that (paragraphs three and four, page six, remarks)
However, according to the above disclosure, the new or different recipe obtained after the step of S176 is based on other variable used in reinforcement learning. Jeong does not specifically disclose how to determine the variable modified for being used in reinforcement learning. The variable can be randomly modified for performing reinforcement learning.
In the present invention, generating a second implanting recipe, with the artificial intelligence module, is clearly determined by the analyzed first set of data and taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and a deposition recipe of the first wafer.
In response, Jeong teaches the process condition at S130 (fig. 1) includes angle of incidence of ions (paragraph [0033]; also shown in figs. 7A and 7B). The angle of incidence is the tile angle of the wafer (500, figs. 7A and 7B). In other words, the second recipe is generated (at S150, fig. 1) with the artificial intelligence module (reinforce learn, fig. 1) taking into cons8ideration at least a tilt angle of the second wafer (at step S130 and paragraph [0033]). When returning to fig. 1 from fig. 10B, the first set of date has already been analyzed (at S176, fig. 10B) and has been determined that the ion profile does not meet the box profile.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899