DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 06/18/2026, with respect to the rejection(s) of claim(s) 1-13 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Applicant’s arguments, see remarks, filed 06/18/2026, with respect to the rejection of claims 21, 24-26 and 28-29 under 35 U.S.C. 103 have been fully considered and are persuasive. The rejection of claims 21, 24-26 and 28-29 has been withdrawn.
Claim Objections
Claim 21 is objected to because of the following informalities: The amended version of claim 21 filed on 06/18/2026 is missing an intermediate amendment filed on 04/20/2026, which was entered on 05/05/2026. Appropriate correction is required.
Claim 23 is objected to because of the following informalities: This claim was canceled in the amendment filed on 04/20/2026, which was entered on 05/05/2026. Cancellation of this claim is required.
Claims 24-26 and 28-29 are objected to for depending from objected claim 21.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US-20210098421-A1 – hereinafter Wu) in view of Iwashita et al. (US-20230307396-A1 – hereinafter Iwashita), and further in view of Chuang et al. (US-20220320024-A1 – hereinafter Chuang).
Regarding claim 1, Wu teaches a semiconductor package (Fig.3; ¶0054) comprising:
one or more integrated circuit dies (Fig.3 130; ¶0027);
a back-side redistribution structure (Fig.3 150; ¶0033) on a back-side (top side) of the one or more integrated circuit dies (130), the back-side redistribution structure (150) comprising:
a first dielectric layer (Fig.1D 154 bottom; ¶0033);
a first metal pattern (Fig.1D 152 middle; ¶0033) in the first dielectric layer (154 bottom), wherein a first portion of the first metal pattern (152 middle) is a metal pad (¶0033);
a second dielectric layer (Fig.1D 154 middle; ¶0033) over the first metal pattern (152 middle); and
a second metal pattern (Fig.1D 152 top; ¶0033) in the second dielectric layer (154 middle), wherein the first portion of the first metal pattern (152 middle) is connected to the first portion of the second metal pattern (152 top) by one or more metal vias (metal vias connecting these metal patterns are shown in Fig.3) extending through the second dielectric layer (154 middle); and
a third dielectric layer (Fig.1D 154 top; ¶0033) over the second metal pattern (152 top);
a front-side redistribution structure (Fig.3 110; ¶0020) on the front-side (bottom side) of the one or more integrated circuit dies (130):
an encapsulant (Fig.3 140; ¶0031) surrounding the one or more integrated circuit dies (130): and
one or more through vias (Fig.3 120; ¶0025) extending through the encapsulant (140) and electrically connecting the back-side redistribution structure (150) to the front-side redistribution structure (110).
Wu does not teach wherein a first portion of the second metal pattern is a dummy pad, and wherein the first portion of the first metal pattern, the first portion of the second metal pattern, and the one or more metal vias are electrically isolated from remaining portions of the back-side redistribution structure, and
wherein the width of the one or more metal vias tapers from the metal pad to the dummy pad.
Iwashita teaches interconnection structures (Fig.7 41-43; ¶0054 of Iwashita) having dummy pads (Fig.7 41A; ¶0056 of Iwashita), metal pads (Fig.7 43; ¶0055 of Iwashita) and metal interconnects (Fig.7 42; ¶0054 of Iwashita) between both pads, where these interconnection structures (41-43 of Iwashita) are electrically isolated from the other circuity of the device disclosed in Iwashita (¶0053 of Iwashita).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have added the electrically isolated interconnection structures of Iwashita (41A, 42 and 43 of Iwashita) to the redistribution structures of Wu (152 top and middle of Wu) where the dummy pad (41A of Iwashita) is added to 152 top of Wu and the metal pad (43 of Iwashita) is added to 152 middle of Wu with the metal interconnect (or via, 42 of Iwashita) in-between. A practitioner would be motivated to add these features to the structure disclosed by the primary reference for the benefit of mimicking the physical properties of the non-dummy equivalent components for improved reliability.
Wu in view of Iwashita does not teach wherein the width of the one or more metal vias tapers from the metal pad to the dummy pad.
Chuang teaches tapering vias (Fig.9 54; ¶0020 of Chuang) for connecting a metal pad (Fig.9 60; ¶0022 of Chuang) to a dummy pad (Fig.9 48; ¶0021 of Chuang).
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the metal via is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of coupling a plurality of pads (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Regarding claim 7, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang from claim 1 teaches the semiconductor package of claim 1, further comprising an insulating layer (Fig.3 250; ¶0055 of Wu) over the third dielectric layer (154 top of Wu) and an electrical connector (Fig.1E 208; ¶0038 of Wu) extending through the insulating layer (250 of Wu) and the third dielectric layer (154 top of Wu) to contact the first portion of the second metal pattern (152 top of Wu).
Regarding claim 8, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang from claim 7 teaches the semiconductor package of claim 7, wherein the insulating layer (250 of Wu) comprises a molding compound (¶0031 of Wu).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Chuang, and further in view of Hsieh et al. (US-20210082845-A1 – hereinafter Hsieh).
Regarding claim 2, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang from claim 1 teaches the semiconductor package of claim 1.
The aforementioned combination does not teach wherein the metal pad comprises openings that extend through a thickness of the metal pad.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with the metal pad of Wu in view of Iwashita (a pad of 152 middle of Wu) because said holes can be filled with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 3, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang, and further in view of Hsieh from claim 2 teaches the semiconductor package of claim 2.
The aforementioned combination does not teach wherein the openings are filled in by the first dielectric layer.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh) that are filled with dielectric material (¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to fill the mesh holes of Wu in view of Iwashita and further in view of Hsieh from claim 2 with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 4, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang from claim 1 teaches the semiconductor package of claim 1.
The aforementioned combination does not teach wherein the dummy pad comprises openings that extend through a thickness of the dummy pad.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with the dummy pad of Wu in view of Iwashita (a pad of 152 middle of Wu) because said holes can be filled with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Regarding claim 5, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang, and further in view of Hsieh from claim 4 teaches the semiconductor package of claim 4.
The aforementioned combination does not teach wherein the openings are filled in by the second dielectric layer.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058 of Hsieh) with mesh holes (Fig.7 701; ¶0058 of Hsieh) that are filled with dielectric material (¶0058 of Hsieh).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to fill the mesh holes of Wu in view of Iwashita and further in view of Hsieh from claim 4 with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Chuang, and further in view of Kim et al. (US-20230019311-A1 – hereinafter Kim).
Regarding claim 6, the aforementioned combination of Wu in view of Iwashita, and further in view of Chuang from claim 1 teaches the semiconductor package of claim 1.
The aforementioned combination does not teach wherein the second metal pattern also comprises a power pad, a ground pad, and a signal pad.
Kim teaches redistribution structures that comprise components for power, signal and ground (¶0056 of Kim).
These components are well-known to be part of the conductive redistribution layers within redistribution structures and claiming these components does not patentably distinguish claim 6 over the art of record.
Claim(s) 9 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim et al. (US-20230019311-A1 – hereinafter Kim), and further in view of Jang et al. (US-20170154878-A1 – hereinafter Jang).
Regarding claim 9, Wu teaches a semiconductor package (Fig.3; ¶0054) comprising:
an integrated circuit die (Fig.3 130; ¶0027);
a redistribution structure (Fig.3 150; ¶0033) on a back-side (top side) of the integrated circuit die (130), the redistribution structure (150) comprising:
a first insulating layer (Fig.1D 154 bottom; ¶0033);
a first redistribution pattern (Fig.1D 152 middle; ¶0033) in the first insulating layer (154 bottom);
a second insulating layer (Fig.1D 154 middle; ¶0033) over the first redistribution pattern (152 middle); and
a second redistribution pattern (Fig.1D 152 top; ¶0033) in the second insulating layer (154 middle), wherein the second redistribution pattern (152 top) comprises a plurality of contact pads (¶0033);
a third insulating layer (Fig.1D 154 top; ¶0033) over the second redistribution pattern (152 top); and
a fourth insulating layer (Fig.1D 250; ¶0055) over the third insulating layer (154 top) and contact pad connectors (Fig.1E 208; ¶0038) extending through the third insulating layer (250) and fourth insulating layer (154 top) to contact the plurality of contact pads (¶0033), wherein the fourth insulating layer (250) comprises a molding compound (¶0031), wherein the first insulating layer (154 bottom) is between the integrated circuit die (130) and the fourth insulating layer (250).
Wu does not teach wherein the contact pads are comprising:
signal pads;
power pads;
ground pads; and
dummy pads;
wherein first portions of the first redistribution pattern are connected to the dummy pads by vias extending through the second insulating layer, a first dummy pad of the dummy pads connected to a first portion of the first redistribution pattern by more than two vias;
a heat dissipation system comprising:
the first portions of the first redistribution pattern;
the dummy pads; and
the vias, wherein the heat dissipation system is electrically isolated from circuits of the semiconductor package.
Iwashita teaches interconnection structures (Fig.7 41-43; ¶0054 of Iwashita) having dummy pads (Fig.7 41A; ¶0056 of Iwashita), metal pads (Fig.7 43; ¶0055 of Iwashita) and metal interconnects (Fig.7 42; ¶0054 of Iwashita) between both pads, where these interconnection structures (41-43 of Iwashita) are electrically isolated from the other circuity of the device disclosed in Iwashita (¶0053 of Iwashita).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have added the electrically isolated interconnection structures of Iwashita (41A, 42 and 43 of Iwashita) to the redistribution structures of Wu (152 middle and 152 top of Wu) where the dummy pad (41A of Iwashita) is added to 152 top of Wu and the metal pad (43 of Iwashita) is added to 152 middle of Wu with the metal interconnect (or via, 42 of Iwashita) in-between. A practitioner would be motivated to add these features to the structure disclosed by the primary reference for the benefit of mimicking the physical properties of the non-dummy equivalent components for improved reliability.
Wu in view of Iwashita does not teach wherein the contact pads are comprising:
signal pads;
power pads; and
ground pads.
Kim teaches redistribution structures that comprise components for power, signal and ground (¶0056 of Kim).
These components are well-known to be part of the conductive redistribution layers within redistribution structures and claiming these components does not patentably distinguish claim 6 over the art of record.
Wu in view of Iwashita, and further in view of Kim does not teach wherein a first dummy pad of the dummy pads is connected to a first portion of the first redistribution pattern by more than two vias.
Jang teaches a plurality of vias (Fig.1 352; ¶0142 of Jang) for thermally coupling a first dummy pad (Fig.1 332; ¶0142 of Jang) to a second dummy pad (Fig.1 342; ¶0142 of Jang) within a redistribution pattern (Fig.1 300; ¶0028 of Jang).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the pads of Iwashita (41A and 43 of Iwashita) to be coupled with a plurality of metal vias (352 of Jang) to arrive at the claimed invention. This difference is obvious because it is a matter of design choice (¶0077 of Jang).
Regarding claim 13, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim, and further in view of Jang from claim 9 teaches the semiconductor package of claim 9, wherein the fourth insulating layer (250 of Wu) comprises an epoxy (¶0031 of Wu).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim, and further in view of Jang, and further in view of Pei et al. (US- 20190148262-A1 – hereinafter Pei).
Regarding claim 10, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim, and further in view of Jang from claim 9 teaches the semiconductor package of claim 9.
The aforementioned combination does not teach wherein the plurality of contact pads are disposed on the semiconductor package in an array comprising columns and rows in a top view, and wherein a center region of the array is free of contact pads.
Pei teaches a semiconductor package having contacts in columns and rows having a center region free of contact pads (Fig.12B; ¶0062 of Pei).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply the layout of Pei (Fig.12B of Pei) to the primary reference to save room for other components, like a thermally conductive material (¶0044).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim, and further in view of Jang, and further in view of Park et al. (US- 20110068481-A1 – hereinafter Park).
Regarding claim 11, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim, and further in view of Jang from claim 9 teaches the semiconductor package of claim 9.
The aforementioned combination does not teach wherein the plurality of contact pads are disposed on the semiconductor package in an array comprising columns and rows in a top view, and wherein one or more dummy pads are disposed in a column closest to an edge of the semiconductor package.
Park teaches a semiconductor package having contact pads in an array of columns and rows where the dummy pads are closer to the edge of the semiconductor package (Fig.1D; ¶0066 of Park).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply this layout to the primary reference because dummy components for heat dissipation or structural support are better located near the edge to protect the components closer to the center of the package.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Iwashita, and further in view of Kim, and further in view of Jang, and further in view of Hsieh.
Regarding claim 12, the aforementioned combination of Wu in view of Iwashita, and further in view of Kim, and further in view of Jang from claim 9 teaches the semiconductor package of claim 9.
The aforementioned combination does not teach wherein the dummy pads have openings that extend from top surfaces of the dummy pads to bottom surfaces of the dummy pads.
Hsieh teaches a redistribution layer (Fig.7 509; ¶0058) with mesh holes (Fig.7 701; ¶0058).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the holes of Hsieh (701 of Hsieh) with the dummy pad of Wu in view of Iwashita (a pad of 152 top of Wu) because said holes can be filled with dielectric material to reduce high sidewall peeling stresses and cracks (¶0058 of Hsieh).
Allowable Subject Matter
Claims 21, 24-26 and 28-29 are allowed.
Regarding independent claim 21, the most relevant prior art references US-20210098421-A1 to Wu et al. and US-20230307396-A1 to Iwashita et al. teaches most of the limitations of claim 21, but not the limitations of “wherein the first metal pad and the second metal pad are connected by at least two metal vias extending through the second dielectric layer, the at least two metal vias being laterally offset from the first openings and the second openings in a top-down view” as recited. Therefore, claim 21 is deemed patentable over the prior art.
Claims 24-26 and 28-29 are allowed for depending from allowed claim 21.
Conclusion
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/T.J.K./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
