DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/28/2025 has been entered.
Status of Claims
Claims 1, 2, 4-7, 9-16, and 18-19 have been amended. Claim 8 has been cancelled.
Response to Amendment
The claim amendments presented by the applicant on 10/07/2025 is acknowledged by the examiner, but are insufficient in overcoming the following 35 USC 112 rejections:
The “contact” of claims 1, 7, 12, and 16 has been amended to “hybrid cross-couple contact” and is still claimed as comprising a contact to a gate, a contact to a source, and a contact to a drain of a CMOS device without specifying to which transistors of the CMOS device the gate contact, the source contact, and the drain contact belong to. As claimed, the gate contact, source contact, and drain contact of a single transistor can be interpreted as being connected to the “hybrid cross-couple contact” which comprises the said contacts. For examination purposes, the “contact” is interpreted as a pair of cross couple contacts between two inverter circuits that electrically connects a shared gate of a 1st (2nd ) pull-up and 1st (2nd) pull-down transistor to a shared bottom source/drain contact of a 2nd (1st) pull-up and 2nd (1st) pull-down transistor. Additionally, the examiner interprets the GND contact is any contact that is supplied by a common reference voltage and a word line is a separate connection to a word line as is understood in the art.
Response to Arguments
Applicant's arguments filed 10/07/20 have been fully considered but they are not persuasive. Regarding the 35 USC §103 rejections of Claims 1-19, applicant argues that the amendment to claims 1, 7, 12, and 16 wherein the limitation “a hybrid cross-couple contact” is added, renders the claims allowable as Zhang, Weste, and Doornbos, individually and in combination, do not teach or suggest the added limitation.
However, the examiner submits that the limitation has been considered in a prior office action dated 03/13/2025, where the examiner indicated that the metes and bounds of the term “hybrid cross-couple contact” could not be determined as this term has not been adequately defined in the applicant’s specification and the claim language is unclear in its presentation. As such, reinstatement of the limitation “hybrid cross-couple contact” and the arguments provided do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Furthermore, the applicant traverses the 35 USC § 112 rejection of claims 1, 7, 12, and 16 with regards to limitations “frontside” and “backside.” The applicant alleges that the specifications and the drawings provide enough information to determine the metes and bounds of the limitations “frontside” and “backside.”
However, the applicant fails to demonstrate what the metes and bounds are of the limitations “backside” and “frontside” as allegedly “shown in the figures and described throughout the specifications.” The examiner reiterates that the term “backside” is described in the specs to have varying relational properties. For example, the term backside can refer to either being close to the substrate ([0101] Backside ILD 444 with PDN 448 over BPR 446 as shown in Fig. 4N) or away from the substrate ([0094], Fig. 4K, Backside contact 434). Since the term “backside” is not confined to one particular side of the overall device, the examiner could not determine what counts as “backside” or “frontside.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The independent Claims 1, 7, 12, 16 contain the limitation “Hybrid cross-couple contact” the structure of which is not adequately supported in the specifications and drawings. As claimed, the “hybrid cross-couple contact” is described to act as a conductive element that electrically connects a gate of a complementary metal oxide semiconductor (CMOS) device to a source of the same CMOS device, further connecting to a drain of the said CMOS device. As described, the CMOS device could not be conceived to function as a node for a static random-access memory (SRAM) device. For examination purposes, the “hybrid cross-couple contact” is interpreted as a pair of cross couple contacts between two inverter circuits that electrically connects a shared gate of a 1st (2nd ) pull-up and 1st (2nd) pull-down transistor to a shared bottom source/drain contact of a 2nd (1st) pull-up and 2nd (1st) pull-down transistor.
The independent claim 7 contain the limitation “the hybrid contact.” There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the “hybrid contact” is interpreted to mean “hybrid cross-couple contact.”
Claims 1, 7, 12, and 16 contain the limitation “backside” and “frontside.” According to the applicant’s specifications, the term backside can refer to either being close to the substrate ([0101] Backside ILD 444 with PDN 448 over BPR 446 as shown in Fig. 4N) or away from the substrate ([0094], Fig. 4K, Backside contact 434). For examination purposes, the examiner interprets the term backside as referring to the backside of a carrier substrate or wafer. This includes contacts that may be transferred unto a carrier substrate and flipped over to form a backside contact just as illustrated in Fig. 4K of the applicant’s specifications.
Claims 4-6, 9-11, 13-15, 16-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4-6, 9-11, 13-15, 16-19 contain the limitations “8-way shared GND contact,” “4-way shared VDD contact,” and “4-way shared word line contact,” which as claimed, is determined to be indefinite as it is unclear what part of the SRAM device is sharing the GND, VDD, and word line contacts (transistors, inverters, or memory cells). In accordance with the applicant’s specifications, the examiner interprets the relevant claims as referring to the sharing of contacts between respective memory cells, i.e. memory cells 202-1 U, 202-1 L, 202-2 U, 202-2 L sharing a VDD contact 4-way. The applicant is requested to amend the claims accordingly.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zang et al. (US 20190027483 A1), hereinafter referred to as Zang and in further view of Weste et al. (“CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition” ISBN:978-0-321-54774-3, 2010), hereinafter referred to as Weste.
Regarding the independent claim 1:
Zang discloses A complementary metal oxide semiconductor (CMOS) device comprising that includes a static random access memory (SRAM) device comprising (Zhang [0002]):
a hybrid cross-couple contact, wherein the hybrid cross-couple contact comprises:
a frontside contact to a gate of the CMOS device, wherein the frontside contact is disposed on a frontside of the CMOS device (Zang Fig. 5A, [0078] "The 1st cross-coupled contact 184 is in electrical contact with the 2nd common gate structure 182 of the 2nd inverter 108 1st and the metal contact 159 1st of the inverter," where frontside is interpreted by the examiner as referring to an area above the substrate.);
and a source contact to a source of the CMOS device, wherein the source contact is disposed on a backside of the CMOS device ((Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).).")
and a drain contact to a drain of the CMOS device, wherein the drain contact is disposed on the backside of the CMOS device (Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).).”)
The examiner notes that the term "backside" is interpreted by the examiner according to applicant’s disclosure where the backside can refer to an area behind the substrate or a transfer wafer, while frontside is interpreted to refer to a region above the substrate or a transfer wafer. Therefore, “backside contacts” are interpreted to refer to any electrically conductive contacts that are fabricated behind a substrate, either by direct material deposition unto vias or a flip-chip process, so as to make it possible to electrically connect the “backside contacts” to another interconnect, a landing pad, a larger circuit, etc by flipping the device. Therefore, the CA contacts 163 of Zang can be considered as backside contacts if flipped, similar to backside contacts 434 of Fig. 4K of applicant’s drawings.
The examiner also notes that the disclosure of Zang relates to a single SRAM cell. However, it is understood in the art that SRAM cells are fabricated in arrays with shared contacts (VDD and VSS/GND) and word lines with neighboring cells (Weste pg. 503-504 “Figure 12.13(a) shows a stick diagram of a traditional 6T cell. The cell is designed to be mirrored and overlapped to share VDD and GND lines between adjacent cells along the cell boundary, as shown in Figure 12.13(b)”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to expect that the memory cell of Zang could be configured in an array where the VDD and GND contacts, as well as the word line would be shared by a plurality of memory cells just as taught by Weste (Weste pg. 503-504).
Regarding claim 2: The combined disclosure of Zang and Weste teach the CMOS device of claim 1.
Zang further discloses the device wherein the hybrid cross-couple contact forms a memory node for the SRAM device, and the memory node is configured to serve as a memory storage unit of the SRAM device. (Zang [0079] "The 1st cross-coupled contact 184 completes the formation of the 1st storage node 114 by electrically cross coupling the output 106 (best seen in FIG. 3) of the 1st inverter 102 to the input 110 (best seen in FIG. 3) of the 2nd inverter 108.").
Regarding claim 3: The combined disclosure of Zang and Weste teach the CMOS device of claim 2.
Zang further discloses the device wherein the SRAM device comprises a plurality of backside contacts that wire Vdd and Vss power supplies for the SRAM device from the backside of the CMOS device. (Zang Fig. 5A, [0069] "The S/D region 148 of the 1st PU transistor 144 is electrically connected with a supply voltage 160 (which may be designated herein as Vdd). The S/D region 156 of the 1st PD transistor 146 is electrically connected with a voltage ground 162 (which may be designated herein as Vcc).")
Regarding claim 6: The combined disclosure of Zang and Weste teach the CMOS device of claim 2.
Zang further discloses the device wherein the SRAM device comprises a 4-way shared word line contact wiring to the frontside of the CMOS device. (Zang [0063] "A gate structure 124 of the 1st PG transistor 118 is connected to a word line (WL) 130." Zang [0065] “The gate structure 138 of the 2nd PG transistor 132 is connected to the [word line] WL”)
Just as discussed in the rejection of claim 1, the examiner notes that word lines are known in the art to be shared by multiple memory cells. Therefore a word line shared by four cells is considered to be an obvious variation in the art.
Regarding the independent claim 7:
Zang discloses A complementary metal oxide semiconductor (CMOS) device that includes a static random access memory (SRAM) device (Zang [0002]),
the CMOS device comprising: a hybrid cross-couple contact, wherein the hybrid cross-couple contact comprises: a frontside contact to a gate of the CMOS device, wherein the frontside contact is disposed on a frontside of the CMOS device; (Zang Fig. 5A, [0078] "The 1st cross-coupled contact 184 is in electrical contact with the 2nd common gate structure 182 of the 2nd inverter 108 1st and the metal contact 159 1st of the inverter," where frontside is interpreted by the examiner as referring to an area above the substrate.);
and a plurality of backside contacts that wire Vdd and Vss power supplies for the SRAM device from a backside of the CMOS device ((Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).).")
The examiner notes that the term "backside" is interpreted by the examiner according to applicant’s disclosure where the backside can refer to an area behind the substrate or a transfer wafer, while frontside is interpreted to refer to a region above the substrate or a transfer wafer. Therefore, “backside contacts” are interpreted to refer to any electrically conductive contacts that are fabricated behind a substrate, either by direct material deposition unto vias or a flip-chip process, so as to make it possible to electrically connect the “backside contacts” to another interconnect, a landing pad, a larger circuit, etc by flipping the device. Therefore, the CA contacts 163 of Zang can be considered as backside contacts if flipped, similar to backside contacts 434 of Fig. 4K of applicant’s drawings.
The examiner also notes that the disclosure of Zang relates to a single SRAM cell. However, it is understood in the art that SRAM cells are fabricated in arrays with shared contacts (VDD and VSS/GND) and word lines with neighboring cells (Weste pg. 503-504 “Figure 12.13(a) shows a stick diagram of a traditional 6T cell. The cell is designed to be mirrored and overlapped to share VDD and GND lines between adjacent cells along the cell boundary, as shown in Figure 12.13(b)”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to expect that the memory cell of Zang could be configured in an array where the VDD and GND contacts, as well as the word line would be shared by a plurality of memory cells just as taught by Weste (Weste pg. 503-504).
Regarding claim 11: The combined disclosure of Zang and Weste teach the CMOS device of claim 7.
Zang further discloses the device wherein a word line contact is shared with four cells. (Zang [0063] "A gate structure 124 of the 1st PG transistor 118 is connected to a word line (WL) 130." Zang [0065] “The gate structure 138 of the 2nd PG transistor 132 is connected to the [word line] WL”)
Just as discussed in the rejection of claim 7, the examiner notes that word lines are known in the art to be shared by multiple memory cells. Therefore a word line shared by four cells is considered to be an obvious variation in the art.
Regarding the independent claim 12:
Zang discloses a complementary metal oxide semiconductor (CMOS) device comprising: a contact of a static random-access memory (SRAM) device wherein the SRAM device comprises a plurality of backside contacts that wire Vdd and Vss power supplies for the SRAM device from the backside of the CMOS device. (Zang Fig. 5A, [0069] "The S/D region 148 of the 1st PU transistor 144 is electrically connected with a supply voltage 160 (which may be designated herein as Vdd). The S/D region 156 of the 1st PD transistor 146 is electrically connected with a voltage ground 162 (which may be designated herein as Vcc)." Where the CA contacts 162 can be flipped to form backside contacts similar to the backside contacts 434 of Fig. 4K of applicant’s disclosure.)
and wherein the contact comprises a frontside contact to a gate of the CMOS device, wherein the frontside contact is disposed on a frontside of the CMOS device (Zang Fig. 5A, [0078] "The 1st cross-coupled contact 184 is in electrical contact with the 2nd common gate structure 182 of the 2nd inverter 108 1st and the metal contact 159 1st of the inverter" where the contact 184 has a frontside contact.);
and a source contact to a source of the CMOS device, wherein the source contact is disposed on a backside of the CMOS device ((Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).).")
and a drain contact to a drain of the CMOS device, wherein the drain contact is disposed on the backside of the CMOS device (Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).).”)
and the drain contact is a VDD contact shared with a second plurality of cells and is wired to the backside of the CMOS device (Zang Fig. 5A where the S/D regions are capped by backside CA contacts 163 connected to VDD);
a GND contact shared with a first plurality of cells and wired to the backside of a CMOS device (Zang Fig. 5A where the S/D regions are capped by backside CA contacts 163 connected to VCC also known in the art to carry reference voltage or GND.);
a word line contact shared with a third plurality of cells and wired to the frontside of the CMOS device (Zang Fig. 5A word line contact WL 130 on front side of device.)
The examiner notes that the term "backside" is interpreted by the examiner according to applicant’s disclosure where the backside can refer to an area behind the substrate or a transfer wafer, while frontside is interpreted to refer to a region above the substrate or a transfer wafer. Therefore, “backside contacts” are interpreted to refer to any electrically conductive contacts that are fabricated behind a substrate, either by direct material deposition unto vias or a flip-chip process, so as to make it possible to electrically connect the “backside contacts” to another interconnect, a landing pad, a larger circuit, etc by flipping the device. Therefore, the CA contacts 163 of Zang can be considered as backside contacts if flipped, similar to backside contacts 434 of Fig. 4K of applicant’s drawings.
The examiner also notes that the disclosure of Zang relates to a single SRAM cell. However, it is understood in the art that SRAM cells are fabricated in arrays with shared contacts (VDD and VSS/GND) and word lines with neighboring cells (Weste pg. 503-504 “Figure 12.13(a) shows a stick diagram of a traditional 6T cell. The cell is designed to be mirrored and overlapped to share VDD and GND lines between adjacent cells along the cell boundary, as shown in Figure 12.13(b)”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to expect that the memory cell of Zang could be configured in an array where the VDD and GND contacts, as well as the word line would be shared by a plurality of memory cells just as taught by Weste (Weste pg. 503-504).
Regarding claim 15: The combined disclosure of Zang and Weste teach the CMOS device of claim 12.
Zang further discloses the device wherein the SRAM device comprises a 4-way shared word line contact wiring to the frontside of the CMOS device.. (Zang [0063] "A gate structure 124 of the 1st PG transistor 118 is connected to a word line (WL) 130." Zang [0065] “The gate structure 138 of the 2nd PG transistor 132 is connected to the [word line] WL”)
Just as discussed in the rejection of claim 12, the examiner notes that word lines are known in the art to be shared by multiple memory cells. Therefore a word line shared by four cells is considered to be an obvious variation in the art.
Claims 4-5, 9-10, 13-19 are rejected under 35 U.S.C. 103 as being unpatentable by Zang in further view Weste and in further view of Doornbos et al. (US 11004789 B2), hereinafter referred to as Doornbos.
Regarding claim 4: The combined disclosure of Zang and Weste teach the CMOS device of claim 2.
Zang fails to teach the device, wherein the GND contact is shared with 8 cells
The examiner notes that this is because the disclosure of Zang only discloses a single SRAM memory cell.
As discussed in the rejection of claim 1, Weste teaches that SRAM memory cells are designed to be mirrored and overlapped to share GND lines between memory cells.
In a related field of manufacturing semiconductor devices, Doornbos, teaches a method of fabricating a semiconductor device with a back side power supply circuit (including ground connection) that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VSS with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VSS line an obvious variation in the art, rendering the 8-way shared ground contact for eight memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared ground and power supply contacts. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of devices allowing for greater control of the device power dissipation thereby reducing device power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 5: The combined disclosure of Zang and Weste teach the CMOS device of claim 2.
Zang fails to teach the device, wherein the SRAM device comprises a VDD contact shared with 4 cells. This is because Zang’s disclosure focuses on a single memory cell but is understood to be a part of a network of memory cells as known in the art.
As discussed in the rejection of claim 1, Weste teaches that SRAM memory cells are designed to be mirrored and overlapped to share VDD contacts between memory cells.
In a related field of manufacturing semiconductor devices, Doornbos teaches a method of fabricating a semiconductor device with a back side power supply circuit (which includes a shared VDD contact), that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VVDD with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VVDD line an obvious variation in the art, rendering the 4-way shared VDD contact for four memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention, would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared power supply contacts VDD and/or VVDD. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of semiconductor devices allowing for greater control of the device power dissipation which reduces power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 9: The combined disclosure of Zang and Weste teach the CMOS device of claim 7.
Zang fails to teach the device, wherein the SRAM device comprises an 8-way shared GND contact wiring to the backside of the CMOS device
The examiner notes that this is because the disclosure of Zang only discloses a single SRAM memory cell.
As discussed in the rejection of claim 7, Weste teaches that SRAM memory cells are designed to be mirrored and overlapped to share GND lines between memory cells.
In a related field of manufacturing semiconductor devices, Doornbos, teaches a method of fabricating a semiconductor device with a back side power supply circuit (including ground connection) that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VSS with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VSS line an obvious variation in the art, rendering the 8-way shared ground contact for eight memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared ground and power supply contacts. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of devices allowing for greater control of the device power dissipation thereby reducing device power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 10: Zang The combined disclosure of Zang and Weste teach the CMOS device of claim 7.
Zang fails to teach the device, wherein the SRAM device comprises a 4-way shared VDD contact wiring to the backside of the CMOS device.. This is because Zang’s disclosure focuses on a single memory cell but is understood to be a part of a network of memory cells as known in the art.
As discussed in the rejection of claim 7, Weste teaches that SRAM memory cells are designed to be mirrored and overlapped to share VDD contacts between memory cells.
In a related field of manufacturing semiconductor devices, Doornbos teaches a method of fabricating a semiconductor device with a back side power supply circuit (which includes a shared VDD contact), that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VVDD with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VVDD line an obvious variation in the art, rendering the 4-way shared VDD contact for four memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention, would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared power supply contacts VDD and/or VVDD. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of semiconductor devices allowing for greater control of the device power dissipation which reduces power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 13: The combined disclosure of Zang and Weste teach the CMOS device of claim 12.
Zang fails to teach the device, wherein the SRAM device comprises an 8-way shared GND contact wiring to the backside of the CMOS device.
The examiner notes that this is because the disclosure of Zang only discloses a single SRAM memory cell.
As discussed in the rejection of claim 12, Weste teaches that SRAM memory cells are designed to be mirrored and overlapped to share GND lines between memory cells.
In a related field of manufacturing semiconductor devices, Doornbos, teaches a method of fabricating a semiconductor device with a back side power supply circuit (including ground connection) that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VSS with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VSS line an obvious variation in the art, rendering the 8-way shared ground contact for eight memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared ground and power supply contacts. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of devices allowing for greater control of the device power dissipation thereby reducing device power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 14: The combined disclosure of Zang and Weste teach the CMOS device of claim 12.
Zang fails to teach the device, he SRAM device comprises a 4-way shared VDD contact wiring to the backside of the CMOS device. This is because Zang’s disclosure focuses on a single memory cell but is understood to be a part of a network of memory cells as known in the art.
As discussed in the rejection of claim 12, Weste teaches that SRAM memory cells are designed to be mirrored and overlapped to share VDD contacts between memory cells.
In a related field of manufacturing semiconductor devices, Doornbos teaches a method of fabricating a semiconductor device with a back side power supply circuit (which includes a shared VDD contact), that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VVDD with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VVDD line an obvious variation in the art, rendering the 4-way shared VDD contact for four memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention, would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared power supply contacts VDD and/or VVDD. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of semiconductor devices allowing for greater control of the device power dissipation which reduces power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding the independent claim 16:
Zang discloses a complementary metal oxide semiconductor (CMOS) device comprising: a hybrid cross-couple contact, wherein the hybrid cross-couple contact form a memory node for a static random access memory (SRAM) device wherein the memory node is configured to serve as a memory storage unit of the SRAM device, and wherein the SRAM device comprises a GND contact wiring to a backside of the CMOS device (Zang Fig. 5A where the S/D regions are capped by backside CA contacts 163 connected to VCC also known in the art to carry reference voltage or GND.);,
and wherein the hybrid cross-couple contacts comprises (Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).");
a frontside contact to a gate of the CMOS device, wherein the frontside contact is disposed on a frontside of the CMOS device (Zang Fig. 5A, 5C [0078] "The 1st cross-coupled contact 184 is in electrical contact with the 2nd common gate structure 182 of the 2nd inverter 108 1st and the metal contact 159 1st of the inverter", where the contact 184 has a frontside contact.);
and a source contact to a source of the CMOS device, wherein the source contact is disposed on a backside of the CMOS device ((Zang [0066] "The 1st inverter 102 of SRAM cell 100 commonly includes … pull-up (PU) transistor 144 and … pull-down (PD) transistor 146. The 1st PU transistor 144 has a S/D region 148 (which functions herein as a source region) and a S/D region 150 (which functions herein as a drain region)." Zang Fig. 5A [0067] "The S/D region 150 of the 1st PU transistor 144 is electrically connected to the S/D region 154 of the 1st PD transistor 146 through a 1st metal contact 159");
and a drain contact to a drain of the CMOS device, wherein the drain contact is disposed on the backside of the CMOS device (ibid).
and a drain contact to a drain of the CMOS device, wherein the drain contact is disposed on the backside of the CMOS device (Zang [0051] " Disposed over each upper S/D region 32 are CA contacts 34 that connect to external electrical sources such as bit lines, word lines, voltage sources and voltage grounds (not shown).).”)
wherein the drain contact is a VDD contact shared with a second plurality of cells and is wired to the backside of the CMOS device (Zang Fig. 5A where the S/D regions are capped by backside CA contacts 163 connected to VDD);
Zang fails to teach the device, wherein the SRAM device comprises a GND contact shared with a first plurality of cells. The examiner notes that this is because the disclosure of Zang only discloses a single SRAM memory cell.
However, in a related field of manufacturing semiconductor devices, Doornbos teaches a method of fabricating a semiconductor device with a back side power supply circuit (including ground connection) that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VSS with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VSS line an obvious variation in the art, rendering the 8-way shared ground contact for eight memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared ground and power supply contacts. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of devices allowing for greater control of the device power dissipation thereby reducing device power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 17: The combined disclosure of Zang and Doornbos disclose the CMOS device of claim 16.
Zang further discloses the device wherein the SRAM device comprises a plurality of backside contacts that wire Vdd and Vss power supplies for the SRAM device from the backside of the CMOS device. (Zang Fig. 5A, [0069] "The S/D region 148 of the 1st PU transistor 144 is electrically connected with a supply voltage 160 (which may be designated herein as Vdd). The S/D region 156 of the 1st PD transistor 146 is electrically connected with a voltage ground 162 (which may be designated herein as Vcc).")
Regarding claim 18: The combined disclosure of Zang and Doornbos disclose the device of claim 16.
Zang fails to teach the device, wherein the SRAM device comprises a 4-way shared VDD contact wiring to the backside of the CMOS device. This is because Zang’s disclosure focuses on a single memory cell but is understood to be a part of a network of memory cells as known in the art.
In a related field of manufacturing semiconductor devices, Doornbos teaches a method of fabricating a semiconductor device with a back side power supply circuit (which includes a shared VDD contact), that is shared by multiple standard cells (STDC), i.e. memory cells, as shown in Fig. 1 (Doornbos Col.3 Line 8 "As shown in FIG. 1, the local power supply lines VVDD and/or VVSS are divided into a plurality of local power supply lines, to each of which one or more standard cells (STDC) are connected, as a cell block."). Furthermore, Fig. 2A shows a continuous line for VVDD with multiple through-silicon via (TSV 100) that correspond to each individual STDC i.e. a memory cell. The examiner considers the number STDC connected to the VVDD line an obvious variation in the art, rendering the 4-way shared VDD contact for four memory cells as being obvious in view of Doornbos.
A person having ordinary skill in the art, prior to the effective filing date of the claimed invention, would have been motivated to apply the teaching of Doornbos to the device of Zang, in order to wire multiple memory cells with shared power supply contacts VDD and/or VVDD. This is obvious to try because Doornbos teaches that this configuration allows for the management of entire blocks of semiconductor devices allowing for greater control of the device power dissipation which reduces power consumption (Doornbos Col. 3 Line 16 “The power consumption is reduced by turning-off the header/footer switch coupled to a non-active functional circuit in the semiconductor device”).
Regarding claim 19: The combined disclosure of Zang and Doornbos disclose the device of claim 16.
Zang further discloses the SRAM device comprises a 4-way shared word line contact wiring to the frontside of the CMOS device. (Zang [0063] "A gate structure 124 of the 1st PG transistor 118 is connected to a word line (WL) 130." Zang [0065] “The gate structure 138 of the 2nd PG transistor 132 is connected to the [word line] WL”)
The examiner notes that word lines are known in the art to be shared by multiple memory cells. Therefore a 4-way shared word line is considered to be an obvious variation in the art.
Conclusion
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/EMILIO ARDEO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899