Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 20, 2025. Claims 1-18 are examined below. Including new claims 21-28.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Traynor et al. (US-20200071160-A1 referred as Traynor) in view of Ouderkirk et al. (US-11243333-B1 referred as Ouderkirk).
Regarding claim 1. Traynor discloses a semiconductor structure, comprising: a semiconductor device substrate ([0047], figure 1, the semiconductor device substrate #14); and
an auxetic microstructure located in or over the semiconductor device substrate and comprising an auxetic matrix having a negative Poisson's ratio ([[0022], figure 1, the auxetic microstructure #12 is seen located in the semiconductor device #14 containing an auxetic pattern. It is known in the art that patterned auxetic material contains negative Poission’s ratio (see attached abstract of non patent literature to Lee et al. – but also other documentation correlates the negative Poission’s ratio to auxetic materials). The auxetic microstructure #12 makes up to be an auxetic matrix #20 the combination of all the pattern elements broadly form a matrix – see also [0047]).
Traynor lacks a semiconductor device substrate comprising a semiconductor material having electrical conductivity in the range from 1.0 x 10^-6 S/cm to 1.0 x 10^5 S/cm.
Ouderkirk discloses a semiconductor device substrate comprising a semiconductor material having electrical conductivity in the range from 1.0 x 10^-6 S/cm to 1.0 x 10^5 S/cm ([col 6 lines 12-15], figure 1, a semiconductor device substrate #130 comprises of semiconductor material (more specifically, germanium). It is a known fact that germanium has a conductivity of 0.0047 S/cm which resides within the claimed range above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Traynor to include a semiconductor device substrate comprising a semiconductor material having electrical conductivity as taught by Ouderkirk in order to provide enhance structural integrity, reduce manufacturing costs, and to provide for additional device versatility.
Regarding claim 2. Traynor as modified discloses wherein the auxetic matrix comprises a continuously extending structure with a plurality of openings therethrough ([0083], figure 9, the auxetic matrix #20 comprises of the auxetic structure #300 which is continuously extending with a plurality of openings as it relates to the microstructure formed according to the invention).
Regarding claim 3. Traynor as modified discloses further comprising at least one of a plurality of fill material portions or cavities embedded within the plurality of openings in the auxetic matrix ([0047], figure 1, the plurality of fill material portions #14 is seen filling in the openings in the auxetic matrix).
Regarding claim 4. Traynor as modified discloses wherein the auxetic matrix comprises a first material and the fill material portions comprise a second material different from the first material ([0047, 0049], the auxetic matrix consists of a first material #14 (resin) which is different than the second material #12 (nickel)).
Regarding claim 5. Traynor as modified discloses wherein the semiconductor device substrate comprises a semiconductor substrate containing the semiconductor material and the auxetic matrix ([0047], figure 1, the semiconductor device substrate comprises of a semiconductor substrate #14 containing the auxetic matrix #).
Traynor as modified lacks wherein the auxetic matrix comprises a portion of the semiconductor material.
Ouderkirk discloses wherein the auxetic matrix comprises a portion of the semiconductor material (figure 1, the auxetic matrix #155 (seen formed as a matrix in figure 6) can be seen over the semiconductor substrate #130. In a embodiment, the auxetic matrix #155 comprises a portion of the semiconductor material (more specifically polymer as described in [col 6 line 51 – col 7 line 1], which is the same material used for the semiconductor substrate #130 containing the semiconductor material (more specifically polymer as described in [col 5 lines 53-68])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Traynor as modified to include the auxetic matrix comprises a portion of the semiconductor material as taught by Ouderkirk in order to increase the manufacturing speed, reduce manufacturing costs with less total materials, and to increase the devices lifetime.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Traynor et al. (US-20200071160-A1 referred as Traynor) and Ouderkirk et al. (US-11243333-B1 referred as Ouderkirk), in further view of Otsu et al. (US-20200402992-A1 referred as Otsu).
Regarding claim 7. Traynor as modified lacks further comprising semiconductor devices located over a top side of the semiconductor substrate, wherein the auxetic matrix is located in the top side of the semiconductor substrate.
Otsu discloses further comprising semiconductor devices located over a top side of the semiconductor substrate, wherein the auxetic matrix is located in the top side of the semiconductor substrate ([0260], figure 23D, the semiconductor devices which include regions #400, #200, and #100 are seen over a topside of the semiconductor substrate #8. The auxetic matrix is located above the topside of the semiconductor substrate #8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Traynor to semiconductor devices on top of the substrate as taught by Otsu in order to provide enhanced structural support, increased integration and provide thermal management.
Regarding claim 9. Traynor as modified lacks further comprising semiconductor devices located over the semiconductor device substrate.
Otsu discloses further comprising semiconductor devices located over the semiconductor device substrate ([0260], figure 23D, the semiconductor devices which include regions #400, #200, and #100 are seen over a topside of the semiconductor substrate #8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Traynor to semiconductor devices on top of the substrate as taught by Otsu in order to provide enhanced structural support, increased integration and provide thermal management.
Response to Amendment
Applicant's arguments filed 12/29/2025 have been fully considered: see below for explanations.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
For claims 1 and 5 .... "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Traynor et al. in combination with newly cited reference to Ouderkirk et al. has been presented with regard to claim 1 and 5."
Allowable Subject Matter
Claims 6, 8, 11, and 21-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Noting the prior art does not each or render obvious the limitations of claims 1, 8, and 11 in combination with all claims they depend from. While claims 21-28 further limit claim 11, and would be considered allowable if claim 11 was rewritten in independent form.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818