DETAILED ACTION
This Office action responds to Applicant’s amendments filed on 11/26/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-4, 6-13, 15-20. Claims 5 and 14 are cancelled by the Applicant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 6, 9-11, 13, 15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over by Ho (KR 20150111413) in view of Zhang (US 2007/0246817) in further view of Seo (US 2021/0320077).
Regarding claim 1, Ho (see, e.g., Ho: figs. 1, 2a-2d, and 3) shows most aspects of the instant invention including a semiconductor system fabrication method, comprising:
Forming a patterned mask 210 upon a first integrated circuit (IC) package 200/206
The patterned mask 210 comprising a trench 208/212 that exposes at least a portion of a wiring contact 204 and a portion of an external surface of the first IC package 200/206
wherein forming the patterned mask 210 comprises:
Forming a patterned layer 210 upon the wiring contact 204 and the external surface of the first IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming the trench 208/212 within the patterned layer 210 see, e.g., Ho: figs. 1, 2a-2d, and 3)
Retaining one or more portions from a plurality of portions of the patterned layer 210 to form the patterned mask 210
Forming a contact pad 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206
Forming a solder bump 216 within the trench 208/212 upon the contact pad 214
A top surface of the contact pad 214 is recessed below a top surface of the patterned mask 210
Ho, however, fails (see, e.g., Ho: figs. 1, 2a-2d, and 3) to specify the method step of thinning the patterned mask 210, subsequent to forming the solder bump 216. Zhang, in a method to Ho, teaches (see, e.g., Zhang: figs. 4-8) the method step of thinning the patterned mask 502/204, a method step that is subsequent to the method step of forming the solder bump 206 (see, e.g., Zhang: par. [0022]). Zhang also shows that the method step of thinning the patterned mask 502/204 is to expose the sidewalls of the solder pillar for contact with further deposited layers 208 (see, e.g., Zhang: par. [0023])
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of thinning of the patterned mask (subsequent to the forming of the solder bump) of Zhang in the semiconductor system fabrication method of Ho to expose the sidewalls of the solder pillar for contact with further deposited layers.
Ho in view of Zhang shows (see, e.g., Zhang: figs. 4-8) the method steps of:
Forming an adhesion layer 208 (see, e.g., Zhang: par. [0018], element 208 is a molding compound) upon the thinned patterned mask 204
Planarizing the adhesion layer 208 and the solder bump 206
Ho in view of Zhang, however, fails to show (see, Ho: e.g., figs. 1, 2a-2d, and 3, and also see, e.g., Zhang: figs. 4-8) the method step of joining the first IC package 200/206 with a second IC package by connecting the contact pad 214 of the first IC package 200/206 with a contact pad of the second IC package with the solder bump 216 and by connecting the patterned mask 204 of the first IC package with a dielectric layer of the second IC package with the adhesion layer 208. Seo, in a similar method to Ho in view of Zhang, shows (see, e.g., Seo: fig. 5A) the method step of joining the first IC package 200 with a second IC package 110 by connecting the contact pad 210 of the first IC package 200 with a contact pad 140 of the second IC package 110 with the solder bump 155 and by connecting the patterned mask 160 of the first IC package 200 with a dielectric layer 120 of the second IC package 110 with the adhesion layer 130. Seo further shows that the method step of joining the first IC package 200 with a second IC package 110 is to provide a semiconductor package for a semiconductor apparatus (see, e.g., Seo: par. [0027]).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of joining the first IC package with a second IC package of Seo in the semiconductor system fabrication method of Ho in view of Zhang to provide a semiconductor package for a semiconductor apparatus.
Also, Ho in view of Zhang in view of Seo shows (see, e.g., Seo: figs. 4A) that the patterned layer 180 is a resist layer see, e.g., Seo: par. [0048]).
Regarding claim 2, Ho in view of Zhang in view of Seo (see, e.g., Zhang: figs. 4-8) shows that the method step of thinning the patterned mask 502/204 comprises exposing the top portion of a sidewall of the solder bump 206.
Regarding claim 4, Ho in view of Zhang in view of Seo shows the method steps of:
Forming a contact pad 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming a first metal layer 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming a second metal layer 151 within the trench upon the first metal layer 140 (see, e.g., Seo: fig. 1C)
Regarding claim 6, Ho in view of Zhang in view of Seo shows (see, e.g., Seo: fig. 1C) that the wiring contact 127 is electrically connected to a microdevice 121 within the first IC package 110 by wiring.
Regarding claim 9, Ho in view of Zhang in view of Seo shows (see, e.g., Seo: fig. 1C) that the solder bump 155 is a tin alloy solder bump 155 (see, e.g., Seo: par. 0036]).
Regarding claim 10, Ho (see, e.g., Ho: figs. 1, 2a-2d, and 3) shows most aspects of the instant invention including a semiconductor system fabrication method, comprising:
Forming a patterned mask 210 upon a first integrated circuit (IC) package 200/206
The patterned mask 210 comprising a trench 208/212 that exposes at least a portion of a wiring contact 204 and a portion of an external surface of the first IC package 200/206
wherein forming the patterned mask 210 comprises:
Forming a patterned layer 210 upon the wiring contact 204 and the external surface of the first IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming the trench 208/212 within the patterned layer 210 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Retaining one or more portions from a plurality of portions of the patterned layer 210 to form the patterned mask 210
Forming a contact pad 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206
Forming a solder bump 216 within the trench 208/212 upon the contact pad 214
A top surface of the contact pad 214 is recessed below a top surface of the patterned mask 210
Ho, however, fails (see, e.g., Ho: figs. 1, 2a-2d, and 3) to specify the method step of thinning the patterned mask 210, subsequent to forming the solder bump 216. Zhang, in a method to Ho, teaches (see, e.g., Zhang: figs. 4-8) the method step of thinning the patterned mask 502/204, a method step that is subsequent to the method step of forming the solder bump 206 (see, e.g., Zhang: par. [0022]). Zhang also shows that the method step of thinning the patterned mask 502/204 is to expose the sidewalls of the solder pillar for contact with further deposited layers 208 (see, e.g., Zhang: par. [0023])
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of thinning of the patterned mask (subsequent to the forming of the solder bump) of Zhang in the semiconductor system fabrication method of Ho to expose the sidewalls of the solder pillar for contact with further deposited layers.
Ho in view of Zhang shows (see, e.g., Zhang: figs. 4-8) the method steps of:
Forming an adhesion layer 208 (see, e.g., Zhang: par. [0018], element 208 is a molding compound) upon the thinned patterned mask 204
Planarizing the adhesion layer 208 and the solder bump 206
However, Ho in view of Zhang fails to show (see, e.g., Ho: figs. 1, 2a-2d, and 3) that the patterned layer 210 is a resist layer. Ho in view of Zhang is silent that the patterned layer 210 is a resist layer. Ho in view of Zhang specify that the patterned layer 210 is a solder mask 208 (see, e.g., Ho: figs. 1, 2a-2d, and 3). Seo, in a similar method to Ho in view of Zhang, shows (see, e.g., Seo: fig. 4A) a patterned layer 180 that is made of resist (see, e.g., Seo: par. [0048]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the solder mask layer of Ho in view of Zhang or resist layer of Seo because these were recognized in the semiconductor art for their use as solder mask layers in semiconductor structures, as taught by Ho in view of Zhang and by Seo, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 11, Ho in view of Zhang in view of Seo (see, e.g., Zhang: figs. 4-8) shows that the method step of thinning the patterned mask 502/204 comprises exposing the top portion of a sidewall of the solder bump 206.
Regarding claim 13, Ho in view of Zhang in view of Seo shows that most aspects of the instant invention including the method steps of:
Forming a contact pad 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming a first metal layer 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming a second metal layer 151 within the trench upon the first metal layer 140 (see, e.g., Ho: figs. 1, 2a-2d, and 3, and see, e.g., Seo: par. [0033]).
Regarding claim 15, Ho in view of Zhang in view of Seo shows that most aspects of the instant invention including a wiring contact 204 and the first IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3).
Ho in view of Zhang in view of Seo shows see, e.g., Seo: fig. 1C) that the wiring contact 127 is electrically connected to a microdevice 121 within the first IC package 110 by wiring (see, e.g., Seo: par. [0007]).
Regarding claim 18, Ho in view of Zhang shows (see, e.g., Ho: figs. 1, 2a-2d, and 3) most aspects of the instant invention including a solder bump 216 within the trench 208/212 upon the contact pad 214.
Ho in view of Zhang in view of Seo shows (see, e.g., Seo: fig. 1C) that the solder bump 155 comprises tin alloy (see, e.g., Seo: par. 0036]).
Regarding claim 19, Ho (see, e.g., Ho: figs. 1, 2a-2d, and 3) shows most aspects of the instant invention including a semiconductor system fabrication method, comprising:
Forming a patterned mask 210 upon a first integrated circuit (IC) package 200/206
The patterned mask 210 comprising a trench 208/212 that exposes at least a portion of a wiring contact 204 and a portion of an external surface of the first IC package 200/206
wherein forming the patterned mask 210 comprises:
Forming a patterned layer 210 upon the wiring contact 204 and the external surface of the first IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming the trench 208/212 within the patterned layer 210 see, e.g., Ho: figs. 1, 2a-2d, and 3)
Retaining one or more portions from a plurality of portions of the patterned layer 210 to form the patterned mask 210
Forming a contact pad 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206
Forming a solder bump 216 within the trench 208/212 upon the contact pad 214
A top surface of the contact pad 214 is recessed below a top surface of the patterned mask 210
Ho, however, fails (see, e.g., Ho: figs. 1, 2a-2d, and 3) to specify the method step of thinning the patterned mask 210. Zhang, in a method to Ho, teaches (see, e.g., Zhang: figs. 4-8) the method step of thinning the patterned mask 502/204 (see, e.g., Zhang: par. [0022]). Zhang also shows that the method step of thinning the patterned mask 502/204 is to expose the sidewalls of the solder pillar for contact with further deposited layers 208 (see, e.g., Zhang: par. [0023])
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of thinning of the patterned mask of Zhang in the semiconductor system fabrication method of Ho to expose the sidewalls of the solder pillar for contact with further deposited layers.
Ho in view of Zhang shows (see, e.g., Zhang: figs. 4-8) the method steps of:
Forming an adhesion layer 208 (see, e.g., Zhang: par. [0018], element 208 is a molding compound) upon the thinned patterned mask 204
Planarizing the adhesion layer 208 and the solder bump 206
Ho in view of Zhang, however, fails to show (see, Ho: e.g., figs. 1, 2a-2d, and 3, and also see, e.g., Zhang: figs. 4-8) the method step of joining the first IC package 200/206 with a second IC package by connecting the contact pad 214 of the first IC package 200/206 with a contact pad of the second IC package with the solder bump 216 and by connecting the patterned mask 204 of the first IC package with a dielectric layer of the second IC package with the adhesion layer 208. Seo, in a similar method to Ho in view of Zhang, shows (see, e.g., Seo: fig. 5A) the method step of joining the first IC package 200 with a second IC package 110 by connecting the contact pad 210 of the first IC package 200 with a contact pad 140 of the second IC package 110 with the solder bump 155 and by connecting the patterned mask 160 of the first IC package 200 with a dielectric layer 120 of the second IC package 110 with the adhesion layer 130. Seo further shows that the method step of joining the first IC package 200 with a second IC package 110 is to provide a semiconductor package for a semiconductor apparatus (see, e.g., Seo: par. [0027]).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of joining the first IC package with a second IC package of Seo in the semiconductor system fabrication method of Ho in view of Zhang to provide a semiconductor package for a semiconductor apparatus.
Also, Ho in view of Zhang in view of Seo shows (see, e.g., Seo: figs. 4A) that the patterned layer 180 is a resist layer see, e.g., Seo: par. [0048]).
Claims 3, 12, and 20, are rejected under 35 U.S.C. 103 as being unpatentable over by Ho in view of Zhang in view of Seo in further view of Test (US 2006/0249821).
Regarding claims 3 and 20, Ho in view of Zhang in view of Seo (see, e.g., Zhang: figs. 4-8) shows that most aspects of the instant invention including an adhesion layer 208 (see, e.g., Zhang: par. [0018], element 208 is a molding compound).
However, Ho in view of Zhang in view of Seo fails to show (see, e.g., Zhang: figs. 4-8) that the adhesion layer 208 is a low-modulus adhesion layer. Ho in view of Zhang in view of Seo is silent that the adhesive layer has a low-modulus. Ho in view of Zhang in view of Seo specify that the adhesive layer has a molding compound 208 (see, e.g., Zhang: par. [0018]). Test, in a similar method to Ho in view of Zhang in view of Seo, shows (see, e.g., Test: fig. 3) an adhesive layer 340 that has a stress-reducing low-modulus material and is formed as a layer between the protective layer 320, and thus the substrate 310, and the conductive layer 330.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the molding-compounded adhesive layer of Ho in view of Zhang in view of Seo or the stress-reducing low-modulus of Test because these were recognized in the semiconductor art for their use as adhesive/protective layers in semiconductor structures, as taught by Ho in view of Zhang in view of Seo and by Test, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 12, Ho in view of Zhang in view of Seo (see, e.g., Zhang: figs. 4-8) shows that most aspects of the instant invention including an adhesion layer 208 (see, e.g., Zhang: par. [0018], element 208 is a molding compound).
However, Ho in view of Zhang in view of Seo fails to show (see, e.g., Zhang: figs. 4-8) that the adhesion layer 208 is a low-modulus adhesion layer. Ho in view of Zhang in view of Seo is silent that the adhesive layer has a low-modulus. Ho in view of Zhang in view of Seo specify that the adhesive layer has a molding compound 208 (see, e.g., Zhang: par. [0018]). Test, in a similar method to Ho in view of Zhang in view of Seo, shows (see, e.g., Test: fig. 3) an adhesive layer 340 that has a stress-reducing low-modulus material and is formed as a layer between the protective layer 320, and thus the substrate 310, and the conductive layer 330.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the molding-compounded adhesive layer of Ho in view of Zhang in view of Seo or the stress-reducing low-modulus of Test because these were recognized in the semiconductor art for their use as adhesive/protective layers in semiconductor structures, as taught by Ho in view of Zhang in view of Seo and by Test, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over by Ho in view of Zhang in view of Seo in further view of Fu (US 2012/0193788).
Regarding claim 7, Ho in view of Zhang in view of Seo (see, e.g., Seo: fig. 5A) shows that most aspects of the instant invention including the method step of connecting the contact pad 210 of the first IC package 200 with the contact pad 140 of the second IC package 110 with the solder bump 155.
However, Ho in view of Zhang in view of Seo fails to show (see, e.g., Seo: fig. 5A) the method step of reflowing the solder bump 155 and wetting the solder bump 155 to the contact pad 210 of the first IC package 200 and the contact pad 140 of the second IC package 110. Fu, in a similar method to Ho in view of Zhang in view of Seo, shows (see, e.g., Fu: fig. 2) the method step of reflowing the solder bump 100 and wetting the solder bump 100 to the contact pad 120 of the first IC package 35 and the contact pad 90 of the second IC package 13. Fu further shows that the method step of reflowing the solder bump 100 and wetting the solder bump 100 to the contact pad 120 of the first IC package 35 and the contact pad 90 of the second IC package 13 is to establish metallurgical bonds between the contact pads and the solder structures (see, e.g., Fu: par. 0037]).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of reflowing and wetting the solder bump to the contact pads of the first and second IC packages of Fu in the semiconductor system fabrication method of Ho in view of Zhang in view of Seo to establish metallurgical bonds between the contact pads and the solder structures.
Regarding claim 16, Ho in view of Zhang in view of Seo (see, e.g., Ho: figs. 1, 2a-2d, and 3) shows that most aspects of the instant invention the method step of forming a contact pad 214 within the trench 208/212 upon the exposed portion of the wiring contact 204 and upon the exposed portion of the external surface of the IC package 200/206
Ho in view of Zhang in view of Seo shows (see, e.g., Seo: fig. 5A) the method step of joining the first IC package 200 with a second IC package 110 by connecting the contact pad 210 of the first IC package 200 with a contact pad 140 of the second IC package 110 with the solder bump 155 and by connecting the patterned mask 160 of the first IC package 200 with a dielectric layer 120 of the second IC package 110 with the adhesion layer 130. Seo further shows that the method step of joining the first IC package 200 with a second IC package 110 is to provide a semiconductor package for a semiconductor apparatus (see, e.g., Seo: par. [0027]).
However, Ho in view of Zhang in view of Seo fails to show (see, e.g., Seo: fig. 5A) the method step of reflowing the solder bump 155 and wetting the solder bump 155 to the contact pad 210 of the first IC package 200 and the contact pad 140 of the second IC package 110. Fu, in a similar method to Ho in view of Zhang in view of Seo, shows (see, e.g., Fu: fig. 2) the method step of reflowing the solder bump 100 and wetting the solder bump 100 to the contact pad 120 of the first IC package 35 and the contact pad 90 of the second IC package 13. Fu further shows that the method step of reflowing the solder bump 100 and wetting the solder bump 100 to the contact pad 120 of the first IC package 35 and the contact pad 90 of the second IC package 13 is to establish metallurgical bonds between the contact pads and the solder structures (see, e.g., Fu: par. 0037]).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of reflowing and wetting the solder bump to the contact pads of the first and second IC packages of Fu in the semiconductor system fabrication method of Ho in view of Zhang in view of Seo to establish metallurgical bonds between the contact pads and the solder structures.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over by Ho in view of Zhang in view of Seo in further view of Aoki (US 2016/0056116).
Regarding claim 8, Ho in view of Zhang in view of Seo (see, e.g., Ho: figs. 1, 2a-2d, and 3) shows that most aspects of the instant invention including the method step of forming the solder bump 216 within the trench 208/212 upon the contact pad 214.
However, Ho in view of Zhang in view of Seo fails to show (see, e.g., Ho: figs. 1, 2a-2d, and 3) the method step of injecting molten solder 216 within the trench 208/212 upon the contact pad 214. Aoki, in a similar method to Ho in view of Zhang in view of Seo, shows (see, e.g., Aoki: figs. 1A-1E) the method step of injecting molten solder 16 within the trench 14 upon the contact pad 12. Aoki further shows that the method step of injecting molten solder can be performed using the IMS technique to supply the molten solder directly into the trenches (see, e.g., Aoki: par. [0034] – [0035]).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of injecting molten solder within the trench upon the contact pad of Aoki in the semiconductor system fabrication method of Ho in view of Zhang in view of Seo to supply the molten solder directly into the trenches.
Regarding claim 17, Ho in view of Zhang in view of Seo (see, e.g., Ho: figs. 1, 2a-2d, and 3) shows that most aspects of the instant invention including the method step of forming the solder bump 216 within the trench 208/212 upon the contact pad 214.
However, Ho in view of Zhang in view of Seo fails to show (see, e.g., Ho: figs. 1, 2a-2d, and 3) the method step of injecting molten solder 216 within the trench 208/212 upon the contact pad 214. Aoki, in a similar method to Ho in view of Zhang in view of Seo, shows (see, e.g., Aoki: figs. 1A-1E) the method step of injecting molten solder 16 within the trench 14 upon the contact pad 12. Aoki further shows that the method step of injecting molten solder can be performed using the IMS technique to supply the molten solder directly into the trenches (see, e.g., Aoki: par. [0034] – [0035]).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of injecting molten solder within the trench upon the contact pad of Aoki in the semiconductor system fabrication method of Ho in view of Zhang in view of Seo to supply the molten solder directly into the trenches.
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the previous grounds of rejection.
The applicants argue:
Ho in view of Zhang in view of Seo fails to anticipate or otherwise render obvious the limitation of “… wherein forming the patterned mask comprises: forming a resist layer upon the wiring contact and the external surface of the first IC package; and forming the trench within the resist layer,”, as it was previously recited in exemplary claims 1, 10, and 19.
The examiner responds:
In view of the previous grounds of rejection, Ho in view of Zhang in view of Seo shows clearly teaches (see, e.g., Ho: figs. 1, 2a-2d, and 3) wherein forming the patterned mask 210 comprises:
Forming a patterned layer 210 upon the wiring contact 204 and the external surface of the first IC package 200/206 (see, e.g., Ho: figs. 1, 2a-2d, and 3)
Forming the trench 208/212 within the patterned layer 210 see, e.g., Ho: figs. 1, 2a-2d, and 3)
Retaining one or more portions from a plurality of portions of the patterned layer 210 to form the patterned mask 210
A top surface of the contact pad 214 is recessed below a top surface of the patterned mask 210
Indeed, Ho in view of Zhang fails to teach that the pattern layer 210 is a resist layer. However, Also, Ho in view of Zhang in view of Seo shows (see, e.g., Seo: figs. 4A) that the patterned layer 180 is a resist layer (see, e.g., Seo: par. [0048]), where the element 180 from the Seo reference is equivalent to the element 210 from the Ho reference.
Also, it is show in claim 10, that Seo reference shows (see, e.g., Seo: figs. 4A) that the patterned layer 180 is a resist layer (see, e.g., Seo: par. [0048]) such as: However, Ho in view of Zhang fails to show (see, e.g., Ho: figs. 1, 2a-2d, and 3) that the patterned layer 210 is a resist layer. Ho in view of Zhang is silent that the patterned layer 210 is a resist layer. Ho in view of Zhang specify that the patterned layer 210 is a solder mask 208 (see, e.g., Ho: figs. 1, 2a-2d, and 3). Seo, in a similar method to Ho in view of Zhang, shows (see, e.g., Seo: fig. 4A) a patterned layer 180 that is made of resist (see, e.g., Seo: par. [0048]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the solder mask layer of Ho in view of Zhang or resist layer of Seo because these were recognized in the semiconductor art for their use as solder mask layers in semiconductor structures, as taught by Ho in view of Zhang and by Seo, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814