DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments, filed 01/02/2026, have been entered. Claims 3, 4, 10, and 14 have been cancelled and Claims 1-2, 5-9, 11-13 and 15-20 are pending.
Drawings
The Applicant’s amendments to the Claims, filed 01/02/2026, have overcome the Drawings Objection previously set forth in the Office Action dated 10/01/2025. The Drawings Objection has been withdrawn.
Claim Objections
Claims 1 and 15 are objected to because of the following informalities:
Claim 1 states “the connection bypass the second source/drain”. The Examiner believes this to be a mere typo and should be read as “the connection bypasses the second source/drain.”
Claim 15 states “the connection bypass the second source/drain”. The Examiner believes this to be a mere typo and should be read as “the connection bypasses the second source/drain.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The Applicant’s amendments to the Claims, filed 01/02/2026, have overcome the 35 U.S.C. 112(b) rejections of Claims 3, 4, 10, and 14 previously set forth in the Office Action dated 10/01/2025. The 35 U.S.C. 112(b) rejections of Claims 3, 4, 10, and 14 have been withdrawn.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 5-9, 11-12, and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the backside region". There is insufficient antecedent basis for this limitation in the claim as there is no mention of “a backside” previously in Claim 1. For examination purposes, “the backside region” will be interpreted as “a backside region”. Claims 2, 5-9, and 11-12 are also rejected under 35 U.S.C. 112(b) as they depend from and include all of the limitations of rejected Claim 1.
Claim 2 recites the limitation “the source/drain epitaxies”. There is insufficient antecedent basis for this limitation in the claim as there is no mention of “a source/drain epitaxy” previously in Claim 2 or Claim 1 from which Claim 2 relies. For examination purposes, “the source/drain epitaxies” will be interpreted as “a source/drain epitaxy” as interpreted from the Applicant’s drawings. Claims 5-9 are also rejected under 35 U.S.C. 112(b) as they depend from and include all of the limitations of rejected Claim 2.
Claim 15 recites the limitation "the backside region". There is insufficient antecedent basis for this limitation in the claim as there is no mention of “a backside” previously in Claim 15. For examination purposes, “the backside region” will be interpreted as “a backside region”. Claim 16 is also rejected under 35 U.S.C. 112(b) as it depends from and includes all of the limitations of rejected Claim 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9, 11-12 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20230307515 A1) hereinafter “Hsu” in view of Lin et al. (US 20230180451 A1) hereinafter “Lin” and Ju et al. (US 20210351303 A1) hereinafter “Ju.”
Regarding Claim 1, Figures 2-21B of Hsu teach: A semiconductor device (200) comprising: a plurality of logic devices (Paragraph 0013) with frontside wiring (277; Figure 21A); wherein one of the logic devices (200) of the plurality of logic devices includes a first source/drain (leftmost 260; Figure 21B), a second source/drain (middle 260; Figure 21B), and a third source/drain (rightmost 260; Figure 21B), wherein the second source/drain is located between the first source/drain and the third source/drain; a backside power delivery network (BSPDN) (286; Figure 21B); and a connection (282/284; Figure 20D and 21B) between the BSPDN and the bottom of a source/drain (260; Figure 20D);wherein the connection is self-aligned on at least two sides (Figure 20C and 20D where the connection is self-aligned via isolation features 230).
Hsu does not teach: the connection is between the BSPDN and the bottom of the first source/drain and the bottom of the third source/drain, wherein the connection bypasses the second source/drain
Figure 5O-2 of Lin teaches: a semiconductor structure (Paragraph 0047) with a first source/drain (124a), a second source/drain (124c) and a third source/drain (124d), wherein connections (178a and 178c) are formed on the first source/drain and the third source/drain, and wherein the connections bypass the second source/drain.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the connection be between the BSPDN and the bottom of the first source/drain and the bottom of the third source/drain, wherein the connection bypasses the second source/drain because Lin teaches contacts are formed over specific transistors, such as pull-up, pull-down, and pass-gate transistors, to electrically connect the components (Lin Paragraph 0036; Figures 3 and 5O-2), while transistors without a contact become isolation transistors (Lin Paragraph 0026).
The combination of the connections of Lin with the structure of Hsu would yield a structure such that the connection is between the BSPDN and the bottom of the first source/drain and the bottom of the third source/drain, wherein the connection bypasses the second source/drain.
Hsu does not teach: wherein the first source/drain and the third source/drain extends further into a backside region than the second source/drain
Figure 2 of Ju teaches: a semiconductor transistor device (200) comprising: a back-side power rail (122), a first source/drain (leftmost 108), a second source/drain (106), and a third source/drain (rightmost 108); wherein the first source/drain and the third source/drain extends further into a backside region (126) than the second source/drain.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the first source/drain and the third source/drain extends further into a backside region than the second source/drain because Ju teaches that the source/drain regions in semiconductor transistor devices may be formed to be diamond-like in shape to extend further into a back-side dielectric (Ju Paragraph 0025). Further, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second source/drain not extend further into a backside region than the first source/drain and the third source/drain because Ju teaches that having a bottom surface of a source/drain region be recessed vertically away from a backside region of the device can reduce cell capacitance (Ju Paragraph 0032).
Regarding Claim 2, Figures 2-21B of Hsu teach: the connection (282/284) is a ground or power rail (Paragraph 0050) that connects the source/drain epitaxies (260) from multiple logic devices (Left stack 205 and right stack 205; Paragraph 0013) to the BSPDN (286).
Regarding Claim 5, Figures 2-21B of Hsu teach: the power or ground rail (282/284) is shared (Figure 21B) by two adjacent logic devices (Left stack 205 and right stack 205; Paragraph 0013) of the same polarity (Paragraph 0027; N-type or P-type).
Regarding Claim 6, Figures 2-21B of Hsu teach: the two adjacent logic devices (Left stack 205 and right stack 205; Paragraph 0013) are NFET nanosheet transistors (Paragraph 0013; paragraph 0027).
Regarding Claim 7, Figures 2-21B of Hsu teach: perimeter edges (left/right horizontal sides of 282) of the ground or power rail (282/284) are defined by frontside patterned isolation regions (230 Figure 20D).
Regarding Claim 8, Figures 2-21B of Hsu teach: the frontside patterned isolation regions (230) are shallow trench isolation (STI) regions (Paragraph 0021) under channels (215) of the plurality of logic devices (Left stack 205 and right stack 205; Paragraph 0013).
Regarding Claim 9, Figures 2-21B of Hsu teach: a bottom dielectric isolation (BDI) layer (283; Figure 13C) under gates (350) of the plurality of logic devices (Left stack 205 and right stack 205; Paragraph 0013).
Regarding Claim 11, Figures 2-21B of Hsu teach: the connection (282/284) is a backside contact (Paragraph 0048).
Regarding Claim 12, Figures 2-21B of Hsu teach: two sides (left/right horizontal sides of 282) of the backside contact (282/284) are defined (Figure 20D) by frontside patterned isolation regions (230).
Regarding Claim 15, Figures 2-21B of Hsu teach: A semiconductor device (200) comprising: a plurality of nanosheet transistors (Paragraph 0013). wherein one of the nanosheet transistors (200) of the plurality of nanosheet transistors includes a first source/drain (leftmost 260; Figure 21B), a second source/drain (middle 260; Figure 21B), and a third source/drain (rightmost 260; Figure 21B), wherein the second source/drain is located between the first source/drain and the third source/drain; a backside power delivery network (BSPDN) (286; Figure 21B); a connection (282/284; Figure 20D and 21B) between the BSPDN and the bottom of a source/drain epitaxy of a nanosheet transistor, wherein the connection is self-aligned on at least two sides(Figure 20C and 20D where the connection is self-aligned via isolation features 230); a back-end-of-line (BEOL) structure (277; Paragraph 0041); and one or more BEOL contacts (Paragraph 0041), each of the one or more BEOL contacts connecting a source/drain epitaxy of a nanosheet transistor to the BEOL (Paragraph 0041).
Hsu does not teach: the connection is between the BSPDN and the bottom of the first source/drain and the bottom of the third source/drain, wherein the connection bypasses the second source/drain
Figure 5O-2 of Lin teaches: a semiconductor structure (Paragraph 0047) with a first source/drain (124a), a second source/drain (124c) and a third source/drain (124d), wherein connections (178a and 178c) are formed on the first source/drain and the third source/drain, and wherein the connections bypass the second source/drain.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the connection be between the BSPDN and the bottom of the first source/drain and the bottom of the third source/drain, wherein the connection bypasses the second source/drain because Lin teaches contacts are formed over specific transistors, such as pull-up, pull-down, and pass-gate transistors, to electrically connect the components (Lin Paragraph 0036; Figures 3 and 5O-2), while transistors without a contact become isolation transistors (Lin Paragraph 0026).
The combination of the connections of Lin with the structure of Hsu would yield a structure such that the connection is between the BSPDN and the bottom of the first source/drain and the bottom of the third source/drain, wherein the connection bypasses the second source/drain.
Hsu does not teach: wherein the first source/drain and the third source/drain extends further into a backside region than the second source/drain
Figure 2 of Ju teaches: a semiconductor transistor device (200) comprising: a back-side power rail (122), a first source/drain (leftmost 108), a second source/drain (106), and a third source/drain (rightmost 108); wherein the first source/drain and the third source/drain extends further into a backside region (126) than the second source/drain.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the first source/drain and the third source/drain extends further into a backside region than the second source/drain because Ju teaches that the source/drain regions in semiconductor transistor devices may be formed to be diamond-like in shape to extend further into a back-side dielectric (Ju Paragraph 0025). Further, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second source/drain not extend further into a backside region than the first source/drain and the third source/drain because Ju teaches that having a bottom surface of a source/drain region be recessed vertically away from a backside region of the device can reduce cell capacitance (Ju Paragraph 0032).
Regarding Claim 16, Figures 2-21B of Hsu teach: an inter-layer dielectric (ILD) (Paragraph 0041; Where layer 277 is used to denote various dielectric layers) between the nanosheet transistors (Left stack 205 and right stack 205; Paragraph 0013) and the BEOL (277), wherein the one or more BEOL contacts are formed in the ILD (Paragraph 0041).
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 01/02/2026, with respect to the rejections of Claims 1 and 15 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Hsu, Lin, and Ju.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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