DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 27, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant' s Amendment filed on 06/03/2026. Claims 1 have been amended. No claims have been added or canceled. Claims 11-20 have been cancelled. Currently, claims 1-10 are pending.
Applicant’s amendment to claim 1 successfully overcomes the 112(b) rejection of claim 1 set forth in the previous Office Action.
Response to Arguments
Applicant's arguments with respect to claims 1 filed on 06/03/2027 have been fully considered but they are not persuasive. The reason is set forth below.
In the Remarks document page 7 Applicant stated "A. Lee does not teach or suggest the claimed "spalled III-V planar substrate" having the recited spalled terrace structure.;"
However, A. Spalled has the definition: "to break off chips, scales, or slabs" and a spalled structure has the definition “It is a form of structural deterioration where internal stress causes the surface to frail, creating rough, pitted or jagged areas” and a spalled semiconductor substrate refers to a brittle semiconductor donor wafer from which a thin, single-crystal layer has been mechanically or acoustically exfoliated, or "spalled". In the instant application the substrate was spalled to create terrace structured substrate with a roughness.
B. Fujikura and Yasuda do not cure Lee's failure to teach the claimed spalled III-V planar;
However, Examiner disagrees. Lee et al. discloses the terrace structure and FUJIKURA et al. discloses the surface roughness, and height and width of the terraces.
C. Yasuda does not teach the claimed W range.
However, FUJIKURA et al. already disclosed the width of the terrace width cane be 500μm (for example, a region having a size of 1 mm square or more or a region having a width of 500 μm square or more).” ¶ [0081]). Furthermore, Yasuda et al. ¶ [0043] discloses, “The size of the irregularities may be in a range of 10-1000 nanometers in height and in a range of 10-1000 nanometers in pitch”.
"A prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of "having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium" as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium. "The proportions are so close that prima facie one skilled in the art would have expected them to have the same properties.")."
The prior arts of records (US 20200043728 A1) “Lee et al.” in view of (US 20190272990 A1) “FUJIKURA et al.” further in view of (US 20070096116 A1) “Yasuda et al.” disclose all the limitations that required by the claimed invention after being spalled. Therefore, does not overcome the current prior arts and the rejection is maintained.
Furthermore, a new search has been conducted and a non-final rejection has been made using newly found prior arts along with the existing prior arts to address newly amended new limitations 0.1µm≤H≤3µm of amended claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20200043728 A1) “Lee et al.” in view of (US 20190272990 A1) “FUJIKURA et al.” further in view of (P. G. Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021, pp. 2141-2143, doi: 10.1109/PVSC43889.2021.9518656.) “Coll et al.”.
Regarding Independent Claim 1, Lee et al. Figs. 1-5 discloses a composition comprising: a spalled (spalled terraces are shown in figs. 4C and 5C) III-V planar substrate having a surface (“epitaxial layer 62 may include … GaAs” ¶ [0045]; “FIGS. 4A to 4C, the semiconductor epitaxial substrate WF10 includes a semiconductor substrate WF and a semiconductor epitaxial layer 62 formed on the main surface MS of the semiconductor substrate WF.” ¶ [0043) aligned with and parallel to a reference plane (“The semiconductor epitaxial layer 62 has an upper surface 62T on which a plurality of atomic level steps ST is formed. An extending direction D1 of each of the plurality of atomic level steps ST may be parallel to the second straight line L2 (see FIG. 1A)” ¶ [0044), wherein:
the surface comprises a plurality of terraces (“flat terrace TE may extend, parallel to the extending direction D1, between the atomic level steps ST formed on the upper surface 62T of the semiconductor epitaxial layer 62” ¶ [0045]),
each terrace comprises a first surface (Fig. 4C shows each terrace has first surface TE) positioned between a first boundary (the left edge of each TE in Fig. 4C) and a second boundary (the right edge of each TE in Fig. 4C),
for each terrace, the first boundary is substantially parallel the second boundary (Fig. 4C shows the left edge and right edge of terrace TE is parallel to each other) and
for each terrace, the first boundary is positioned substantially parallel to the reference plane (Fig. 4C shows the left edge is parallel to the reference plane),
each terrace is separated from an adjacent terrace by a second surface (Fig. 4C shows each terrace TE separated by the surface ST) positioned between the second boundary of the terrace and the first boundary of the adjacent terrace (Fig. 4C shows ST is positioned between the second boundary of the terrace and the first boundary of the adjacent terrace),
for each terrace, the first boundary is positioned approximately at a distance, H, relative to its second boundary in a first direction that is orthogonal to the reference plane (Fig. 4C shows the boundaries are separated by a step height for each terrace which is orthogonal to the main surface),
for each terrace, the first boundary is positioned approximately at a distance, W relative to the second boundary in a second direction parallel to the reference plane and orthogonal to the first direction (Fig. 4C shows the height is in vertical direction and width is in the lateral direction),
each terrace lies positioned in a plane at an angle, α (“the main surface MS of the semiconductor substrate WF is inclined by the first off-angle θ in the <110> direction parallel to the (100) crystal plane and the semiconductor epitaxial layer 62 is formed on the inclined main surface MS of the semiconductor substrate WF), relative to the reference plane,
However, Lee et al. does not disclose each terrace has a surface roughness of less than 1 nm, as measured by atomic force microscopy, 0.1µm≤H≤3µm and 1μm<W≤1mm.
In the similar field of endeavor of crystals and substrates FUJIKURA et al. discloses each terrace has a surface roughness of less than 1 nm, as measured by atomic force microscopy (“rms value of a surface roughness obtained by AFM measurement in a 5 μm square region is preferably 0.3 nm or less, more preferably 0.2 or less” ¶ [0095]; “rms value of a surface roughness obtained by AFM measurement in a 5 μm square region is 1 nm or less” ¶ [0111]), and
1 μm < W ≤ 1 mm (“The laminate having the step-terrace which is flatter than the macro step-macro terrace on the epi-layer surface is not limited to the laminate having the step-terrace on the entire surface of the epi-layer, and may be the laminate having the step-terrace in a part of the epi-layer surface (for example, a region having a size of 1 mm square or more or a region having a width of 500 μm square or more).” ¶ [0081]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the surface roughness and the length of the terraces of Lee et al. with the surface roughness and the length of the terraces of FUJIKURA et al. in order to improve surface flatness (FUJIKURA et al. ¶ [0044]), the high flatness of the surface of the epitaxial layer brings about at least an advantage such that it is easy to laminate other layer on the epitaxial layer for example (FUJIKURA et al. ¶ [0031]), and in order to improve a withstand voltage of a semiconductor device (FUJIKURA et al. ¶ [0003]).
However, Lee et al. and FUJIKURA et al. does not explicitly disclose spalled substrate and 0.1µm≤H≤3µm.
In the similar field of semiconductor device substrates Coll et al. discloses spalled substrate (“spalled GaAs wafers” Section III. Results and Discussion, Line 4) and 0.1µm≤H≤3µm (“the surface facets that are typical in standard spalling processes and reduced them from 7.55 µm to 0.3 µm in height.” Section IV, Conclusion, Lines 3-4).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the length of the terraces of Lee et al. with the spalled wafers and heights of the terraces of Coll et al. in order to show minimal residual strain after spalling as observed from PL measurements of a QW in an AlGaAs double heterojunction. The electrical characterization of the spalled solar cell show a solar cell efficiency of 17.8% with no significant Voc degradation compared to the baseline (Coll et al. Section IV, Conclusion, Lines 5-8).
Regarding Claim 9, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. Lee et al. further discloses wherein each terrace is positioned substantially in at least one of the (110) plane (“in the <110> direction” ¶ [0045]), the (111) plane, the (211) plane, or the (311) plane.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over (US 20200043728 A1) “Lee et al.” in view of (US 20190272990 A1) “FUJIKURA et al.” further in view of (P. G. Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021, pp. 2141-2143, doi: 10.1109/PVSC43889.2021.9518656.) “Coll et al.” further in view of (US 20110220915 A1) “Edgar et al.”
Regarding Claim 2, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. However, Lee et al. does not disclose wherein H varies between ± 20%.
In the similar field of endeavor of crystals and substrates Edgar et al. discloses wherein H varies between ± 20% (“step height and offset might be within about 15% of a height” ¶ [0054]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the step height of FUJIKURA et al. with the variations in height of Edgar et al. in order to be consistent with a substantial crystalline match between portions of material grown on adjacent terraces (Edgar et al. ¶ [0054]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over (US 20200043728 A1) “Lee et al.” in view of (US 20190272990 A1) “FUJIKURA et al.” further in view of (P. G. Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021, pp. 2141-2143, doi: 10.1109/PVSC43889.2021.9518656.) “Coll et al.” further in view of (US 20070085170 A1) “Shin et al.”
Regarding Claim 3, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. However, Lee et al. does not disclose wherein W varies between ± 15%.
In the similar field of endeavor of crystals and substrates Shin et al. discloses a GaAs wafer of {111} plane or a sapphire wafer of c-plane ({0001}), and is grown by a method such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or halide vapor phase epitaxy (HVPE) (Shin et al. ¶ [0006]).
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the terrace width W would inherently have properties of the width W within 15% because the terrace is made of GaAs, which is the same as the material of the terraces as disclosed. See MPEP 2112.01.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20200043728 A1) “Lee et al.” in view of (US 20190272990 A1) “FUJIKURA et al.” further in view of (P. G. Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021, pp. 2141-2143, doi: 10.1109/PVSC43889.2021.9518656.) “Coll et al.” further in view of (US 20100212729 A1) “Hsu et al.”.
Regarding Claim 4, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. Lee et al. further discloses wherein the III-V planar substrate is GaAs substrate (“GaAs substrate” Column 5, lines 28-29).
However, Lee et al. does not explicitly disclose wherein the GaAS substrate has a zinc blende crystal structure.
In the similar field of endeavor of crystals and substrates Hsu et al. discloses wherein the GaAs substrate has a zinc blende crystal structure (“GaAs has a zincblende crystal structure” ¶ [0007]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the crystal structure of Lee et al. with the crystal structure of Hsu et al. in order to provide crystal structure is polarized in the (111) direction (Hsu et al. ¶ [0007]).
Regarding Claim 5, Lee et al. as modified by FUJIKURA et al. discloses the composition of claim 4. Lee et al. further discloses wherein the III-V planar substrate is constructed of at least one of GaAs, GaP, InAs, AlAs, AlP, or InP (“epitaxial layer 62 may include .. GaAs, InP” ¶ [0045]).
Regarding Claim 6, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 4. Lee et al. further discloses wherein the III-V planar substrate is constructed of a pseudo-binary combination of at least one of GaAs, GaP, InAs, AlAs AlP, or InP (“epitaxial layer 62 may include .. GaAs, InP, or a combination thereof.” ¶ [0045]).
Claim 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20200043728 A1) “Lee et al.” in view of FUJIKURA, Hajime (US 20190272990 A1) “FUJIKURA et al.” further in view of (P. G. Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021, pp. 2141-2143, doi: 10.1109/PVSC43889.2021.9518656.) “Coll et al.” further in further in view of Morkoc, Hadis (US 4872046 A) “Morkoc et al.”.
Regarding Claim 7, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. However, Lee et al. does not disclose wherein α is less than 5°.
In the similar field of endeavor of heterojunction semiconductor devices Morkoc et al. discloses wherein α is between less than 5° (“In a preferred embodiment of the invention, gallium arsenide is epitaxially deposited over silicon tilted, in one of the designated directions, by at least 2.29 degrees.” Column 3, Lines 50-53).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify tilt angle of Lee et al. with the tilt angle of Morkoc et al. in order to reduce misfit dislocation densities (Morkoc et al., Column 3, Line 57). The quality improvement over the use of tilt toward the <011> direction has been striking, and results in a reduction by two-thirds in dislocations in the epitaxial layer (Morkoc et al., Column 3, Lines 67-68; Column 4, Lines 1-2).
Regarding Claim 8, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. However, Lee et al. does not disclose wherein α is less than 3°.
In the similar field of endeavor of heterojunction semiconductor devices Morkoc et al. discloses wherein α is between less than 3° (“In a preferred embodiment of the invention, gallium arsenide is epitaxially deposited over silicon tilted, in one of the designated directions, by at least 2.29 degrees.” Column 3, Lines 50-53).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify tilt angle of Lee et al. with the tilt angle of Morkoc et al. in order to reduce misfit dislocation densities (Morkoc et al., Column 3, Line 57). The quality improvement over the use of tilt toward the <011> direction has been striking, and results in a reduction by two-thirds in dislocations in the epitaxial layer (Morkoc et al., Column 3, Lines 67-68; Column 4, Lines 1-2).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over (US 20200043728 A1) “Lee et al.” in view of (US 20190272990 A1) “FUJIKURA et al.” further in view of (P. G. Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021, pp. 2141-2143, doi: 10.1109/PVSC43889.2021.9518656.) “Coll et al.” further in view of US 20180366325 A1) “Norman et al.”.
Regarding Claim 10, Lee et al. as modified by FUJIKURA et al. and Coll et al. discloses the composition of claim 1. However, Lee et al. does not disclose wherein 30 μm < W ≤ 100 μm.
In the similar field of endeavor of crystals and substrates Norman et al Fig. 11 discloses wherein, 30 μm < W ≤ 100 μm (“An average terrace length of 72 μm between step edges was determined by AFM.” ¶ [0069]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the length of the terraces of Lee et al. with the surface roughness and the length of the terraces of NORMAN et al. in order to confirm growth of high-quality semiconductor devices on epitaxial substrates has enabled the development of a multitude of technologies ranging from light-emitting devices to photovoltaics. (NORMAN et al. ¶ [0004]).
Conclusion
The Prior art Yoon, Woojun (US 20190157497 A1) “Yoon et al.” filing date 2018-11-20 made of record and not relied upon is considered pertinent to applicant’s disclosure.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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