DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/05/2026 has been entered.
Response to Amendment
Acknowledgment is made of the amendment filed 08/05/2026, in which: claim(s) 1, 6, 8, and 18 is/are amended; and the rejection of the claims are traversed. Claim(s) 1, 4-12, 15, and 18-20 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 08/05/2026, with respect to the rejection(s) of claim(s) 1, 4-12, 15, and 18-20 as amended have been fully considered but they are not persuasive.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
However, a full rejection of these claims, as amended, is detailed below.
Claim Objections
Claims 1, 4-12, 15, and 18-20 are objected to because of the following informalities:
Claim 1:
“…the opposite outer portions positioned…” should read “…the opposite outer portions being positioned…” for tense agreement with the rest of the clause;
The subordinate clause beginning “…wherein the opposite outer portions of the inner spacer being located…” lacks a finite verb, such as “are” in place of “being”;
“…and opposite outer portions…” (in the last paragraph of the claim) is missing the definite article “the”, since the feature is previously recited in the claim;
Claim 4: “…a width that is larger than a width of the middle portion” should use “the” instead of “a” in both instances, since the feature is previously recited in claim 1.
Claim 6: “…an outer surface of the metal gate stack…” should use “the” instead of “an”, since the feature is previously recited in claim 1;
Claim 8:
The subordinate clause beginning “…and the opposite outer portions of the inner spacer being located…” lacks a finite verb, such as “are” in place of “being”;
“…the opposite outer portions of the inner spacer…and are wider than a middle portion of the inner spacer” should use “the” instead of “a”, since the feature is previously recited in the claim;
Claim 9:
“…comprises opposite outer portions…” is missing the definite article “the”, since the feature is previously recited in claim 8;
“…a middle portion of the inner spacer…” should use “the” instead of “a”, since the feature is previously recited in claim 8;
Claim 11: “…an outer surface of the metal gate stack…” should use “the” instead of “an”, since the feature is previously recited in claim 8.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 4-12, 15, and 18-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim(s) 1 and 4-7, the claim feature or are dependent upon claims which feature the limitation “…the opposite outer portions positioned and curving inward in a direction towards the first source/drain region…” (emphasis added). It is unclear what it means for an opposite outer portion to be “curving inward in a direction towards the first source/drain region”. Multiple interpretations may apply. For example, the limitation may mean the “vertex” or “turning point” of the curve may be closer to the first source/drain region than the start/end point(s) of the curve. Alternatively, it may mean that the start/end point(s) are closer to the source/drain region than the "vertex" such that a vector tangent to the curve and pointing in the direction of motion from one point to the other turns toward S/D when moving from one point to the other (like how a road that you would describe as curving left/right would be oriented, where the direction of curvature refers to the orientation of the end of a curve relative to its start). These interpretations would have oppositely oriented curvatures of opposite outer portions. Either interpretation is supported by the instant disclosure, since the first source/drain region is not necessarily limited as the source/drain region on either the same or opposite side of the metal gate stack as the inner spacer in question, so the former interpretation is met when the first source/drain region and inner spacer are on the same side and the latter is met when they are on opposite sides. Therefore, it is unclear which interpretation is intended. As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008). For the purpose of examination, Examiner interprets the limitation according to the former interpretation.
Further regarding claim(s) 1 and 4-7, the claim feature or are dependent upon claims which feature the limitation, “…the opposite outer portions positioned and curving inward in a direction towards the first source/drain region and relative to an outer surface of the metal gate stack…” (emphasis added). The grammatical structure of the clause makes it unclear which claim feature or verb is “relative to an outer surface of the metal gate stack” or what that would mean. For the purpose of examination, Examiner interprets the limitation as reciting “the opposite outer portions positioned and curving inward in a direction towards the first source/drain region, and the opposite outer portions being curved relative to an outer surface of the metal gate stack”.
Further regarding claim(s) 6, the claim feature or are dependent upon claims which feature the limitation, “…a concave surface of the inner spacer is relative to an outer surface of the metal gate stack…” (emphasis added). It is unclear in what sense the concave surface is “relative” to the outer surface. For the purpose of examination, Examiner interprets the limitation as reciting “a concave surface of the inner spacer is concave relative to an outer surface of the metal gate stack”.
Regarding claim(s) 8-12, 15, and 18-20, the claim feature or are dependent upon claims which feature the limitation “…the inner spacer having a concave surface curving inward in a direction towards the first source/drain region…” (emphasis added). It is unclear what it means for the concave surface to be “curving inward in a direction towards the first source/drain region”. Multiple interpretations may apply. For example, the limitation may mean the “vertex” or “turning point” of the curve may be closer to the first source/drain region than the start/end point(s) of the curve. Alternatively, it may mean that the start/end point(s) are closer to the source/drain region than the "vertex" such that a vector tangent to the curve and pointing in the direction of motion from one point to the other turns toward S/D when moving from one point to the other (like how a road that you would describe as curving left/right would be oriented, where the direction of curvature refers to the orientation of the end of a curve relative to its start). These interpretations would have oppositely oriented curvatures of opposite outer portions. Either interpretation is supported by the instant disclosure, since the first source/drain region is not necessarily limited as the source/drain region on either the same or opposite side of the metal gate stack as the inner spacer in question, so the former interpretation is met when the first source/drain region and inner spacer are on the same side and the latter is met when they are on opposite sides. Therefore, it is unclear which interpretation is intended. As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008). For the purpose of examination, Examiner interprets the limitation according to the former interpretation.
Further regarding claim(s) 8-12, 15, and 18-20, the claim feature or are dependent upon claims which feature the limitation, “…the inner spacer having a concave surface curving inward in a direction towards the first source/drain region and relative to an outer surface of the metal gate stack…” (emphasis added). The grammatical structure of the clause makes it unclear which claim feature or verb is “relative to an outer surface of the metal gate stack” or what that would mean. For the purpose of examination, Examiner interprets the limitation as reciting “the inner spacer having a concave surface curving inward in a direction towards the first source/drain region, and the opposite outer portions being curved relative to an outer surface of the metal gate stack”.
Further regarding claim(s) 11, the claim feature or are dependent upon claims which feature the limitation, “…the concave surface of the inner spacer is relative to an outer surface of the metal gate stack…” (emphasis added). It is unclear in what sense the concave surface is “relative” to the outer surface. For the purpose of examination, Examiner interprets the limitation as reciting “the concave surface of the inner spacer is concave relative to an outer surface of the metal gate stack”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The limitation(s) of claim 9 appear in claim 8, on which claim 9 depends, which recites “the concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region”. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4-12, 15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US 20230063786 A1, hereinafter Liao), and further in view of Greene et al. (US 20210043728 A1, hereinafter Greene).
Regarding independent claim 1, Liao discloses in Liao FIG. 2-20C and associated text a semiconductor structure, comprising: a plurality of semiconductor layers vertically stacked over a semiconductor substrate, each of the plurality of semiconductor layers defining a channel region extending in a first horizontal direction (semiconductor fins 20a/20b are vertically stacked on substrate 12 and extend in the x-direction); a first source/drain region located on one end of the plurality of semiconductor layers (source/drain features 38/40); a metal gate stack surrounding each of the plurality of semiconductor layers (gate electrode layer 48 surrounds semiconductor layers 16a/16b); a sidewall spacer located along opposite sidewalls of the metal gate stack (sidewall spacer 34 is along opposite sidewalls of 48, as shown in Liao FIG. 4); and an inner spacer located between each of the plurality of semiconductor layers, the inner spacer separating the metal gate stack from the first source/drain region (inner spacers 36 separate gate electrode layer 48 from source/drain features 38/40 as shown in Liao FIG. 10A).
Liao does not explicitly disclose the inner spacer includes opposite outer portions and a middle portion located therebetween, the opposite outer portions each having a width greater than a width of the middle portion along a direction perpendicular to a length of the channel region, the opposite outer portions positioned and curving inward in a direction towards the first source/drain region, and the opposite outer portions being curved relative to an outer surface of the metal gate stack to provide a substantially uniform thickness of the middle portion of the inner spacer, or the opposite outer portions of the inner spacer being located at an interface between the inner spacer and the sidewall spacer, and opposite outer portions extend over and cover portions of the sidewall spacer and outermost portions of the metal gate stack.
However, in the same field of endeavor, Greene discloses in Greene FIG. 11 and associated text the inner spacer includes opposite outer portions and a middle portion located therebetween, the opposite outer portions each having a width greater than a width of the middle portion along a direction perpendicular to a length of the channel region (inner spacers 702 have the claimed structure as shown, with the wider opposite outer potions being the top and bottom portions of the inner spacers, which are wider than a middle portion of the inner spacers between the opposite outer portions when widths are measured in the left/right horizontal direction, which is perpendicular to a length of the channel region in the vertical direction, for example), the opposite outer portions positioned and curving inward in a direction towards the first source/drain region, and the opposite outer portions being curved relative to an outer surface of the metal gate stack to provide a substantially uniform thickness of the middle portion of the inner spacer (opposite outer portions, as interpreted, are positioned and also curve inward towards source and drain structures 802 relative to an outer surface of gate conductor 1004; and the middle portion, as interpreted, has a substantially uniform thickness), and opposite outer portions extend over and cover portions of the sidewall spacer and outermost portions of the metal gate stack (opposite outer portions, as interpreted extend over and cover portions of gate spacers 304 (portions of 304 at an interface with 702) and outermost portions of 1004, as shown).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Liao with the concave inner spacer of Greene, which would position the inner spacer such that the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer (opposite outer portions of Greene’s inner spacer would extend laterally across the spacer, ending at an interface with Liao’s sidewall spacer) to provide a transistor where there are no voids left in the source/drain structures when sacrificial layers are etched away to be replaced by the metal gate (Greene [0044]).
Regarding dependent claim 4, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the inner spacer has a shape that includes two of the opposite outer portions and the middle portion, the two of the opposite outer portions being connected by the middle portion in the shape of a letter "C", the two of the opposite outer portions having a width that is larger than a width of the middle portion (the inner spacer 702 has the claimed structure as shown, with widths interpreted as above, with respect to the analogous limitation of claim 1).
Regarding dependent claim 5, Liao, as modified by Greene, further discloses in Liao FIG. 4 and associated text a portion of the semiconductor substrate below the plurality of semiconductor layers being located between shallow trench isolation regions (portions of substrate 12 are beneath insulation layer 22, which may be a shallow trench insulation (Liao [0018])).
Regarding dependent claim 6, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text a concave surface of the inner spacer is concave relative to an outer surface of the metal gate stack for providing an uniform thickness to the inner spacer and protecting the first source/drain region, wherein edges of the plurality of semiconductor layers have a substantially square shape (inner spacers 702 have a concave surface relative to gate conductors 1004, which have convex outer surfaces; the thickness of the inner spacer 702 is substantially uniform; and edges of the semiconductor layers are square). Examiner is interpreting "uniform thickness to the inner spacer" to be similar to the representation in Figure 8D of the application where inner spacer region 830b is of substantially uniform thickness while inner spacer region 830a at the edges is thicker than in region 830b.
Regarding dependent claim 7, Liao, as modified by Greene, further discloses the plurality of semiconductor layers comprises at least one selected from a group consisting of a nanosheet, a nanowire, and a nano-ellipse (the semiconductor stack 18a/18b is made of nanosheets (Liao [0019])).
Regarding independent claim 8, Liao discloses in Liao FIG. 1-20C and associated text a method of forming a semiconductor structure, comprising: forming a plurality of semiconductor layers vertically stacked over a semiconductor substrate, each of the plurality of semiconductor layers defining a channel region of the semiconductor structure (semiconductor stacks 18a/18b vertically stacked on substrate 12, which is a semiconductor (Liao [0017])), wherein the forming the plurality of semiconductor layers includes forming a nanosheet stack on the semiconductor substrate, the nanosheet stack comprising an alternating sequence of sacrificial semiconductor layers and semiconductor channel layers (semiconductor stack 18a/18b is nanosheets (Liao [0019]) comprising semiconductor layers 14a/14b (sacrificial layers) and 16a/16b (channel layers)); forming a first source/drain region located on one end of the plurality of semiconductor layers (source/drain features 38/40); forming a metal gate stack surrounding each of the plurality of semiconductor layers (gate electrode layer 48 surrounds semiconductor layers 16a/16b); forming an inner spacer located between each of the plurality of semiconductor layers, the inner spacer separating the metal gate stack from the first source/drain region (inner spacers 36 separate gate electrode layer 48 from source/drain features 38/40 as shown in Liao FIG. 10A); patterning the nanosheet stack to form a nanosheet fin (semiconductor fins 20a/20b); forming a dummy gate on the nanosheet fin (sacrificial gate structures 24a/24b/24c); etching outer portions of the sacrificial semiconductor layers, wherein the etching forms a first indentation region (semiconductor layers 14a/14b are etched to form spacer cavities (Liao [0036])); conformally depositing a spacer material to form a sidewall spacer along opposite sidewalls of the dummy gate (inner spacers 36 are formed conformally (Liao [0037])); using the sidewall spacer along sidewalls of the dummy gate as a mask, etching the nanosheet fin in a way such that a remaining portion of the nanosheet fin is vertically aligned with the sidewall spacer (semiconductor fins 20a/20b are etched where not covered by sacrificial gate structures including sidewall spacers 34, resulting in remaining portions being vertically aligned with the sidewall spacers 34 as shown in Liao FIG. 5), wherein a second surface of the inner spacer is in contact with the sidewall spacer and outer sidewalls of the inner spacer are vertically aligned with outer sidewalls of the sidewall spacer (left and right surfaces of inner spacers 36 are in contact with sidewall spacer 34, (Liao FIG. 5); and outer sidewalls of the inner spacers are vertically aligned with outer sidewalls of the sidewall spacer (Liao FIG. 10A));
Liao does not explicitly disclose the inner spacer having a concave surface curving inward in a direction towards the first source/drain region, and the opposite outer portions being curved relative to an outer surface of the metal gate stack, the concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region; depositing a sacrificial dielectric layer within the first indentation region; the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer and are wider than a middle portion of the inner spacer; removing the sacrificial dielectric layer; or etching second outer portions of the sacrificial semiconductor layers to form a second indentation region.
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However, in the same field of endeavor, Greene discloses in Greene FIG. 1-12 the inner spacer having a concave surface curving inward in a direction towards the first source/drain region, and the opposite outer portions being curved relative to an outer surface of the metal gate stack, the concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region (inner spacers 702 have the claimed structure, as shown in Greene FIG. 11, with the wider opposite outer potions being the top and bottom portions of the inner spacers, which are wider a middle portion of the inner spacers between the opposite outer portions when widths are measured in the left/right horizontal direction, which is perpendicular to a length of the channel region in the vertical direction, for example); depositing a sacrificial dielectric layer within the first indentation region (dielectric plugs 502 are deposited in recesses 402); the opposite outer portions of the inner spacer are wider than a middle portion of the inner spacer (opposite outer portions are wider than the middle portion of 702, as interpreted above); removing the sacrificial dielectric material (dielectric plugs 502 are etched away (Greene [0044])); and etching second outer portions of the sacrificial semiconductor layers to form a second indentation region (a second recessing etch is performed on the tails 404 of sacrificial layers 104 (Greene [0036])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Liao with the concave inner spacer of Greene, which would position the inner spacer such that the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer (opposite outer portions of Greene’s inner spacer would extend laterally across the spacer, ending at an interface with Liao’s sidewall spacer) to provide a transistor where there are no voids left in the source/drain structures when sacrificial layers are etched away to be replaced by the metal gate (Greene [0044]).
Regarding independent claim 9, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the inner spacer having the concave surface comprises opposite outer portions of the inner spacer being wider than a middle portion of the inner spacer (the inner spacer 702 has the claimed structure as shown).
Regarding dependent claim 10, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the inner spacer has a shape that includes two opposite segments and a vertical segment, the two opposite segments being connected by the vertical segment in the shape of a letter "C", the two opposite segments having a width that is larger than a width of the vertical segment (the inner spacer 702 has the claimed structure as shown).
Regarding dependent claim 11, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the concave surface of the inner spacer is concave relative to an outer surface of the metal gate stack for providing an uniform thickness to the inner spacer and protecting the first source/drain region, wherein edges of the plurality of semiconductor layers have a substantially square shape (inner spacers 702 have a concave surface relative to gate conductors 1004, which have convex outer surfaces; the thickness of the inner spacer 702 is substantially uniform; and edges of the semiconductor layers are square). Examiner is interpreting "uniform thickness to the inner spacer" to be similar to the representation in Figure 8D of the application where inner spacer region 830b is of substantially uniform thickness while inner spacer region 830a at the edges is thicker than in region 830b.
Regarding dependent claim 12, Liao, as modified by Greene, further discloses the plurality of semiconductor layers comprises at least one of a nanosheet, a nanowire, and a nano-ellipse (the semiconductor stack 18a/18b is made of nanosheets (Liao [0019])).
Regarding dependent claim 15, Liao, as modified by Greene, further discloses the sacrificial dielectric layer has good etch selectivity to the sacrificial semiconductor layers and includes at least one material selected from a group consisting of SiO2, SiBCN, SiCN, and SiOCN (dielectric plug 502 is SiO2 and has etch selectivity relative to the tails 404 of sacrificial layers 106 (Greene [0062])).
Regarding dependent claim 18, Liao, as modified by Greene, further discloses in Liao FIG. 10A and associated text forming the inner spacer on one side of the sacrificial semiconductor layers (as shown in Liao FIG. 10A); epitaxially growing the first source/drain region (source/drain features 38/40 are epitaxial (Liao [0038])); and forming a dielectric layer above the first source/drain region and between portions of the sidewall spacer being adjacent to the first source/drain region (interlayer dielectric layer 44).
Regarding dependent claim 19, Liao, as modified by Greene, further discloses in Liao FIG. 7 and associated text removing the dummy gate, wherein removing the dummy gate creates a recess between the sidewall spacer (sacrificial gate electrode layer 28 is initially between the sidewall spacer 34, leaving a cavity once removed (Liao [0046]-[0048])); and selectively removing the sacrificial semiconductor layers (semiconductor layers 14a/14b are selectively removed (Liao [0047])).
Regarding dependent claim 20, Liao, as modified by Greene, further discloses in Liao FIG. 10A and associated text forming the metal gate stack within the recess, the metal gate stack surrounding the plurality of semiconductor layers and being separated from the first source/drain region by the inner spacer (gate electrode layer 48 has the claimed structure).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200075718 A1, pertaining to a variety of inner spacer geometries.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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