DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed April 27, 2026, in which: claim(s) 1, 6, 8, 11, 18, and 20 is/are amended; and the rejection of the claims are traversed. Claim(s) 1, 4-12, 15, and 18-20 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed April 27, 2026, with respect to the rejection(s) of claim(s) 1, 4-12, 15, and 18-20 as amended have been fully considered but they are not persuasive.
Regarding independent claims 1 and 8 as amended, Greene discloses in Greene FIG. 11 and associated text opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region (inner spacers 702 have the claimed structure as shown, with the opposite outer potions being the top and bottom portions of the inner spacers, which are wider a middle portion of the inner spacers between the opposite outer portions, in the middle of the inner spacers in the vertical direction, which is perpendicular to a length of the channel region).
In response to the applicant’s remarks that “the Office Action does not identify, and the references do not provide, a reason why one of ordinary skill in the art would have been motivated to modify Greene's "inner spacer" structure using Liao's teachings”, the rejection as previously set forth and herein relies upon the semiconductor structure disclosed by Liao, not Greene, as a primary reference, which is modified to include the inner spacer of Greene. Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Liao with the concave inner spacer of Greene, which would position the inner spacer such that the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer (opposite outer portions of Greene’s inner spacer would extend laterally across the spacer, ending at an interface with Liao’s sidewall spacer) to provide a transistor where there are no voids left in the source/drain structures when sacrificial layers are etched away to be replaced by the metal gate (Greene [0044]). The references relied upon for the rejection explicitly provide motivation for the combination without the need for hindsight reasoning.
Other amendments to these claims do not introduce new limitations or substantially change limitations previously considered for examination, and are therefore omitted from this portion of the response. However, a full rejection of these claims, as amended, is detailed below.
Claim Objections
Claim 8 is objected to because of the following informalities: the limitation “curving inward in a direction towards the first source/drain region” regarding the concave surface of the inner spacer appears to have been repeated (twice in the paragraph in which the limitation appears: lines 2 and 5). Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4-12, 15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US 20230063786 A1, hereinafter Liao), and further in view of Greene et al. (US 20210043728 A1, hereinafter Greene).
Regarding independent claim 1, Liao discloses in Liao FIG. 2-20C and associated text a semiconductor structure, comprising: a plurality of semiconductor layers vertically stacked over a semiconductor substrate, each of the plurality of semiconductor layers defining a channel region of the semiconductor structure (semiconductor fins 20a/20b vertically stacked on substrate 12); a first source/drain region located on one end of the plurality of semiconductor layers (source/drain features 38/40); a metal gate stack surrounding each of the plurality of semiconductor layers (gate electrode layer 48 surrounds semiconductor layers 16a/16b); an inner spacer located between each of the plurality of semiconductor layers, the inner spacer separating the metal gate stack from the first source/drain region (inner spacers 36 separate gate electrode layer 48 from source/drain features 38/40 as shown in Liao FIG. 10A); and a sidewall spacer located along opposite sidewalls of the metal gate stack, wherein a second surface of the inner spacer is in contact with the sidewall spacer and outer sidewalls of the inner spacer are vertically aligned with outer sidewalls of the sidewall spacer (left and right surfaces of inner spacers 36 are in contact with sidewall spacer 34, (Liao FIG. 5); and outer sidewalls of the inner spacers are vertically aligned with outer sidewalls of the sidewall spacer (Liao FIG. 10A)).
Liao does not explicitly disclose the inner spacer having a concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region, and curving inward in a direction towards the first source/drain region and relative to an outer surface of the metal gate stack, or the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer.
However, in the same field of endeavor, Greene discloses in Greene FIG. 11 and associated text the inner spacer having a concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region, and curving inward in a direction towards the first source/drain region and relative to an outer surface of the metal gate stack (inner spacers 702 have the claimed structure as shown, with the wider opposite outer potions being the top and bottom portions of the inner spacers, which are wider a middle portion of the inner spacers between the opposite outer portions, in the middle of the inner spacers in the vertical direction, which is perpendicular to a length of the channel region).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Liao with the concave inner spacer of Greene, which would position the inner spacer such that the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer (opposite outer portions of Greene’s inner spacer would extend laterally across the spacer, ending at an interface with Liao’s sidewall spacer) to provide a transistor where there are no voids left in the source/drain structures when sacrificial layers are etched away to be replaced by the metal gate (Greene [0044]).
Regarding dependent claim 4, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the inner spacer has a shape that includes two of the opposite outer portions and the middle portion, the two of the opposite outer portions being connected by the middle portion in the shape of a letter "C", the two of the opposite outer portions having a width that is larger than a width of the middle portion (the inner spacer 702 has the claimed structure as shown).
Regarding dependent claim 5, Liao, as modified by Greene, further discloses in Liao FIG. 4 and associated text a portion of the semiconductor substrate below the plurality of semiconductor layers being located between shallow trench isolation regions (portions of substrate 12 are beneath insulation layer 22, which may be a shallow trench insulation (Liao [0018])).
Regarding dependent claim 6, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the concave surface of the inner spacer is relative to an outer surface of the metal gate stack for providing an uniform thickness to the inner spacer and protecting the first source/drain region, wherein edges of the plurality of semiconductor layers have a substantially square shape (inner spacers 702 have a concave surface relative to gate conductors 1004, which have convex outer surfaces; the thickness of the inner spacer 702 is substantially uniform; and edges of the semiconductor layers are square). Examiner is interpreting "uniform thickness to the inner spacer" to be similar to the representation in Figure 8D of the application where inner spacer region 830b is of substantially uniform thickness while inner spacer region 830a at the edges is thicker than in region 830b.
Regarding dependent claim 7, Liao, as modified by Greene, further discloses the plurality of semiconductor layers comprises at least one selected from a group consisting of a nanosheet, a nanowire, and a nano-ellipse (the semiconductor stack 18a/18b is made of nanosheets (Liao [0019])).
Regarding independent claim 8, Liao discloses in Liao FIG. 1-20C and associated text a method of forming a semiconductor structure, comprising: forming a plurality of semiconductor layers vertically stacked over a semiconductor substrate, each of the plurality of semiconductor layers defining a channel region of the semiconductor structure (semiconductor stacks 18a/18b vertically stacked on substrate 12), wherein the forming the plurality of semiconductor layers includes forming a nanosheet stack on the substrate, the nanosheet stack comprising an alternating sequence of sacrificial semiconductor layers and semiconductor channel layers (semiconductor stack 18a/18b is nanosheets (Liao [0019]) comprising semiconductor layers 14a/14b (sacrificial layers) and 16a/16b (channel layers)); forming a first source/drain region located on one end of the plurality of semiconductor layers (source/drain features 38/40); forming a metal gate stack surrounding each of the plurality of semiconductor layers (gate electrode layer 48 surrounds semiconductor layers 16a/16b); forming an inner spacer located between each of the plurality of semiconductor layers, the inner spacer separating the metal gate stack from the first source/drain region (inner spacers 36 separate gate electrode layer 48 from source/drain features 38/40 as shown in Liao FIG. 10A); patterning the nanosheet stack to form a nanosheet fin (semiconductor fins 20a/20b); forming a dummy gate on the nanosheet fin (sacrificial gate structures 24a/24b/24c); etching outer portions of the sacrificial semiconductor layers, wherein the etching forms a first indentation region (semiconductor layers 14a/14b are etched to form spacer cavities (Liao [0036])); conformally depositing a spacer material to form a sidewall spacer along opposite sidewalls of the dummy gate (inner spacers 36 are formed conformally (Liao [0037])); using the sidewall spacer along sidewalls of the dummy gate as a mask, etching the nanosheet fin in a way such that a remaining portion of the nanosheet fin is vertically aligned with the sidewall spacer (semiconductor fins 20a/20b are etched where not covered by sacrificial gate structures including sidewall spacers 34, resulting in remaining portions being vertically aligned with the sidewall spacers 34 as shown in Liao FIG. 5), wherein a second surface of the inner spacer is in contact with the sidewall spacer and outer sidewalls of the inner spacer are vertically aligned with outer sidewalls of the sidewall spacer (left and right surfaces of inner spacers 36 are in contact with sidewall spacer 34, (Liao FIG. 5); and outer sidewalls of the inner spacers are vertically aligned with outer sidewalls of the sidewall spacer (Liao FIG. 10A));
Liao does not explicitly disclose the inner spacer having a concave surface curving inward in a direction towards the first source/drain region, the concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region, and curving inward in a direction towards the first source/drain region and relative to an outer surface of the metal gate stack, depositing a sacrificial dielectric layer within the first indentation region, the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer, removing the sacrificial dielectric material, or etching second outer portions of the sacrificial semiconductor layers to form a second indentation region.
However, in the same field of endeavor, Greene discloses in Greene FIG. 1-12 the inner spacer having a concave surface curving inward in a direction towards the first source/drain region, the concave surface comprising opposite outer portions of the inner spacer each having a width greater than a width of a middle portion of the inner spacer along a direction perpendicular to a length of the channel region, and curving inward in a direction towards the first source/drain region and relative to an outer surface of the metal gate stack (inner spacers 702 have the claimed structure as shown in Greene FIG. 11, with the wider opposite outer potions being the top and bottom portions of the inner spacers, which are wider a middle portion of the inner spacers between the opposite outer portions, in the middle of the inner spacers in the vertical direction, which is perpendicular to a length of the channel region); depositing a sacrificial dielectric layer within the first indentation region (dielectric plugs 502 are deposited in recesses 402); removing the sacrificial dielectric material (dielectric plugs 502 are etched away (Greene [0044])); and etching second outer portions of the sacrificial semiconductor layers to form a second indentation region (a second recessing etch is performed on the tails 404 of sacrificial layers 104 (Greene [0036])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor structure of Liao with the concave inner spacer of Greene, which would position the inner spacer such that the opposite outer portions of the inner spacer being located at an interface between the second surface of the inner spacer and the sidewall spacer (opposite outer portions of Greene’s inner spacer would extend laterally across the spacer, ending at an interface with Liao’s sidewall spacer) to provide a transistor where there are no voids left in the source/drain structures when sacrificial layers are etched away to be replaced by the metal gate (Greene [0044]).
Regarding independent claim 9, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the inner spacer having the concave surface comprises opposite outer portions of the inner spacer being wider than a middle portion of the inner spacer (the inner spacer 702 has the claimed structure as shown).
Regarding dependent claim 10, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the inner spacer has a shape that includes two opposite segments and a vertical segment, the two opposite segments being connected by the vertical segment in the shape of a letter "C", the two opposite segments having a width that is larger than a width of the vertical segment (the inner spacer 702 has the claimed structure as shown).
Regarding dependent claim 11, Liao, as modified by Greene, further discloses in Greene FIG. 11 and associated text the concave surface of the inner spacer is relative to an outer surface of the metal gate stack for providing an uniform thickness to the inner spacer and protecting the first source/drain region, wherein edges of the plurality of semiconductor layers have a substantially square shape (inner spacers 702 have a concave surface relative to gate conductors 1004, which have convex outer surfaces; the thickness of the inner spacer 702 is substantially uniform; and edges of the semiconductor layers are square). Examiner is interpreting "uniform thickness to the inner spacer" to be similar to the representation in Figure 8D of the application where inner spacer region 830b is of substantially uniform thickness while inner spacer region 830a at the edges is thicker than in region 830b.
Regarding dependent claim 12, Liao, as modified by Greene, further discloses the plurality of semiconductor layers comprises at least one of a nanosheet, a nanowire, and a nano-ellipse (the semiconductor stack 18a/18b is made of nanosheets (Liao [0019])).
Regarding dependent claim 15, Liao, as modified by Greene, further discloses the sacrificial dielectric layer has good etch selectivity to the sacrificial semiconductor layers and includes at least one material selected from a group consisting of SiO2, SiBCN, SiCN, and SiOCN (dielectric plug 502 is SiO2 and has etch selectivity relative to the tails 404 of sacrificial layers 106 (Greene [0062])).
Regarding dependent claim 18, Liao, as modified by Greene, further discloses in Liao FIG. 10A and associated text forming the inner spacer on one side of the sacrificial semiconductor layers (as shown in Liao FIG. 10A); epitaxially growing the first source/drain region (source/drain features 38/40 are epitaxial (Liao [0038])); and forming a dielectric layer above the first source/drain region and between portions of the sidewall spacer being adjacent to the first source/drain regions (interlayer dielectric layer 44).
Regarding dependent claim 19, Liao, as modified by Greene, further discloses in Liao FIG. 7 and associated text removing the dummy gate, wherein removing the dummy gate creates a recess between the sidewall spacer (sacrificial gate electrode layer 28 is initially between the sidewall spacer 34, leaving a cavity once removed (Liao [0046]-[0048])); and selectively removing the sacrificial semiconductor layers (semiconductor layers 14a/14b are selectively removed (Liao [0047])).
Regarding dependent claim 20, Liao, as modified by Greene, further discloses in Liao FIG. 10A and associated text forming the metal gate stack within the recess, the metal gate stack surrounding the plurality of semiconductor layers and being separated from the first source/drain region by the inner spacer (gate electrode layer 48 has the claimed structure).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200075718 A1, pertaining to a variety of inner spacer geometries.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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