Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendments filed 06/11/2025 and 07/07/2025, in which: claim(s) 1, 14, and 19 is/are amended; claim(s) 10, 20, and 23-30 is/are cancelled; and the rejection of the claims are traversed. Claim(s) 1-9, 11-19, and 22 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments filed 06/11/2025, with respect to the rejection(s) of claim(s) 1-9, 11-19, and 22 under 35 U.S.C. 102(a)(2) and/or 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yang et al. (US 10840190 B1, hereinafter YANG) and further in view of Yu et al. (US 20170186715 A1, hereinafter YU).
Claim Objections
Claim 19 is objected to because of the following informalities: “a first contact portion” is a probably typo as there is already recited in the claim “a contact portion”, which appears to refer to the same structure. For the purpose of examination, the examiner interprets “a first contact portion” broadly, potentially including configurations where it is read on by structures which also read on “a contact portion”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first bonding pad" (sans “structure”). There is insufficient antecedent basis for this limitation in the claim. It is unclear whether the term refers to “a first bonding pad structure” recited earlier in the claim or a new and distinct feature. In the specification it is evident that a first bonding pad is a particular part of a first bonding pad structure, not identified as the structure itself, but it is unclear whether this is the case for the elements in the claim language. Therefore, for the purpose of examination, Examiner interprets the claim as reading “…wherein the first bonding pad structure includes a first contact portion and a first bonding pad, the first contact portion being in contact with the test pad inside the first bonding insulating layer and having a lower surface positioned opposite to the test pad, the first bonding pad bonded to the dummy pad, and a first seed layer disposed between the first bonding pad and the first contact portion…”. However, if it is the applicant’s intention to refer to the same feature using both terms, it is recommended to amend all instances of “first bonding pad” (sans “structure”) to “first bonding pad structure”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-9, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 10840190 B1, hereinafter YANG), and further in view of Yu et al. (US 20170186715 A1, hereinafter YU).
Regarding independent claim 1, YANG discloses a semiconductor package (Fig. 8/10D; see annotated Figures, below (note that certain features indicated in the figure are no longer relied upon for the rejection)) comprising:
a base structure (Fig. 1F, 8/TD1) including a body (Fig. 1F,8/110) having a rear surface (Fig 1F,8/side of 110 facing 124) on which a dummy pad (Fig. 8/154) and a connection pad (Fig. 8/152) are arranged and a rear insulating layer (Fig. 1F,8/140) disposed on the rear surface and surrounding the dummy pad and the connection pad (Fig. 1F,8/140 surrounds 154 and 152); and
a semiconductor chip (Fig. 4B,8/TS2) disposed on the base structure (Fig. 8/TS2 disposed on Fig 1F,8/110) and including a semiconductor layer (Fig. 4B,8/110) having a front surface facing the rear surface of the body (Fig. 4B,8/side of 110 facing 224), a test pad (Fig. 8/222’ disposed over 154) and an input/output pad (Fig. 8/222’ disposed over leftmost 152; the terms “test” and “input/output” pads do not further limit structurally the claimed pads and 222’ are at least capable of being used in said manner per MPEP 2111, 2112 and/or 2114) disposed on the front surface of the semiconductor layer (Fig. 8/222’ are disposed on 110 of TS2), a first bonding insulating layer (Fig. 4B/224 and 226’) surrounding the test pad and the input/output pad (Fig. 4B/224 and 226’ surround the 222’), a first bonding pad structure (Fig. 8/454) disposed between the test pad and the dummy pad (Fig. 8/454 is between 222’ and 154), the first bonding insulating layer having a first opening exposing at least a portion of the test pad (opening 226b (Fig. 4B) through 226’ exposes a portion of test pad 222’), a second bonding pad structure (Fig. 8/330 + leftmost 452) disposed between the input/output pad and the connection pad (Fig 8/330+leftmost 452 are between 222’ and 152), and a second bonding insulating layer (Fig. 4B,8/440) disposed on the first bonding insulating layer (440 is disposed on 226’) and surrounding at least a portion of each of the first bonding pad structure and the second bonding pad structure (440 surrounds portions of 454, 452, and 330),
wherein the first bonding pad structure bonded to the dummy pad (Fig. 8/454 bonded to 154; column 8, lines 5-7),
the second bonding pad structure includes a second contact portion being in contact with the input/output pad (Fig. 8/top of 330 in contact with 222’) inside the first bonding insulating layer and having a lower surface (second contact portion comprises a lower surface) positioned opposite to the input/output pad (Fig. 8/top of 330), a second bonding pad bonded to the connection pad (Fig. 8/452 is bonded to 152, column 20, lines 5-7), and a second seed layer disposed between the second bonding pad and the second contact portion (column 14, lines 53-57 seed layer lining 452) and extending in the first direction (Fig. 8/seed layer lines top of 452 therefore is parallel to it),
the second bonding insulating layer is in contact with a side surface of each of the second seed layer (Fig. 4B,8/440+226’ is in contact with sides of seed layer between 330 and 452) and the second bonding pad (Fig. 4B,8/440+226’ is in contact with sides of 452).
YANG does not explicitly disclose wherein the first bonding pad structure includes a first contact portion and a first bonding pad, the first contact portion being in contact with the test pad inside the first bonding insulating layer and having a lower surface positioned opposite to the test pad, the first bonding pad bonded to the dummy pad, and a first seed layer disposed between the first bonding pad and the first contact portion and extending in a first direction, parallel to the lower surface of the first contact portion, the second bonding insulating layer is in contact with a side surface of each of the first seed layer and the first bonding pad, the first contact portion includes a first contact seed layer extending along an inner wall surface of the first opening and an exposed surface of the test pad and a first contact via filling the first opening on the first contact seed layer, or a lower end of the first contact seed layer is in contact with the first seed layer.
However, in the same field of endeavor, YU discloses in YU FIG. 3, 7-8, and 11 and associated text wherein the first bonding pad structure includes a first contact portion and a first bonding pad (54 and 66B respectively), the first contact portion being in contact with the test pad inside the first bonding insulating layer and having a lower surface positioned opposite to the test pad (54 contacts pad 34B, corresponding to the test pad, in dielectric layers 32 and 40, corresponding to the first bonding insulating layer, and the top surface of 54, corresponding to the lower surface, is opposite pad 34B), the first bonding pad bonded to the dummy pad (66B is bonded to 74B, corresponding to the dummy pad), and a first seed layer disposed between the first bonding pad and the first contact portion and extending in a first direction, parallel to the lower surface of the first contact portion (seed layer 62 and barrier layer 60, together considered the first seed layer, extends horizontally and is disposed between 54 and 66B), the second bonding insulating layer is in contact with a side surface of each of the first seed layer and the first bonding pad (dielectric barrier layer 68 and dielectric material 70, together corresponding to the second bonding insulating layer, is in contact with sides of both the first seed layer 60/62 and the first bonding pad 66B), the first contact portion includes a first contact seed layer and a first contact via filling the first opening on the first contact seed layer (conductive barrier layer 56, interpreted as the first contact seed layer, and metal 58 fill via 54), and a lower end of the first contact seed layer is in contact with the first seed layer (conductive barrier 60, part of the seed layer as interpreted above, is in contact with 58) the first contact seed layer extending along an inner wall surface of the first opening and an exposed surface of the test pad (conductive barrier layer 56, corresponding to the first seed layer, extends along via 54 and pad 34B, corresponding to the test pad).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the structure of YU’s via 54 and pad 66B including seed layers for the dummy connectors 454 of YANG since both structures provide a connection from a lower pad to a direct bonding surface and since the structure of YU provides pads with stronger bonds, lower annealing temperature, and shorter annealing time (YU [0031]).
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Annotated versions of Fig. 8 of YANG
Regarding claim 2, YANG, as modified by YU, discloses the semiconductor package of claim 1, wherein the lower surface of the first contact portion and the lower surface of the second contact portion are coplanar with each other (as combined, the top surface of via 54 of YU, corresponding to the lower surface of the first contact portion, would be coplanar to the top of YANG’s 330, corresponding to the lower surface of the second contact portion, which would allow both the first and second bonding pads to be formed in the same process, reducing the steps of the manufacturing process).
Regarding claim 3, YANG, as modified by YU, discloses in YU FIG. 7-8 and associated text the semiconductor package of claim 1 wherein the first seed layer overlaps the first bonding pad in a second direction, perpendicular to the first direction, and the second seed layer overlaps the second bonding pad in the second direction (seed layer 62 and bonding pads 66A and 66B are overlapping in a vertical direction).
Regarding claim 4, YANG, as modified by GAO and YU, discloses in YU FIG. 7-8 and associated text the semiconductor package of claim 1, wherein the first seed layer has a width equal to or smaller than a width of the first bonding pad, and the second seed layer has a width equal to or smaller than a width of the second bonding pad (remaining portions of seed layer 62 beneath pads 66A and 66B are equal in width to the pads above them).
Regarding claim 8, YANG, as modified by YU, discloses the semiconductor package of claim 1, wherein the first and second bonding pads include copper (Cu) or a Cu alloy (YANG Fig. 8/452 (second bonding pad) is at the hybrid bonding interface IF, which can include copper-to-copper bonding column 10, line 67 – column 11, line 3; YU FIG. 11/66B is copper (YU [0026]-[0027])), and the test pad and the input/output pad include aluminum (Al) or an Al alloy (Fig. 4B/222 which are similar to the 122, column 9, lines 18-22, and the 122 can be aluminum, column 3, lines 25-28).
Regarding claim 9, YANG, as modified by YU, discloses the semiconductor package of claim 8, wherein the first and second seed layers include titanium (Ti) or a Ti alloy (conductive barrier layer 60, considered part of the first seed layer as interpreted above, is titanium (YU [0026]); 452 includes a seed layer, as interpreted above, and seed layers may include titanium (YANG (25))).
Regarding claim 13, YANG, as modified by GAO and YU, discloses the semiconductor package of claim 1, wherein the rear insulating layer (Fig. 8/140) and the second bonding insulating layer (Fig. 4B,8/440+222’) include silicon oxide or silicon nitride (140 is the un-patterned 140’, column 5, lines 22-24; 140’ includes silicon oxide or nitride, column 5, lines 16-18; Fig. 2A/240 is a similar material to 140, column 10, lines 22, 38-39; and 440 is similar material to 240, column 14, lines 23-25).
Regarding independent claim 19, YANG discloses a semiconductor package (Fig. 8/10D; see annotated Figures, below) comprising:
a base structure (Fig. 1F, 8/TD1) including a body (Fig. 1F,8/110) having a rear surface (Fig 1F,8/side of 110 facing 124) on which a dummy pad is disposed (Fig. 8/154) and a rear insulating layer (Fig. 1F,8/140) disposed on the rear surface and surrounding the dummy pad (Fig. 1F,8/140 surrounds 154); and
a semiconductor chip (Fig. 4B,8/TS2) disposed on the base structure (Fig. 8/TS2 disposed on Fig 1F,8/110) and including a semiconductor layer (Fig. 4B,8/110) having a front surface facing the rear surface of the body (Fig. 4B,8/side of 110 facing 224), a test pad (Fig. 8/222’ disposed over 154; the term “test” pad does not further limit structurally the claimed pads and 222’ are at least capable of being used in said manner per MPEP 2111, 2112 and/or 2114) disposed on the front surface of the semiconductor layer (Fig. 8/222’ are disposed on 110 of TS2), a bonding pad structure (Fig. 8/454) disposed between the test pad and the dummy pad (Fig. 8/454 is between 222’ and 154), and a bonding insulating layer (Fig. 4B,8/440) surrounding at least a portion of the bonding pad structure (440 surrounds a portion of 454), a first bonding insulating layer (Fig. 4B/224 and 226’) surrounding the test pad (Fig. 4B/224 and 226’ surround the 222’) and having a first opening exposing at least a portion of the test pad (opening 226b (Fig. 4B) through 226’ exposes a portion of test pad 222’),
wherein the bonding pad structure bonded to the dummy pad (Fig. 8/454 bonded to 154; column 8, lines 5-7),
YANG does not explicitly disclose wherein the bonding pad structure includes a contact portion being in contact with the test pad and having a lower surface positioned opposite to the test pad, a bonding pad bonded to the dummy pad, and a seed layer disposed between the bonding pad and the contact portion and extending in a first direction parallel to the lower surface of the first contact portion, the bonding insulating layer is in direct contact with a side surface of the bonding pad, a first contact portion includes a first contact seed layer extending along an inner wall surface of the first opening and an exposed surface of the test pad and a first contact via filling the first opening on the first contact seed layer, or a lower end of the first contact seed layer is in contact with the seed layer.
However, in the same field of endeavor, YU discloses in YU FIG. 3, 7-8, and 11 and associated text wherein the bonding pad structure includes a contact portion (via 54) being in contact with the test pad and having a lower surface positioned opposite to the test pad (54 contacts pad 34B, corresponding to the test pad, and the top surface of 54, corresponding to the lower surface, is opposite pad 34B), a bonding pad bonded to the dummy pad (66B is bonded to 74B, corresponding to the dummy pad), and a seed layer disposed between the bonding pad and the contact portion and extending in a first direction parallel to the lower surface of the first contact portion (the remainders of seed layer 62 and barrier layer 60 under pad 66B after etching in YU FIG. 8, together considered the seed layer, extends horizontally and is disposed between 54 and 66B), a first contact portion includes a first contact seed layer extending along an inner wall surface of the first opening and an exposed surface of the test pad (conductive barrier layer 56, corresponding to the first contact seed layer, extends along via 54 and pad 34B, corresponding to the test pad) and a first contact via filling the first opening on the first contact seed layer (conductive barrier layer 56, interpreted as the first contact seed layer, and metal 58 fill via 54), and a lower end of the first contact seed layer is in contact with the first seed layer (conductive barrier 60, part of the seed layer as interpreted above, is in contact with 58).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the structure of YU’s via 54 and pad 66B including seed layers for the dummy connectors 454 of YANG since both structures provide a connection from a lower pad to a direct bonding surface and since the structure of YU provides pads with stronger bonds, lower annealing temperature, and shorter annealing time (YU [0031])
Claims 5 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over YANG, and further in view of YU and Cheng et al. (US 20110101527 A1, hereinafter CHENG).
Regarding claim 5, YANG, as modified by YU, discloses the semiconductor package of claim 1. They do not explicitly disclose the side surface of the first seed layer is spaced apart from the side surface of the first bonding pad, or the side surface of the second seed layer is spaced apart from the side surface of the second bonding pad.
However, YU discloses in YU FIG. 7-8 and associated text removal of the exposed parts of seed layer 62 and barrier layer 60 through an etching step.
Additionally, in the same field of endeavor, CHENG discloses in CHENG FIG. 1D and associated text the side surface of a seed layer is spaced apart from the side surface of a bonding pad (Cu seed layer 111U is undercut with respect to Cu metal pillar 125) as a result of an over-etching of seed layer 111U.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of YANG, as modified by YU, with the over-etching of the seed layer (performing the same process on both the first and second bonding pads to reduce the number of steps) to provide complete removal of the exposed seed layer (CHENG [0034]), forming an undercut in the process such that the side surface of the first seed layer is spaced apart from the side surface of the first bonding pad, and the side surface of the second seed layer is spaced apart from the side surface of the second bonding pad.
Regarding claim 21, YANG, as modified by YU, discloses in YU FIG. 8 and associated text the semiconductor package of claim 19, wherein the seed layer has a width greater than a width of the lower surface of the contact portion in the first direction (60+62 are wider than via 54 in the horizontal direction). They do not explicitly disclose the seed layer has a width smaller than a width of the bonding pad in the first direction.
However, YU discloses in YU FIG. 7-8 and associated text removal of the exposed parts of seed layer 62 and barrier layer 60 through an etching step.
Additionally, in the same field of endeavor, CHENG discloses in CHENG FIG. 1D and associated text the seed layer has a width smaller than a width of the bonding pad in the first direction (Cu seed layer 111U is undercut with respect to Cu metal pillar 125) as a result of an over-etching of seed layer 111U.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of YANG, as modified by YU, with the over-etching of the seed layer (performing the same process on both the first and second bonding pads to reduce the number of steps) to provide complete removal of the exposed seed layer (CHENG [0034]), forming an undercut in the process such that the seed layer has a width smaller than a width of the bonding pad in the first direction.
Regarding claim 22, YANG, as modified by YU, discloses the semiconductor package of claim 19 They do not explicitly disclose wherein at least a portion of the bonding pad does not overlap the seed layer in a second direction, perpendicular to the first direction.
However, YU discloses in YU FIG. 7-8 and associated text removal of the exposed parts of seed layer 62 and barrier layer 60 through an etching step.
Additionally, in the same field of endeavor, CHENG discloses in CHENG FIG. 1D and associated text at least a portion of the bonding pad does not overlap the seed layer in a second direction, perpendicular to the first direction (Cu seed layer 111U is undercut with respect to Cu metal pillar 125) as a result of an over-etching of seed layer 111U.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the structure of YANG, as modified by YU, with the over-etching of the seed layer (performing the same process on both the first and second bonding pads to reduce the number of steps) to provide complete removal of the exposed seed layer (CHENG [0034]), forming an undercut in the process such that at least a portion of the bonding pad does not overlap the seed layer in a second direction, perpendicular to the first direction.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over YANG, and further in view of YU and Mueller et al. (US-20210175192-A1, hereinafter MUELLER).
Regarding claim 6, YANG, as modified by YU, discloses the semiconductor package of claim 1. They do not explicitly disclose wherein a width of the first bonding pad is greater than a width of the second bonding pad.
However, in the same field of endeavor, MUELLER teaches wherein a width (Fig. 1B/115,128 width w1) of the first bonding (metallization) pad is greater than a width (Fig. 1B/114,127 width w2) of the second bonding pad. MUELLER teaches that there is a motivation to make 115 and128 wider to accommodate the width of a probe tip (paragraphs [0035], lines 8-10 and [0063], lines 10-12) during testing. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the wider pad of MUELLER into the package of YANG to achieve the desired result of a pad that can be probed, so as to carry out the testing of the die.
Regarding claim 7, YANG, as modified by YU and MUELLER, disclose in MUELLER the semiconductor package of claim 6, wherein the width of the first bonding pad is about 30 µm or greater (Fig. 1B/115, 128 w1 up to 100 µm, paragraph [0063], lines 8-10), and the width of the second bonding pad is about 20 µm or smaller (Fig. 1B/114, 127 w2 up to 20 µm, paragraph [0063], lines 8-10). As discussed for claim 6 above, there is a motivation to make the 128 wide enough to accommodate a probe tip. Further there is motivation to keep the 127 smaller, so as to accommodate more connections in the interface 103, supporting greater interconnectivity between the devices 101 and 102, which enhances performance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to employ the prescribed widths in the claim in order to achieve the desired result of a testable circuit that sacrifices minimal loss of interconnectivity.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over YANG, and further in view of YU and Gao et al. (US-20200335408-A1, hereinafter GAO).
Regarding claim 11, YANG, as modified by YU discloses the semiconductor package of claim 1. YANG does not explicitly disclose wherein the test pad has a protrusion having a pile-up surface.
However, in the same field of endeavor, GAO teaches wherein the test (probe) pad (Fig. 1/104, paragraph [002], lines 1-6) has a protrusion (protrusions of Fig. 1/104, paragraph [0002], line 6) having a pile-up surface (defined in the instant application as deformations, page 1, line 20). Testing with probes is routinely used in semiconductor manufacturing, which requires that the probes make physical contact with the test/probe pad (paragraph [0002], line 3). The deformations are an effect of the probing and thus are a necessary part of performing test. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to have the test pad of YANG deformed by the pile-up of GAO in order to obtain the desired result of incorporating a tested component into the semiconductor package.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over YANG, and further in view of YU and Hu et al. (US-20210057309-A1, hereinafter HU).
Regarding claim 12, YANG, as modified by YU, discloses the semiconductor package of claim 1. They do not explicitly disclose wherein the base structure further includes: individual elements disposed on a front surface of the body positioned opposite to the rear surface and a through-via penetrating through the body and electrically connected to the individual elements, wherein the connection pad is electrically connected to the through-via, and the dummy pad is electrically insulated from the through-via.
However, in the same field of endeavor, HU teaches wherein the base structure (Fig. 3D/T2, paragraph [0033], lines 5-6) further includes: individual elements (Fig. 3D/260 which can be a plurality, paragraph [0043], line 3) disposed on a front surface of the body (Fig. 3D/260 are disposed on 252b) positioned opposite to the rear surface (Fig. 3B/S1 which is near the interface IF) and a through-via (Fig. 3D/230, paragraph [0029], line 3) penetrating through the body and electrically connected to the individual elements (Fig 3D/230 is connected to 260 through 252), wherein the connection pad is electrically connected to the through-via (Fig. 3D/BE1 is electrically connected to 230 by 220 and AP2), and the dummy pad is electrically insulated from the through-via (Fig. 3D/BE0, BC0 are bonded and electrically floating, paragraph [0025], lines 11-13).
In face-to-face hybrid bonded structures there is a need to get electric signals in and out of the package. There is thus a motivation to provide this access by a feature such as a through-via. As dummy vias are used for bonding (paragraph [0025], line 6) and not signal propagation, it would be a waste of space and processing steps to connect the through-vias to them. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to add the base structure of HU to the package of YANG in order to economically provide signal inputs and outputs for the package.
Claims 14-18 rejected under 35 U.S.C. 103 as being unpatentable over YANG, and further in view of YU and J.W. Huang et al. (“Copper-to-copper direct bonding using different (111) surface ratios of nanotwinned copper films”, 2019 ICEP Proceedings, hereafter HUANG).
Regarding independent claim 14, YANG discloses a semiconductor package (Fig. 8/10D; see annotated Figures, below) comprising:
a base structure (Fig. 1F, 8/TD1) including a body (Fig. 1F,8/110) having a rear surface (Fig 1F,8/side of 110 facing 124) on which a dummy pad (Fig. 8/154) and a connection pad (Fig. 8/152) are arranged and a rear insulating layer (Fig. 1F,8/140) disposed on the rear surface and surrounding the dummy pad and the connection pad (Fig. 1F,8/140 surrounds 154 and 152); and
a semiconductor chip (Fig. 4B,8/TS2) disposed on the base structure (Fig. 8/TS2 disposed on Fig 1F,8/110) and including a semiconductor layer (Fig. 4B,8/110) having a front surface facing the rear surface of the body (Fig. 4B,8/side of 110 facing 224), a test pad (Fig. 8/222’ disposed over 154) and an input/output pad (Fig. 8/222’ disposed over leftmost 152; the terms “test” and “input/output” pads do not further limit structurally the claimed pads and 222’ are at least capable of being used in said manner per MPEP 2111, 2112 and/or 2114) disposed on the front surface of the semiconductor layer (Fig. 8/222’ are disposed on 110 of TS2), a first bonding pad structure (Fig. 8/454) disposed between the test pad and the dummy pad (Fig. 8/454 is between 222’ and 154), a first bonding insulating layer (Fig. 4B/224 and 226’) surrounding the test pad and the input/output pad (Fig. 4B/224 and 226’ surround the 222’) and having a first opening exposing at least a portion of the test pad (opening 226b (Fig. 4B) through 226’ exposes a portion of test pad 222’), a second bonding pad structure (Fig. 8/330 + leftmost 452) disposed between the input/output pad and the connection pad (Fig 8/330+leftmost 452 are between 222’ and 152), and a bonding insulating layer (Fig. 4B,8/440) disposed on the front surface of the semiconductor layer (440 is disposed on 110 on the side facing 224, corresponding to the front surface) and surrounding at least a portion of each of the first bonding pad structure and the second bonding pad structure (440 surrounds portions of 454, 452, and 330),
wherein the first bonding pad structure bonded to the dummy pad (Fig. 8/454 bonded to 154; column 8, lines 5-7),
the second bonding pad structure includes a second contact portion being in contact with the input/output pad (Fig. 8/top of 330 in contact with 222’), a second bonding pad bonded to the connection pad (Fig. 8/452 is bonded to 152, column 20, lines 5-7), and a second seed layer extending in the first direction (Fig. 8/seed layer lines top of 452 therefore is parallel to it) between the second bonding pad and the second contact portion (column 14, lines 53-57 seed layer lining 452),
the second bonding insulating layer is in contact with a side surface of each of the second seed layer (Fig. 4B,8/440+226’ is in contact with sides of seed layer between 330 and 452) and the second bonding pad (Fig. 4B,8/440+226’ is in contact with sides of 452).
YANG does not explicitly disclose wherein the first bonding pad structure includes a first contact portion being in contact with the test pad, a first bonding pad bonded to the dummy pad, and a first seed layer extending in a first direction between the first bonding pad and the first contact portion, the first bonding pad includes first grain structures extending in a second direction, perpendicular to the first direction, the second bonding pad includes second grain structures extending in the second direction, the first contact portion includes a first contact seed layer extending along an inner wall surface of the first opening and an exposed surface of the test pad and a first contact via filling the first opening on the first contact seed layer, or a lower end of the first contact seed layer is in contact with the first seed layer.
However, in the same field of endeavor, YU discloses in YU FIG. 3, 7-8, and 11 and associated text wherein the first bonding pad structure includes a first contact portion being in contact with the test pad (54 contacts pad 34B, corresponding to the test pad), a first bonding pad bonded to the dummy pad (66B is bonded to 74B, corresponding to the dummy pad), and a first seed layer extending in a first direction between the first bonding pad and the first contact portion (seed layer 62 and barrier layer 60, together considered the first seed layer, extends horizontally and is disposed between 54 and 66B), the first contact portion includes a first contact seed layer and a first contact via filling the first opening on the first contact seed layer (conductive barrier layer 56, interpreted as the first contact seed layer, and metal 58 fill via 54), and a lower end of the first contact seed layer is in contact with the first seed layer (conductive barrier 60, part of the seed layer as interpreted above, is in contact with 58) the first contact seed layer extending along an inner wall surface of the first opening and an exposed surface of the test pad (conductive barrier layer 56, corresponding to the first seed layer, extends along via 54 and pad 34B, corresponding to the test pad).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the structure of YU’s via 54 and pad 66B including seed layers for the dummy connectors 454 of YANG since both structures provide a connection from a lower pad to a direct bonding surface and since the structure of YU provides pads with stronger bonds, lower annealing temperature, and shorter annealing time (YU [0031]).
Additionally, in the same field of endeavor, HUANG teaches that the first bonding pad includes first grain structures extending in a second direction, perpendicular to the first direction (growth by electroplating, page 52, abstract line 7, which is the plating of YANG – column 14, line 58 – leads to grain structure in copper – YANG column 18, line 37 – in the growth direction; HUANG Fig. 6), and
the second bonding pad includes second grain structures extending in the second direction (growth by electroplating, Abstract line 7, which is the plating of YANG – column 14, line 58 – leads to grain structure in copper – YANG column 18, line 37 – in the growth direction; HUANG Fig. 6).
There is a motivation in hybrid bonding to make the copper-to-copper bonds (YANG column 18, line 37) as strong as possible. Crystallographically-oriented films exhibit greater strength (HUANG page 54, column 2, line 6). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to apply the oriented crystal growth of HUANG to the structure of YANG, as modified by YU, to achieve strong hybrid bonding.
Regarding claim 15, YANG, as modified by YU and HUANG, discloses in HUANG the semiconductor package of claim 14, wherein the first and second grain structures have a 111 crystal orientation (page 52, abstract line 4: plating provides highly (111)-oriented copper). There is a motivation to use (111)-oriented nanotwinned crystal grains in hybrid bonding, since atoms diffuse quickly along this direction, facilitating greater diffusion across the interface, less voids, lower resistivity and better direct bonding (page 52, abstract lines 4-6, Introduction lines 11-16). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to apply the (111)-oriented growth of copper taught by HUANG to the structure of YANG, as previously modified by YU and HUANG, to achieve the result of better hybrid bonding.
Regarding claim 16, YANG, as modified by YU and HUANG, discloses in HUANG the semiconductor package of claim 15, wherein at least a portion of the first and second grain structures includes a nanotwin structure (page 52, abstract line 4 and Introduction, line 9). There is a motivation to use (111)-oriented nanotwinned crystal grains in hybrid bonding, since atoms diffuse quickly along this direction, facilitating greater diffusion across the interface, less voids, lower resistivity and better direct bonding (page 52, abstract lines 4-6, Introduction lines 11-16). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to apply the nanotwinned copper grains taught by HUANG to the structure of YANG, as previously modified by YU and HUANG, to achieve the result of better hybrid bonding.
Regarding claim 17, YANG, as modified by YU and HUANG, discloses in HUANG the semiconductor package of claim 14, wherein the first and second grain structures have a width of about 1 µm or smaller in the first direction (Fig. 1d, wherein grains at the surface – i.e. the first direction – demonstrate a width smaller than about 1 µm, as seen by scale reference in the Figure). There is a motivation to decrease the grain size (Fig. 1d), which increases the (111) Surface Ratio (Fig. 2), which in turn increases bonding strength (Fig. 8). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to apply grain sizes with a width of about 1 µm or smaller to achieve greater bond strength.
Regarding claim 18, YANG, as modified by YU and HUANG, discloses in HUANG the semiconductor package of claim 14, wherein the first and second grain structures have a height of about 0.5 µm or greater in the second direction (Fig. 6, which is a cross-sectional image – i.e. the second direction – wherein columnar grains demonstrate a height greater than about 0.5 µm, as seen by scale reference). As above for claim 17, there is a motivation to decrease grain area in order to increase bond strength. The decreased grain areas of Fig. 1 are associated with the grain heights of about 0.5 µm or greater of Fig. 6. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to apply grain heights of about 0.5 µm or greater to achieve the result of greater bond strength.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20160353568 A1, pertaining to similar contact via and bonding pad structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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