.DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 10/27/2025 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/27/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/08/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 9,406,676 to Yu et al (hereinafter Yu).
Regarding Claim 1, Yu discloses a semiconductor structure comprising:
a first transistor (Fig. 3H, solid left arrow), a second transistor (see below), and a third transistor (dotted right arrow) separated by their respective source/drain regions; and
a diffusion break (325) between the second transistor and the third transistor,
wherein a first distance between a center of a gate of the first transistor and a center of a gate of the second transistor is more than half of a second distance between the center of the gate of the second transistor and a center of a gate of the third transistor (see below).
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The drawings of Yu do not explicitly disclose more than two gates between the double diffusion break 215 and the single diffusion break. However, the description of the article pictured can be relied on, in combination with the drawings, for what they would reasonably teach one of ordinary skill in the art. In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977). It would have been reasonable to one of ordinary skill in the art to have formed more than two gates between the double diffusion break and the single diffusion break. Yu does not note a criticality for there only being two gates. Four or more gates would have resulted in a structure having a first distance between a center of a gate of the first transistor and a center of a gate of the second transistor being more than half of a second distance between the center of the gate of the second transistor and a center of a gate of the third transistor
Regarding Claim 2, Yu makes obvious the semiconductor structure of Claim 1, wherein the diffusion break has a width and the gates of the first, second, and third transistors have a length, wherein the width of the diffusion break is smaller than the length of the gates (Fig. 3H, lower portion of 325 having a width smaller than the length of the gates 220).
Regarding Claim 3, Yu makes obvious the semiconductor structure of Claim 2, wherein the first, second, and third transistors have their respective sidewall spacers (225), wherein two opposing sidewall spacers of the first transistor and the second transistor has a first gap and two opposing sidewall spacers of the second transistor and the third transistor has a second gap, and wherein the second gap equals two times the first gap plus the width of the diffusion break (Fig. 3H).
Regarding Claim 4, Yu makes obvious the semiconductor structure of Claim 1, wherein the diffusion break is adjacent to a source/drain (S/D) epi region of the second transistor and adjacent to a S/D epi region of the third transistor (Fig. 3H).
Regarding Claim 5, Yu makes obvious the semiconductor structure of Claim 4, wherein the diffusion break extends into a substrate underneath the second and third transistors to separate the S/D epi region of the second transistor from the S/D epi region of the third transistor (Fig. 3H).
Regarding Claim 6, Yu makes obvious the semiconductor structure of Claim 1 but does not explicitly disclose a fourth transistor next to the third transistor, wherein a third distance between the center of the gate of the third transistor and a center of a gate of the fourth transistor equals to the first distance.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed a fourth gate or more so as to form a series of transistors which would be needed for a desired circuit. As the gates are the same distance from each other, absent the diffusion break, it would have been obvious for a fourth gate to be a distance from the third gate that equals the distance between the first and second gates.
Regarding Claim 7, Yu makes obvious a semiconductor structure comprising:
a first transistor (220, Fig. 3H), a second transistor (structure right of the gate indicated as 220), a third transistor (structure far right of the gate indicated as 220 and to the right of diffusion break 325), and a fourth transistor (see below) separated by their respective source/drain regions (240), the first, second, third, and fourth transistors being unequally spaced (Fig. 3H); and
a diffusion break (325) between the second transistor and the third transistor.
Yu does not explicitly disclose a fourth gate structure.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed a fourth gate or more so as to form a series of transistors which would be needed for a desired circuit. As the gates are the same distance from each other, absent the diffusion break, it would have been obvious for a fourth gate to be a distance from the third gate that equals the distance between the first and second gates.
Regarding Claim 8, Yu makes obvious the semiconductor structure of Claim 7, wherein a center of a gate of the first transistor and a center of a gate of the second transistor has a first distance, and the center of the gate of the second transistor and a center of a gate of the third transistor has a second distance, wherein the second distance is less than two times the first distance (Fig. 3H).
Regarding Claim 9, Yu makes obvious the semiconductor structure of Claim 7, wherein the diffusion break has a width and the gates of the first, second, third, and fourth transistors have a length,
wherein the width of the diffusion break is smaller than the length of the gates (Fig. 3H, lower portion of 325 having a width smaller than the length of the gates 220).
Regarding Claim 10, Yu makes obvious the semiconductor structure of Claim 7, wherein the first, second, third, and fourth transistors have their respective sidewall spacers (225), wherein two opposing sidewall spacers of the first transistor and the second transistor has a first gap and two opposing sidewall spacers of the second transistor and the third transistor has a second gap,
wherein the second gap equals two times the first gap plus the width of the diffusion break (Fig. 3H).
Regarding Claim 11, Yu makes obvious the semiconductor structure of Claim 10, wherein a third gap between two opposing sidewall spacers of the third transistor and the fourth transistor equals the first gap since it would have been obvious for the third and fourth transistors to have been spaced apart the same as the first and second transistors are.
Regarding Claim 12, Yu makes obvious the semiconductor structure of Claim 7, wherein the diffusion break is adjacent to a source/drain (S/D) epi region of the second transistor and adjacent to a S/D epi region of the third transistor (Fig. 3H).
Regarding Claim 13, Yu makes obvious the semiconductor structure of Claim 12, wherein the diffusion break extends into a substrate underneath the second and third transistors to separate the S/D epi region of the second transistor from the S/D epi region of the third transistor (Fig. 3H).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to Claim 7 above, and further in view of US PG Pub 2022/0376044 to Yu et al (hereinafter Yu’044).
Regarding Claim 14, Yu discloses the semiconductor structure of Claim 7, wherein the diffusion break is a single diffusion break of dielectric material but does not explicitly disclose the first, second, third, and fourth transistors are nanosheet transistors.
Yu’044 discloses a diffusion break (290A, Fig. 34A) between two transistors that are nanosheet transistors (Fig. 34A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the transistors of Yu to comprise nanosheet transistors. Nanosheet transistors were known in the art, before the invention, for providing dense circuits with greater control over the channel regions through a gate-all-around structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893