DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed March 23, 2026. Claims 1, 13, and 17 have been amended. No claims have been added. No claims have been canceled. Claims 17-20 stand withdrawn. Currently, claims 1-3, 5, 7-14, and 16 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 10, 12-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chew et al. (US 20210343549 A1) herein after “Chew” in view of Suk et al. (US 20190051607 A1) herein after “Suk”, Chen et al. (US 20220122898 A1) herein after “Chen”, and Hsieh et al. (US 20150041985 A1) herein after “Hsieh”.
Regarding claim 1, Fig. 2d of Chew discloses a package device (Fig. 2d, semiconductor packages 200, ¶ [0040]), comprising:
an electronic unit (Fig. 2d, die 210, ¶ [0040]), comprising a first surface (Fig. 2d, major die surfaces 212, ¶ [0040]), a second surface (Fig. 2d, major die surfaces 211, ¶ [0040]) opposite to the first surface (212), and a first side surface (Fig. 2d, side die surfaces 213, ¶ [0040]) connecting the first surface (212) to the second surface (211);
a first insulating layer (Fig. 2d, dielectric passivation layer 244, ¶ [0043]) directly disposed on the second surface (211) and comprising a plurality of first openings (see Annotation 1, Fig. 2d of Chew, “pad openings”);
a second insulating layer (Fig. 2d, buffer layer 250, ¶ [0046]) directly disposed on the first insulating layer (244) and comprising a third surface (see Annotation 1, Fig. 2d of Chew, “250B”), a fourth surface (see Annotation 1, Fig. 2d of Chew, “250T”) opposite to the third surface (250B), and a second side surface (see Annotation 1, Fig. 2d of Chew, “250S”) connecting the third surface (250B) to the fourth surface (250T);
a first conductive layer (Fig. 2d, RDL via contacts 274, ¶ [0059]), and a portion of the first conductive layer (274) extending into the plurality of first openings (pad openings);
a third insulating layer (Fig. 2d, mold layer 290, ¶ [0069]) surrounding the electronic unit (210); and
a connecting element (Fig. 2d, RDL structure 270, ¶ [0059]) disposed on the second insulating layer (250) and electrically connected (Fig. 2d, “The RDL structure provides interconnections to the contact pads 242”, ¶ [0059]) to the electronic unit (210), wherein the third surface (250B) of the second insulating layer (250) is in contact with the second surface (211) of the electronic unit (210).
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Annotation 1, Fig. 2d of Chew
Chew fails to disclose wherein a side surface of the first insulating layer comprises an inclined surface;
a first conductive layer disposed between the first insulating layer and the second insulating layer;
wherein a thermal expansion coefficient of the first insulating layer is smaller than a thermal expansion coefficient of the second insulating layer,
wherein a roughness of a sidewall of one of the first openings is less than a roughness of a sidewall of one of the second openings,
wherein a first thickness of the first insulating layer is greater than or equal to 3 um and less than or equal to 8 um, a second thickness of the second insulating layer is greater than or equal to 13 um and less than or equal to 30 um, and a ratio of the first thickness to the second thickness is greater than or equal to 0.1 and less than or equal to 0.6.
In the similar field of endeavor of semiconductor packages, Fig. 3F of Suk discloses wherein a side surface (Fig. 3F, sidewall 320c, ¶ [0043]) of the first insulating layer (Fig. 3F, first lower insulating layer 320, ¶ [0047]) comprises an inclined surface (shown in Fig. 3F);
wherein a roughness of a sidewall of one of the first openings (Fig. 3F, opening in first lower insulating layer 320, ¶ [0047]) is less than a roughness of a sidewall of one of the second openings (Fig. 3F, opening in first upper insulating layer 310, ¶ [0047]) (Fig. 3F, “The surface roughness of the sidewall 310c of the first upper insulating layer 310 may be greater than the surface roughness of the sidewall 320c of the first lower insulating layer 320”, ¶ [0047]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the openings as disclosed by Suk, to prevent damage to the chip (see Suk, ¶ [0060]).
Suk fails to disclose a first conductive layer disposed between the first insulating layer and the second insulating layer;
wherein a thermal expansion coefficient of the first insulating layer is smaller than a thermal expansion coefficient of the second insulating layer,
wherein a first thickness of the first insulating layer is greater than or equal to 3 um and less than or equal to 8 um, a second thickness of the second insulating layer is greater than or equal to 13 um and less than or equal to 30 um, and a ratio of the first thickness to the second thickness is greater than or equal to 0.1 and less than or equal to 0.6.
In the similar field of endeavor of semiconductor devices, Fig. 10 of Chen discloses a first conductive layer (Fig. 10, conductive layer 118, ¶ [0014]) disposed between the first insulating layer (Fig. 10, insulating layers 112, ¶ [0014]) and the second insulating layer (Fig. 10, insulating layers 122, ¶ [0014]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the layer structure disclosed by Chen, to electrically insulate subsequent layers (see Chen, ¶ [0013]).
Chen fails to disclose wherein a thermal expansion coefficient of the first insulating layer is smaller than a thermal expansion coefficient of the second insulating layer,
wherein a first thickness of the first insulating layer is greater than or equal to 3 um and less than or equal to 8 um, a second thickness of the second insulating layer is greater than or equal to 13 um and less than or equal to 30 um, and a ratio of the first thickness to the second thickness is greater than or equal to 0.1 and less than or equal to 0.6.
In the similar field of endeavor of semiconductor devices, Fig. 3i of Hsieh discloses wherein a thermal expansion coefficient (“a CTE ranging from approximately 5-25 ppm/.degree. C”, ¶ [0042]) of the first insulating layer (Fig. 3i, insulating layer 132, ¶ [0042]) is smaller than a thermal expansion coefficient (“a CTE of 64 ppm/.degree. C”, ¶ [0049]) of the second insulating layer (Fig. 3i, insulating layer 156, ¶ [0049]),
wherein a first thickness of the first insulating layer (132) is greater than or equal to 3 um and less than or equal to 8 um (“insulating layer 132 is formed with a thickness in the range of approximately 3-7 .mu.m”, ¶ [0042]), a second thickness of the second insulating layer (156) is greater than or equal to 13 um and less than or equal to 30 um (“insulating layer 156 includes a thickness of approximately 10 .mu.m or greater.”, ¶ [0049]), and a ratio of the first thickness to the second thickness is greater than or equal to 0.1 and less than or equal to 0.6 (Hsieh discloses a ratio of less than 0.7).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the insulating layers disclosed by Hsieh, to prevent damage (see Hsieh, ¶ [0049]).
Regarding claim 2, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, and Fig. 2d of Chew further discloses wherein an angle of one of the first openings (pad openings) is different from an angle of one of the second openings (252) (“the bottom of the via openings of the buffer layer is smaller than the pad openings of the passivation layer”, ¶ [0058]).
Regarding claim 3, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, and Fig. 2d of Chew further discloses wherein the first conductive layer (274) is electrically connected to the electronic unit (210) through one of the first openings (pad openings).
Regarding claim 5, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, but Chew, Suk, and Hsieh fail to disclose wherein at least one of the first openings and at least one of the second openings do not overlap in a normal direction of the electronic unit.
In the similar field of endeavor of semiconductor devices, Figs. 6 and 10 of Chen disclose wherein at least one of the first openings (Fig. 6, openings 114, ¶ [0028]) and at least one of the second openings (Fig. 9, openings 124, ¶ [0035]) do not overlap in a normal direction of the electronic unit (Fig. 6, substrate 102, ¶ [0014]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the openings as disclosed by Chen, to increase device yield (see Chen, ¶ [0136]).
Regarding claim 7, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, and Fig. 2d of Chew further discloses wherein the second side surface (250S) of the second insulating layer (250) is aligned with the first side surface (213) of the electronic unit (210).
Regarding claim 10, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, and Fig. 2d of Chew further discloses wherein the connecting element (270) further comprises:
a second conductive layer (Fig. 2d, RDL lines 276, ¶ [0059]) electrically connected to the first conductive layer (274).
Regarding claim 12, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 10 as applied above, and Fig. 2d of Chew further discloses wherein a portion of the second conductive layer (276) is in contact with a surface of the third insulating layer (290).
Regarding claim 13, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, and Fig. 2d of Chew further discloses wherein the second thickness (see Annotation 1, Fig. 2d of Chew, “T2”) of the second insulating layer (250) is less than a third thickness (see Annotation 1, Fig. 2d of Chew, “T3”) of the third insulating layer (290).
Regarding claim 14, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, and Fig. 2d of Chew further discloses comprising:
a fourth insulating layer (Fig. 2d, RDL encapsulation layer 246, ¶ [0061]) disposed on the connecting element (270) and being in contact with the second insulating layer (250) and the third insulating layer (290).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chew (US 20210343549 A1), Suk (US 20190051607 A1), Chen (US 20220122898 A1), and Hsieh (US 20150041985 A1) in further view of Kwon et al. (US 20140124881 A1) herein after “Kwon”.
Regarding claim 8, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, but the combination fails to disclose wherein the first insulating layer has a third side surface, the third side surface and the second surface have an included angle, and the included angle is greater than or equal to 45 degrees and less than 90 degrees.
In the similar field of endeavor of semiconductor device fabrication, Fig. 2A of Kwon discloses wherein the first insulating layer (Fig. 2A, insulating mold layer 30, ¶ [0050]) has a third side surface (Fig. 2A, sidewalls of the openings 31, ¶ [0057]), the third side surface (sidewalls of the openings 31) and the second surface (Fig. 2A, top surface of the semiconductor substrate 10, ¶ [0056]) have an included angle, and the included angle is greater than or equal to 45 degrees and less than 90 degrees (Fig. 2A, “the sidewall of the opening 31 and the top surface of the semiconductor substrate 10 may form an acute angle .theta. of about 45-90 degrees”, ¶ [0056]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the side surfaces as disclosed by Kwon, to increase ease of subsequent processing (see Kwon, ¶ [0063]).
Regarding claim 9, Chew, Suk, Chen, Hsieh, and Kwon together disclose the package device of claim 8 as applied above, and Fig. 2d of Chew further discloses wherein the second insulating layer (250) is in contact with the third side surface (244S) of the first insulating layer (244).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chew (US 20210343549 A1), Suk (US 20190051607 A1), Chen (US 20220122898 A1), and Hsieh (US 20150041985 A1) in further view of Fan et al. (US 20190114957 A1) herein after “Fan”.
Regarding claim 11, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, but the combination fails to disclose wherein a thickness of the second conductive layer is greater than a thickness of the first conductive layer.
In the similar field of endeavor of semiconductor devices, Fig. 3 of Fan discloses wherein a thickness (Fig. 3, second thickness H2, ¶ [0021]) of the second conductive layer (Fig. 3, second connecting pad 222, second conductive layer 23, ¶ [0021]) is greater than a thickness (Fig. 3, first thickness H1, ¶ [0021]) of the first conductive layer (Fig. 3, first connecting pad 221, ¶ [0021]) (Fig. 3, “the first thickness H1 is greater than or equal to 0.01 μm and is less than or equal to 5 μm, the second thickness H2 is greater than or equal to 6 μm and is less than or equal to 50 μm”, ¶ [0021]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the conductive layers as disclosed by Fan, to simplify the production process (see Fan, ¶ [0006]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chew (US 20210343549 A1), Suk (US 20190051607 A1), Chen (US 20220122898 A1), and Hsieh (US 20150041985 A1) in further view of Lee et al. (JP 2015084394 A) herein after “Lee”.
Regarding claim 16, Chew, Suk, Chen, and Hsieh together disclose the package device of claim 1 as applied above, but the combination fails to disclose wherein the first insulating layer and the second insulating layer are reverse warping layers.
In the similar field of endeavor of printed circuit boards, Fig. 1 of Lee discloses wherein the first insulating layer (110) and the second insulating layer (220) are reverse warping layers (Fig. 1, “the warping compensation means arranged at the upper portion warps downward and the warping compensation means arranged at the lower portion warps upward, thereby reducing the warping phenomenon of the printed circuit board due to the counteracting effect”, ¶ [0016]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Chew with the insulating layers as disclosed by Lee, to prevent damage (see Lee, ¶ [0089]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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