DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 4, 2026 has been entered.
Response to Arguments
Regarding the rejection of the claims under 35 USC 102 and 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration have prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-7, 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20170256551A1 (“Lee”), in view of US20220059454A1 (“Suwa”), further in view of US20210125928A1 (“Kim”), further in view of US20190067131A1 (“Liaw”).
RE: Claim 1, Lee discloses A microelectronic device (100 in FIG. 1F), comprising:
a stack (stack of 104, 126, [0046], [0058]) comprising a vertically alternating sequence of insulative structures (104) and conductive structures (126) arranged in tiers (108);
a staircased stadium (118, [0033]) within the stack and comprising steps (116, [0035]) at different tier elevations of a group of the tiers (FIG. 1F shows the stadium 118 including steps 116 at different tier elevations at 108a through 108k of a group of the tiers 108), the steps comprising treads, each of the treads provided by:
an upper surface area of one of the conductive structures within the group of the tiers (steps 116 are at least partially defined by the conductive structure 126, [0053]; FIG. 1F shows each tread of 116 is provided by an upper surface area of one of 126 within the group of the tiers 108); and
a first conductive contact structure (134, [0053]) terminating at the tread of the one of the steps within the upper surface area of the one of the conductive structures (Conductive contact structures 134 formed on or over the same staircase structure 114 may be fanned to be generally centrally positioned (e.g., in at least the X-direction) over the steps 116), [0055]; As 134 are over the steps defined by 126, and FIG. 1F shows 134 in direct contact with the upper surface of 126, 134 terminates at the tread of the one of the steps 116 within the upper surface area of 126).
Lee does not explicitly disclose:
each of the treads is further provided by an upper surface area of a metal oxide region extending through the one of the conductive structures;
a pair of conductive contact structures extending to one of the steps and comprising:
the first conductive contact structure (134) terminating at the tread of the one of the steps within the upper surface area of the one of the conductive structures; and
a second conductive contact structure extending through the tread of the one of the steps within the upper surface area of the metal oxide region,
the second conductive contact structure extending to terminate on or in a second one of the conductive structures within the group of the tiers.
In the same field of endeavor, Suwa discloses (see FIG. 26A):
a pair of conductive contact structures (86, [0146]; 86 are contact via structures, [0146]) extending to one of the steps (steps defined by multiple conductive layers 46A, 46B, 46C, 46D, and insulating layers 32 under 46A, [0147], [0140]) and comprising:
a first conductive contact structure (86A) terminating at the tread (46A) of the one of the steps within the upper surface area of the one of the conductive structures;
a second conductive contact structure (86C, [0161]) extending through the tread of the one of the steps (86C extends through the tread 46A) within the upper surface area thereof,
the second conductive contact structure extending to terminate on or in a second one of the conductive structures within the group of the tiers (FIG. 26 shows 86C extending to terminate on or in a second one of the conductive structures 46C within the group of the tiers).
Suwa further discloses a via liner 82 surrounding each contact via structure 86, the via liner 82 is dielectric, [0147].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each step 116 to include multiple conductive structures 126 and multiple insulating structures 104 under the topmost 126, and to provide each step with a second conductive contact structure extending through its tread, the second conductive contact structure extending to terminate on or in a second one of the conductive structures 126, with a via liner surrounding each second conductive contact structure as taught by Suwa in order to provide increased circuit routing and improve memory circuit density.
In the same field of endeavor, Kim discloses The cell through-via structure TVC, the first and second extension through-via structures TVE1 and TVE2, and the common source via TCS may include a via liner layer 31 and a central via plug 32, respectively. The via plug 32 may include a metal, a metal compound, and/or a metal alloy, [0068].
Kim further discloses The via liner layer 31 may have protruding portions P filling the insides of the recesses R1, see FIGs. 2C, 12A, 13A, [0066].
FIG. 2C shows the protruding portions P are aligned with conductor word lines 30, [0037].
Kim further discloses the via liner layer 31 may include a silicon oxide based insulator, [0041].
FIG. 2A shows treads (treads defined by 30, oxide region of 31) further provided by an upper surface area of an oxide region (oxide region of 31) extending through the one of the conductive structures (30).
FIG. 2A shows a conductive contact structure (TVE1, [0041], [0043], [0068]) extending through the tread (tread defined by a word line 30, and an oxide region of 31) of the one of the steps within the upper surface area of the oxide region (oxide region of 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include protrusions in each via liner of the second conductive contact structures providing treads as taught by Kim with the upper surfaces of the via liners providing treads so as to better insulate the second conductive contact structures from conductive structures 126.
In a similar field of endeavor, Liaw discloses In some implementations, at least one of vias 70A-70E includes a via liner layer that includes a high-k dielectric material, which generally refers to a material having a dielectric constant (k) greater than about 4.5 (k>4.5). For example, in FIG. 5A and FIG. 5B, the drain node vias (here, vias 70A, 70B) and the source node vias (here, vias 70C, 70D) include a via liner layer 90 that includes a high-k dielectric material, and a via bulk layer 92 that includes a conductive material. In some implementations, the high-k dielectric material includes a nitride-based dielectric material, a metal oxide-based dielectric material, a hafnium-based dielectric material, other suitable high-k dielectric material, or combinations thereof. For example, the high-k dielectric material includes HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, HfO.sub.2—Al.sub.2O.sub.3, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, other suitable high-k dielectric materials, or combinations thereof. Via liner layer 90 further enhances performance of FinFET device 10, for example, by further improving via-to-via isolation margins, [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a metal oxide such as titanium oxide as the material of each via liner of the second conductive contact structures as taught by Liaw in order to improve via-to-via isolation.
As a result:
each of the treads is further provided by an upper surface area of a metal oxide region extending through the one of the conductive structures (each of the treads would be provided at least partially by a metal oxide region of a via liner of a respective second conductive contact structure extending through an uppermost 126 of a step);
a pair of conductive contact structures (134 in combination with a second conductive contact structure) extending to one of the steps and comprising:
the first conductive contact structure (134) terminating at the tread of the one of the steps within the upper surface area of the one of the conductive structures;
a second conductive contact structure extending through the tread of the one of the steps within the upper surface area of the metal oxide region (As modified, the second conductive contact structure would extend through a step’s uppermost 126 functioning as a tread within the upper surface area of the metal oxide region also providing the tread),
the second conductive contact structure extending to terminate on or in a second one of the conductive structures within the group of the tiers (As modified, the second conductive contact structure would extend to terminate on or in a second one of the conductive structures 126 below the step’s uppermost 126).
RE: Claim 2, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 1, wherein the second conductive contact structure further extends through one of the insulative structures (In Suwa FIG. 26A, the second conductive contact structure 86C further extends through an insulative structure 32 directly below conductive layer 46A; Accordingly, as modified, the second conductive contact structure would further extend through an insulative structure 104 directly below the uppermost 126 of the step).
RE: Claim 3, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 2, wherein the one of the insulative structures is directly below the one of the conductive structures (As modified, the second conductive contact structure would further extend through an insulative structure 104 directly below the uppermost conductive structure 126 of the step).
RE: Claim 5, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 1, wherein the second one of the conductive structures does not include an upper surface area providing any of the treads of the steps of the staircased stadium (In Suwa FIG. 26A, the second one of the conductive structures 46C does not include an upper surface area providing any of the treads of the steps of the staircased stadium; Accordingly, as modified, the second one of the conductive structures 126 below the uppermost 126 of the step would not include an upper surface area providing any of the treads of the steps of the staircased stadium).
RE: Claim 6, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 1, further comprising an additional staircased stadium within the stack and comprising additional steps at additional different tier elevations of an additional group of the tiers (In Lee FIG. 2 shows a lefthand stadium and an additional righthand staircased stadium 218 within the stack and comprising additional steps 216 at additional different tier elevations of an additional group of the tiers 208), the additional steps comprising additional treads, each of the additional treads provided wholly by an upper surface area of one of the conductive structures within the additional group of the tiers (Kim FIG. 2A shows MC1 connected to additional steps provided wholly by an upper surface area of one of the conductive structures 30; Lee discloses the insulating structures of each of the tiers 208 are not depicted FIG. 2. However, aside from variances in shape and size, the insulating structures of the conductive stack structure 224 may be substantially similar to, and may be formed and arranged in substantially the same manner as, the insulating structures 104 previously described in relation to the conductive stack structure 124, [0064]; Accordingly, since in FIG. 1E, each of the treads is provided wholly by an upper surface area of one of the conductive structures 126, it would have been obvious to provide an additional lower staircased stadium comprising additional steps, each of the additional treads provided wholly by an upper surface area of one of the conductive structures 126 as taught by Lee in order to enable increased memory circuitry and increased data storage).
RE: Claim 7, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 6, wherein the additional staircased stadium is elevationally lower than the staircased stadium (In FIG. 2 Lee, the righthand additional staircased stadium is elevationally lower than the lefthand staircased stadium; Accordingly, as modified, the additional staircased stadium would be elevationally lower than the staircased stadium).
RE: Claim 9, Lee in view of Suwa, Kim, Liaw discloses discloses The microelectronic device of claim 1, further comprising, within the staircased stadium: at least one dielectric liner (As modified, the via liner of each second conductive contact structure is a dielectric via liner; From Suwa FIG. 26A, each contact via structure 86 is insulated by a dielectric liner 82, [0145]; It would have been obvious to insulate each first conductive contact structure 134 by a dielectric liner as taught by Suwa in order to better insulate each first conductive contact structure 134); and at least one insulative fill material on the at least one dielectric liner (From Suwa FIG. 26A, at least one insulative fill material 65 is on each dielectric liner, [0147], and each conductive contact structure 86 extends through 65; Accordingly, it would have been obvious to provide an insulative fill material as taught by Suwa in order to better insulate each first and second conductive contact structure from each other).
RE: Claim 10, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 9, wherein the first conductive contact structure and the second conductive contact structure each extend through the at least one insulative fill material and through the at least one dielectric liner (As modified, the first conductive contact structure 134 and the second conductive contact structure each extend through the at least one insulative fill material and through the at least one dielectric liner).
RE: Claim 11, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 1, further comprising at least one insulative liner horizontally around conductive material of the second conductive contact structure (As modified, the via liner of each second conductive contact structure is dielectric metal oxide and would be horizontally around conductive material of the second conductive contact structure).
Further, Kim discloses (see FIG. 2A):
at least one insulative liner (41, 42, 43; layers 41-43 may include an insulating material such as silicon oxide, [0075]) horizontally around conductive material (52) of the second conductive contact structure (TVC, [0048]).
In FIG. 2A, the lowest end of insulative liner 41, 42, 43 is above the oxide regions 31 labeled in FIG. 2B-2C providing treads.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an additional insulative liner above oxide regions as taught by Kim in order to improve insulation for each second conductive contact structure.
RE: Claim 12, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 11, wherein a lowest end of the at least one insulative liner is above the metal oxide region (As modified, the lowest end of the additional insulative liner is above the metal oxide region).
RE: Claim 13, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 1, wherein:
the conductive structures comprise at least one metal (Lee discloses 134 comprises the metal titanium, [0056]); and
the metal oxide region comprises the at least one metal and further comprises oxygen (As modified the metal oxide region comprises titanium oxide).
RE: Claim 14, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 1, wherein the steps further comprise risers, at least some of the risers having a height of at least two of the tiers (As modified, each step has a riser having a height of multiple conductive structures 126 and multiple insulating structures 104 and therefore at least two of the tiers).
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Suwa, further in view of Kim, further in view of Liaw as applied to claim 1, further in view of US 20120329277 A1 to Zhu (hereinafter “Zhu”).
RE: Claim 8, Lee in view of Suwa, Kim, Liaw does not explicitly disclose The microelectronic device of claim 1, wherein a horizontal dimension of the metal oxide region is at least about two-hundred nanometers.
However, in the same field of endeavor, Zhu discloses The dielectric liners 10 include a dielectric material that electrically isolates a structure located inside of the dielectric liners 10 from a structure located outside of the dielectric liners 10. The thickness of the dielectric liners 10 may be from 10 nm and 500 nm, and typically from 20 nm to 200 nm, although lesser and greater thicknesses are also contemplated herein, [0027].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to increase the thickness of the via liner to 200 nm or more as taught by Zhu to improve the electrical isolation properties of the via liner and ensure the second conductive contact structures are well isolated.
Claim(s) 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Suwa, further in view of Kim, further in view of Liaw.
RE: Claim 15, Lee discloses A microelectronic device (100 in FIG. 1F), comprising:
a stack structure (stack of 104, 126, [0046], [0058]) comprising a vertically alternating sequence of insulative structures (104) and conductive structures (126) arranged in tiers (108);
a series of stadiums (Lee discloses 112 includes two or more stadium structures 118 extending in series with one another, [0034]) within the stack structure, each of at least some of the stadiums comprising at least one staircase (114a, 114b) defined in a group of the tiers (stadium structures 118 include staircase structures 114a, 114b , 114c, 114d, [0034]; Each of the staircase structures 114 included in the modified stack structure 112 may independently include a desired number of steps 116. The number of steps 116 included in each of the staircase structures 114 may be substantially the same, [0035]), the group of the tiers comprising:
treaded tiers (treaded tiers defined by 126), the conductive structures of which provide treads of steps of the at least one staircase (steps 116 are at least partially defined by the conductive structure 126, [0053]; FIG. 1F shows each tread of 116 is provided by 126); and
at least one conductive contact structure (134) extending to one of the conductive structures providing one of the treads (FIG. 1F shows 134 extending to one of the conductive structures 126 providing one of the treads).
Lee does not explicitly disclose:
the group of the tiers comprising:
covered tiers, the conductive structures of which are each directly vertically below one of the treaded tiers;
metal oxide regions extending through the conductive structures of the treaded tiers;
at least one other conductive contact structure extending through one of the metal oxide regions,
the one of the metal oxide regions being in the one of the conductive structures providing the one of the treads,
the at least one other conductive contact structure further extending to terminate on or in one of the conductive structures of the covered tiers.
Lee discloses: steps 116 included in each of the staircase structures 114 may be substantially the same as (e.g., equal to) the number of tiers 108, [0035]; The first stadium structure 118 a and the second stadium structure 118 b may be substantially similar to one another, [0033].
FIG. 1F shows 114a, 114b including layers 126 providing treads.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify 114c, 114d to be substantially similar to 114a, 114b so that layers 126 provide treads in 114c, 114d in order to simplify manufacturing.
In the same field of endeavor, Suwa discloses (see FIG. 26A):
a group of the tiers (tiers defined by 46A, 46B, 46C, 46D, and insulating layers 32 below 46A) comprising:
covered tiers (46C, 46B, 46D), the conductive structures of which are each directly vertically below one of the treaded tiers (46C, 46B, 46D are each directly vertically below one of the treaded tiers defined by 46A);
at least one conductive contact structure (86A, [0159]) extending to one of the conductive structures providing one of the treads (86A is shown extending to one of the conductive structures 46A providing one of the treads);
at least one other conductive contact structure (86C, [0161]) extending through the conductive structure (46A),
the at least one other conductive contact structure further extending to terminate on or in one of the conductive structures of the covered tiers (86C is shown extending to terminate on or in one of the conductive structures 46C of the covered tiers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each step 116 in each 114 to include multiple conductive structures 126 and multiple insulating structures 104 under the topmost 126, thereby providing covered tiers, and to provide each step with one other conductive contact structure extending through its tread, the one other conductive contact structure extending to terminate on or in one of the conductive structures 126 othe covered tiers, with a via liner surrounding each of the one other conductive contact structures as taught by Suwa in order to provide increased circuit routing and improve memory circuit density.
In the same field of endeavor, Kim discloses in FIGs. 2A-2C:
oxide regions (oxide regions of 31, [0041]) extending through the conductive structures (30, [0037]) of the treaded tiers;
at least one other conductive contact structure (TVE1, [0041], [0043], [0068]) extending through one of the oxide regions,
the one of the oxide regions being in the one of the conductive structures providing the one of the treads (FIG. 2A shows one of the oxide regions of 31 in one of 30 providing one of the treads).
Kim further discloses The cell through-via structure TVC, the first and second extension through-via structures TVE1 and TVE2, and the common source via TCS may include a via liner layer 31 and a central via plug 32, respectively. The via plug 32 may include a metal, a metal compound, and/or a metal alloy, [0068].
Kim further discloses The via liner layer 31 may have protruding portions P filling the insides of the recesses R1, see FIGs. 2C, 12A, 13A, [0066].
FIG. 2C shows the protruding portions P are aligned with conductor word lines 30, [0037].
Kim further discloses the via liner layer 31 may include a silicon oxide based insulator, [0041].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include protrusions in each via liner of the other conductive contact structures in each 114 as taught by Kim with the upper surfaces of the via liners providing treads so as to better insulate the other conductive contact structures from conductive structures 126.
In a similar field of endeavor, Liaw discloses In some implementations, at least one of vias 70A-70E includes a via liner layer that includes a high-k dielectric material, which generally refers to a material having a dielectric constant (k) greater than about 4.5 (k>4.5). For example, in FIG. 5A and FIG. 5B, the drain node vias (here, vias 70A, 70B) and the source node vias (here, vias 70C, 70D) include a via liner layer 90 that includes a high-k dielectric material, and a via bulk layer 92 that includes a conductive material. In some implementations, the high-k dielectric material includes a nitride-based dielectric material, a metal oxide-based dielectric material, a hafnium-based dielectric material, other suitable high-k dielectric material, or combinations thereof. For example, the high-k dielectric material includes HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, HfO.sub.2—Al.sub.2O.sub.3, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, other suitable high-k dielectric materials, or combinations thereof. Via liner layer 90 further enhances performance of FinFET device 10, for example, by further improving via-to-via isolation margins, [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a metal oxide such as titanium oxide or HfSiON as the material of each via liner of the other conductive contact structures as taught by Liaw in order to improve via-to-via isolation.
RE: Claim 16, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 15, wherein at least one other of the stadiums comprises at least one other staircase (From Lee 114c, 114d in FIG. 1F) defined in an other group of the tiers, the other group of the tiers consisting of other treaded tiers (Lee discloses The number of steps 116 included in each of the staircase structures 114 may be substantially the same as (e.g., equal to) the number of tiers 108 in the modified stack structure 112, [0035]),
the conductive structures (126) of which each provide other treads of other steps of the at least one other staircase (As modified, 126 provide treads in 114c, 114d), and
other metal oxide regions extend through the conductive structures of the other treaded tiers (As modified, each step in each 114 is modified to include a metal oxide region extending through its uppermost conductive structure 126).
RE: Claim 17, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 15, wherein the at least one other conductive contact structure has a height that is greater than a height of the at least one conductive contact structure (Suwa FIG. 26A shows at least one other conductive contact structure 86C has a height that is greater than a height of the at least one conductive contact structure 86A; Accordingly, as modified, the at least one other conductive contact structure has a height that is greater than a height of the at least one conductive contact structure).
RE: Claim 18, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 15, wherein: the conductive structures comprise at least one of tungsten, titanium, cobalt, and ruthenium; and the metal oxide regions comprise at least one of tungsten oxide, titanium oxide, cobalt oxide, and non-conductive ruthenium oxide (Lee discloses 134 comprises the metal titanium, [0056]; As modified, the metal oxide regions comprise titanium oxide).
RE: Claim 19, Lee in view of Suwa, Kim, Liaw discloses The microelectronic device of claim 15, wherein: the conductive structures comprise a metal nitride material (Lee discloses 134 comprises a conductive metal nitride, [0056]); and the metal oxide regions comprise a metal oxynitride material (As modified, the metal oxide regions comprise HfSiON; the reference US20060081901A1 identifies HfSiON as a metal oxynitride, [0076]; Accordingly, HfSiON is a metal oxynitride).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Suwa, further in view of Kim, further in view of Liaw, further in view of US20210151455A1 (“Xu”).
RE: Claim 25, Lee discloses An electronic system (600 including 602, 604, FIG. 6; 602 includes the semiconductor device of 100 in FIG. 1F, [0123]; 604 includes a device substantially similar to 100 in FIG. 1F, [0123]), comprising:
a microelectronic device (100 in FIG. 1F) comprising:
a stack structure (stack of 104, 126, [0046], [0058]) comprising tiers (108) each including a conductive structure (126) and an insulative structure (104) vertically adjacent the conductive structure;
a series of staircased stadiums (Lee discloses 112 includes two or more stadium structures 118 extending in series with one another, [0034]) in the stack structure and comprising steps (116) defined by ends of some of the conductive structures of the tiers (FIG. 1F shows 112 includes steps 116 defined by ends of some of the conductive structures 126 of the tiers, [0053]), the steps of at least one of the staircased stadiums having:
a tread defined by one of the conductive structures (FIG. 1F shows the steps 116 having a tread defined by 126); and
conductive contact structures (134) extending toward the steps of the at least one of the staircased stadiums,
at least some of the conductive contact structures terminating on treads of the steps of the at least one of the staircased stadiums (Conductive contact structures 134 formed on or over the same staircase structure 114 may be fanned to be generally centrally positioned (e.g., in at least the X-direction) over the steps 116), [0055]; As 134 are over the steps defined by 126, and FIG. 1F shows 134 in direct contact with the upper surface of 126, 134 terminates on the treads of the steps 116),
at least one processor (604 in FIG. 6, [0123]); and
at least one peripheral device (606, 608, [0123]) in operable communication with the at least one processor (The one or more input devices 606 and output devices 608 may communicate electrically with at least one of the memory device 602 and the electronic signal processor device 604, [0123]).
Lee does not explicitly disclose:
the steps of at least one of the staircased stadiums having:
a riser height of at least two of the tiers; and
a tread defined in part by one of the conductive structures and in another part by a metal oxide region extending through the one of the conductive structures; and
at least some others of the conductive contact structures extending through the metal oxide regions of the treads of the steps of the at least one of the staircased stadiums to terminate on or in some other of the conductive structures of the tiers;
the at least one processor is in operable communication with the microelectronic device.
In the same field of endeavor, Suwa discloses (see FIG. 26A):
the steps of at least one of the staircased stadiums having:
a riser height of at least two of the tiers (each step has a riser height of at least two tiers of 46 including multiple 46A, 46B, 46C, 46D, and multiple insulating layers 32 below 46A); and
a tread defined by one of the conductive structures (each step has a tread defined by 46A);
at least some of the conductive contact structures (86A) terminating on treads of the steps of the at least one of the staircased stadiums (FIG. 26A shows some 86A terminating on treads 46A);
at least some others of the conductive contact structures (86C) extending through the regions of the treads of the steps of the at least one of the staircased stadiums to terminate on or in some other of the conductive structures of the tiers (FIG. 26A shows some 86C extending through the treads 46A to terminate on or in 46C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each step 116 in each 114 to include multiple conductive structures 126 and multiple insulating structures 104 under the topmost 126, thereby providing a riser height of at least two tiers, and to provide each step with one other conductive contact structure extending through its tread, the one other conductive contact structure extending to terminate on or in one of the conductive structures 126 of the covered tiers, with a via liner surrounding each of the one other conductive contact structures as taught by Suwa in order to provide increased circuit routing and improve memory circuit density.
In the same field of endeavor, Kim discloses in FIGs. 2A-2C:
steps of at least one of the staircased stadiums having:
a tread defined in part by one of the conductive structures (30) and in another part by a metal oxide region (oxide region of 31, [0041]) extending through the one of the conductive structures (FIG. 2A shows treads defined in part by 30 and in another part by an oxide region of 31 extending through 30);
at least some others of the conductive contact structures (TVC, TVE1, [0041], [0043], [0068]) extending through the metal oxide regions of the treads of the steps.
Kim further discloses The cell through-via structure TVC, the first and second extension through-via structures TVE1 and TVE2, and the common source via TCS may include a via liner layer 31 and a central via plug 32, respectively. The via plug 32 may include a metal, a metal compound, and/or a metal alloy, [0068].
Kim further discloses The via liner layer 31 may have protruding portions P filling the insides of the recesses R1, see FIGs. 2C, 12A, 13A, [0066].
FIG. 2C shows the protruding portions P are aligned with conductor word lines 30, [0037].
Kim further discloses the via liner layer 31 may include a silicon oxide based insulator, [0041].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include protrusions in each via liner of the other conductive contact structures in each 114 as taught by Kim with the upper surfaces of the via liners providing treads so as to better insulate the other conductive contact structures from conductive structures 126.
In a similar field of endeavor, Liaw discloses In some implementations, at least one of vias 70A-70E includes a via liner layer that includes a high-k dielectric material, which generally refers to a material having a dielectric constant (k) greater than about 4.5 (k>4.5). For example, in FIG. 5A and FIG. 5B, the drain node vias (here, vias 70A, 70B) and the source node vias (here, vias 70C, 70D) include a via liner layer 90 that includes a high-k dielectric material, and a via bulk layer 92 that includes a conductive material. In some implementations, the high-k dielectric material includes a nitride-based dielectric material, a metal oxide-based dielectric material, a hafnium-based dielectric material, other suitable high-k dielectric material, or combinations thereof. For example, the high-k dielectric material includes HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, HfO.sub.2—Al.sub.2O.sub.3, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, other suitable high-k dielectric materials, or combinations thereof. Via liner layer 90 further enhances performance of FinFET device 10, for example, by further improving via-to-via isolation margins, [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a metal oxide such as titanium oxide as the material of each via liner of the other conductive contact structures as taught by Liaw in order to improve via-to-via isolation.
Further in the same field of endeavor, Xu teaches The memory is operably coupled to the processor 502 to store and facilitate execution of various programs. For example, the processor 502 may be coupled to system memory 516, [0081]. The system memory 516 may include volatile memory, non-volatile memory, or a combination thereof. The system memory 516 is typically large so that it can store dynamically loaded applications and data. In some embodiments, the system memory 516 may include semiconductor devices, such as the microelectronic devices (e.g., the microelectronic devices 100, 200, 300), [0081]. As the memory is operably coupled to the processor to store and facilitate execution of various programs, the memory would be in operable communication with the processor to store and facilitate execution of various programs.
Xu teaches The microelectronic device structure 100 may include a stair step region 150 including the stair step structure 102 and a memory array region 160. The memory array region 160 may include vertical strings of memory cells, such as NAND memory cells, [0026].
Lee teaches FIGS. 1A through 1G are simplified perspective (FIGS. 1A through 1F) and top-down (FIG. 1G) views illustrating embodiments of a method of forming a semiconductor device structure including a staircase structure, such as a memory array structure (e.g., a memory array block) for a 3D non-volatile memory device (e.g., a 3D NAND Flash memory device), [0023]. Accordingly, the structure 100 is considered a memory structure.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the processor 604 to be operably coupled with the microelectronic device 100 as taught by Xu in order to store and facilitate execution of various programs.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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