DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-16 are amended and pending.
Claims 17-20 are cancelled.
Claims 21-24 are withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the limitation of “wherein a distance between memory cells along a direction parallel to the first insulator line and the second insulator line is smaller than a distance between memory cells along a direction perpendicular to the first insulator line and the second insulator line” in claim 12 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Servalli et al (U.S. 2021/0210491) and further in view of Zhao et al (U.S. 2023/0133520).
Regarding claim 1. Servalli et al discloses an integrated assembly (FIG. 8, 8A, 8B, item 36), comprising:
a pillar (FIG. 8A, item 12) that includes an upper source/drain (FIG. 8A, item 16), a lower source/drain (FIG. 8A, item 18), a channel (FIG. 8A, item 20) between the upper source/drain (FIG. 8A, item 16) and the lower source/drain (FIG. 8A, item 18), a left-facing vertical surface (FIG. 8A, item -Y of surface of item 16) facing a first direction (FIG. 8A, item -Y) along a first axis (FIG. 8A, item Y), and a right-facing vertical surface (FIG. 8A, item +Y of surface of item 16) facing a second direction (FIG. 8A, item +Y) that is opposite the first direction (FIG. 8A, item -Y) along the first axis (FIG. 8A, item Y), wherein the pillar (FIG. 8A, item 12) extends vertically along a second axis (FIG. 8A, item Z) that is perpendicular to the first axis (FIG. 8A, item Y);
a first conductor line (FIG. 8A, item 58 left side) that extends along the first axis (FIG. 8A, item Y) from the upper source/drain (FIG. 8A, item 16) to a first insulator line (FIG. 8A, item 22 on left) that extends along a third axis (FIG. 8B, item X) that is perpendicular to a plane formed by the first axis (FIG. 8A, item Y) and the second axis (FIG. 8A, item Z), wherein the left-facing vertical surface (FIG. 8A, item -Y of surface of item 16) faces a portion of the first insulator line (FIG. 8A, item 22 on left) that contacts the first conductor line (FIG. 8A, item 58 left side);
a second conductor line (FIG. 8A, item 58 right side) that extends along the first axis (FIG. 8A, item Y) from the upper source/drain (FIG. 8A, item 16) to a second insulator line (FIG. 8A, item 22 on right) that is parallel to the first insulator line (FIG. 8A, item 22 on right side), wherein the right-facing vertical surface (FIG. 8A, item +Y of surface of item 16) faces a portion of the second insulator line (FIG. 8A, item 22 on right) that contacts the second conductor line (FIG. 8A, item 58 right side);
a first gate line (FIG. 8A, item 26b) that extends in a same direction as the first insulator line (FIG. 8A, item 22 on left) and the second insulator line (FIG. 8A, item 22 on right), wherein the left-facing vertical surface (FIG. 8A, item -Y of surface of item 16) faces a portion of the first gate line (FIG. 8A, item 26b) that is proximate to the channel (FIG. 8A, item 20);
a second gate line (FIG. 8A, item 26c) that extends in a same direction as the first insulator line (FIG. 8A, item 22 on left) and the second insulator line (FIG. 8A, item 22 on right), wherein the right-facing vertical surface (FIG. 8A, item +Y of surface of item 16) faces a portion of the second gate line (FIG. 8A, item 26c) that is proximate to the channel (FIG. 8A, item 20); and
an electrode pillar (FIG. 8A, item 56; [0029], i.e. bottom electrodes are configured as angle plates) that is in contact with a conductive contact region (FIG. 8A, item 58) formed by the first conductor line (FIG. 8A, item 58 left side), the second conductor line (FIG. 8A, item 58 right side), and the upper source/drain (FIG. 8, item 16).
Servalli et al fails to explicitly a cylindrical electrode pillar.
However Zhao et al teaches a cylindrical electrode pillar ([0095], i.e. a cylinder capacitor).
Zhao et al further discloses capacitors ([0095]) may include any suitable structure and configuration, such as a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.
Since Servalli et al and Zhao et al disclose bottom electrodes as plates for capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the integrated assembly as disclosed to modify Servalli et al with the teachings of a cylindrical electrode pillar as disclosed by Zhao et al as one of ordinary skill would have found it obvious to substitute the element with a predictable result as a capacitor. The use of a cylinder capacitor in Zhao et al provides an array of memory cells can be arranged in a staggered layout in the plan view to further increase the cell density and reduce the unit cell size (Zhao et al, [0048]). See MPEP 2144.06 II Art Recognized Equivalent for the same purpose.
Regarding claim 2. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 1 above.
Servalli et al further discloses wherein the pillar (FIG. 8, item 12) is a rectangular prism (FIG. 8, shows item 16 of item 12 is rectangular prism).
Regarding claim 3. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 1 above.
Servalli et al further discloses further comprising an array of pillars ([0089]), including the pillar (FIG. 8A, item 12), that are substantially identical ([0102]), wherein a pitch of the array ([0089]) along the first axis (FIG. 8A, item Y) is greater ([0077]) than a pitch of the array ([0089]) along the third axis (FIG. 8B, item X).
Regarding claim 4. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 1 above.
Servalli et al further discloses further comprising:
an array of pillars ([0089]), including the pillar (FIG. 8A, item 12), that are substantially identical ([0102]), and an array of electrode pillars ([0089]), including the electrode pillar (FIG. 8A, item 56), that are substantially identical ([0102]),
wherein each electrode pillar (FIG. 8A, item 56), included in a first set of electrode pillars (FIG. 8A, item 56) accessible via a first digit line (annotated FIG. 8, item second digital line; FIG. 8A, item 24a), is in contact ([0036]) with a respective first conductor line (FIG. 8A, item 58).
Zhao et al discloses the cylindrical electrode pillar ([0095]).
Regarding claim 5. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 4 above.
Servalli et al further discloses wherein each electrode pillar (FIG. 8A, item 56), included in a second set of electrode pillars (FIG. 8A, item 56) accessible via a second digit line (annotated FIG. 8, item second digital line; FIG. 8A, item 24a) and adjacent to the first set of electrode pillars (FIG. 8A, item 56), is in contact ([0036]) with a respective second conductor line (FIG. 8A, item 58).
PNG
media_image1.png
769
613
media_image1.png
Greyscale
Regarding claim 6. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 1 above.
Servalli et al further discloses further comprising: an array of pillars ([0089]), including the pillar (FIG. 8A, item 12), that are substantially identical ([0102]), and an array of electrode pillars ([0089]), including the electrode pillar (FIG. 8A, item 56), that are substantially identical ([0102]),
wherein alternating ([0089]) electrode pillars (FIG. 8A, item 56), included in a set of electrode pillars (FIG. 8A, item 56) that extends along the third axis (FIG. 8B, item X), are in contact with alternating ones ([0080]) of the first conductor line (FIG. 8A, item 58 left side) and the second conductor line (FIG. 8A, item 58 right side).
Zhao et al discloses the cylindrical electrode pillar ([0095]).
Regarding claim 7. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 1 above.
Servalli et al further discloses wherein the pillar (FIG. 8A, item 12), the portion of the first gate line (FIG. 8A, item 26b) that is proximate to the channel (FIG. 8A, item 20), and the portion of the second gate line (FIG. 8A, item 26b) that is proximate to the channel (FIG. 8A, item 20) form a transistor ([0044]),
wherein the electrode pillar (FIG. 8A, item 56) is a bottom electrode ([0080]) of a capacitor ([0100]) that includes the bottom electrode ([0100]), an insulator ([0100]), and a top electrode ([0100]), and
further comprising a digit line (FIG. 8A, item 24a) that is beneath the pillar (FIG. 8A, item 12), is electrically coupled ([0044]) with the lower source/drain (FIG. 8A, item 18), and is parallel (FIG. 8A) to the first conductor line (FIG. 8A, item 58 left side) and the second conductor line (FIG. 8A, item 58 right side), wherein the transistor ([0044]) selectively couples ([0044]) the capacitor ([0100]) and the digit line (FIG. 8A, item 24a).
Zhao et al discloses the cylindrical electrode pillar ([0095]).
Regarding claim 8. Servalli et al and Zhao et al discloses all the limitations of the integrated assembly of claim 1 above.
Servalli et al further discloses wherein a top surface (FIG. 8, item 58) of the conductive contact region (FIG. 8, item 58) is rectangular (FIG. 8A, shows item 58 is rectangular).
Regarding claim 9. Servalli et al discloses a memory device, comprising:
an array of memory cells ([0089]) that each include: a transistor ([0044]), comprising:
a pillar (FIG. 8A, item 12) that includes an upper source/drain (FIG. 8A, item 16), a lower source/drain (FIG. 8A, item 18), and a channel (FIG. 8A, item 20) between the upper source/drain (FIG. 8A, item 16) and the lower source/drain (FIG. 8A, item 18), one or more gates (FIG. 8A, item 26) that are part of one or more gate lines and that are proximate to the channel (FIG. 8A, item 20);
a capacitor ([0100]), comprising:
a bottom electrode ([0100]; FIG. 8A, item 56; [0080]), an insulator ([0100]), and a top electrode ([0100]); and
a conductive contact region (FIG. 8A, item 58) that couples ([0100]) the transistor ([0044]) and the capacitor ([0100]), comprising: the upper source/drain (FIG. 8A, item 16),
a first conductive region (FIG. 8A, item 58 left side) having a right surface (FIG. 8A, item 58 left side right surface) that abuts the upper source/drain (FIG. 8A, item 16) and having a left surface (FIG. 8A, item 58 left side left surface) that contacts a first insulator line (FIG. 8A, item 22 on left on left of item 16), and a second conductive region (FIG. 8A, item 58 right side) having a left surface (FIG. 8A, item 58 right side left surface) that abuts the upper source/drain (FIG. 8A, item 16) and having a right surface (FIG. 8A, item 58 right side right surface) that contacts a second insulator line (FIG. 8A, item 22 on right of item 16) that is parallel to the first insulator line (FIG. 8A, item 22 on left of item 16).
Servalli et al fails to explicitly a cylindrical electrode pillar.
However Zhao et al teaches a cylindrical bottom pillar ([0095], i.e. a cylinder capacitor).
Zhao et al further discloses capacitors ([0095]) may include any suitable structure and configuration, such as a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor.
Since Servalli et al and Zhao et al disclose bottom electrodes as plates for capacitors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the integrated assembly as disclosed to modify Servalli et al with the teachings of a cylindrical electrode pillar as disclosed by Zhao et al as one of ordinary skill would have found it obvious to substitute the element with a predictable result as a capacitor. The use of a cylinder capacitor in Zhao et al provides an array of memory cells can be arranged in a staggered layout in the plan view to further increase the cell density and reduce the unit cell size (Zhao et al, [0048]). See MPEP 2144.06 II Art Recognized Equivalent for the same purpose.
Regarding claim 10. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 9 above.
Servalli et al further discloses wherein a shape of a top surface (FIG. 8, shows item 58) of the conductive contact region (FIG. 8, shows item 58) is approximately a rectangle (FIG. 8, shows item 58 is approximately a rectangle).
Regarding claim 11. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 9 above.
Servalli et al further discloses wherein the pillar (FIG. 8, shows item 12) is approximately a rectangular prism (FIG. 8, shows item 16 of item 12 is approximately rectangular prism).
Regarding claim 12. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 9 above.
Servalli et al further discloses wherein a distance ([0077]) between memory cells ([0089]) along a direction parallel (FIG. 8, item X) to the first insulator line (FIG. 8A, item 22 on left on left of item 16) and the second insulator line (FIG. 8A, item 22 on right of item 16) is smaller ([0077]; FIG. 8 shows width of item 52 is smaller than a width of item 53) than a distance ([0077]) between memory cells ([0089]) along a direction perpendicular (FIG. 8, item Y) to the first insulator line (FIG. 8A, item 22 on right of item 16) and the second insulator line (FIG. 8A, item 22 on right of item 16).
Regarding claim 13. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 9 above.
Servalli et al further discloses wherein a first plurality (FIG. 8, annotated first plurality) of bottom electrodes (FIG. 8A, item 56), included in a first plurality (FIG. 8, annotated first plurality) of capacitors ([0100]) that extends along a direction perpendicular (FIG. 8A, item Z is perpendicular to item Y) to the first insulator line (FIG. 8A, item 22 on left of item 16) and the second insulator line (FIG. 8A, item 22 on right of item 16), are in contact ([0100]) with a corresponding plurality of first conductive regions (FIG. 8A, item 58).
PNG
media_image2.png
769
613
media_image2.png
Greyscale
Regarding claim 14. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 13 above.
Servalli et al further discloses wherein a second plurality (FIG. 8, annotated second plurality) of bottom electrodes (FIG. 8A, item 56), included in a second plurality (FIG. 8, annotated second plurality) of capacitors ([0100]) that is adjacent (FIG. 8 shows first plurality is adjacent second plurality) to the first plurality (FIG. 8, annotated first plurality) of capacitors ([0100]), are in contact with a corresponding plurality of second conductive regions (FIG. 8A, item 58).
PNG
media_image2.png
769
613
media_image2.png
Greyscale
Regarding claim 15. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 9 above.
Servalli et al further discloses wherein consecutive bottom electrodes (FIG. 8A, item 56), included in a plurality of capacitors ([0100]) that extends along a direction parallel (FIG. 8A, item Y) to the first insulator line (FIG. 8A, item 22 on left of item 16) and the second insulator line (FIG. 8A, item 22 on right of item 16), alternate between being in contact with a respective first conductive region (FIG. 8A, item 58 left side) and a respective second conductive region (FIG. 8A, item 58 right side).
Regarding claim 16. Servalli et al and Zhao et al discloses all the limitations of the memory device of claim 9 above.
Servalli et al further discloses wherein consecutive conductive contact regions (FIG. 8A, item 58), included in a column of memory cells ([0100]) that extends along a direction parallel (FIG. 8A, item Y) to the first insulator line (FIG. 8A, item 22 on left of item 16) and the second insulator line (FIG. 8A, item 22 on right of item 16), are separated by respective insulative spacer regions (FIG. 8, item 52) that each abut the first insulator line (FIG. 8A, item 22 on left of item 16) and the second insulator line (FIG. 8A, item 22 on right of item 16).
Response to Arguments
Applicant's arguments filed November 26, 2025 have been fully considered but they are not persuasive.
On page 10 of applicant’s remarks, applicant appears to argue that the spec in [0067] and Fig 5 shows applicant’s claim 12.
Examiner respectfully disagrees. Examiner respectfully points out that this is a drawing objection, not a specification. Applicant’s FIG. 5 shows that the distance between memory cells along a y-direction is smaller than a distance between memory cells along the x-direction. Examiner further points out that in the x direction (up/down arrow of FIG. 5) the horizontal lines do not overlap the outer solid lines of the capacitor, however in the y-direction (left right) the vertical lines do overlap the outer solid lines of the capacitor, therefore, the distance between memory cells along a y-direction is smaller than a distance between memory cells along the x-direction.
On page 12 of applicant’s remarks, applicant argues that Servalli et al fails to disclose the claimed a cylindrical electrode pillar that is in contact with a conductive contact region formed by the first conductor line, the second conductor line, and the upper source/drain in amended claim 1 and 9.
Examiner respectfully points out that Servalli et al in view of Zhao et al discloses applicant’s amended claim 1 and 9. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.E.B./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815