DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Figs. 8A, 8B, and 8C does not show any labeling of the claimed limitations “one or more metal layers within an interior volume of the co-spiral inductor”. There are no corresponding descriptions from the specification that discusses “one or more metal layers within an interior volume of the co-spiral inductor”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10-14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. [U.S. Pub. No. 2009/0273429] in view of Kim [U.S. Pub. No. 2008/0157913] and Park et al. [U.S. Pub. No. 2016/0078998].
Regarding Claim 1, Nakamura et al. shows an apparatus including a co-spiral inductor (Fig. 3C with teachings from Figs. 2A-2C, 4A-4C, 5A-6D, 7A-7C) comprising:
a plurality of turns (21a, 21b, 21c), each of the plurality of turns being displaced both vertically and horizontally from a next successive turn (see Fig. 3C, elements 21a, 21b, 21c are displaced both vertically and horizontally from a next successive turn), wherein the plurality of turns is formed from traces on different metal layers formed on a substrate (see Fig. 3C, elements 21a, 21b, 21c is formed from traces/conductors on different metal layers formed a substrate as disclosed in Paragraphs [0016], [0033], [0041], [0082], claim 1);
a plurality of insulators (24 or 42a, 42b, 42c) configured to electrically insulate each of the plurality of turns (see Fig. 3C, elements 24 or 42a, 42b, 42c configured to electrically insulate elements 21a, 21b, 21c); and
a plurality of interconnects (vias) configured to couple each of the plurality of turns to at least one other turn (vias are configured to couple elements 21a, 21b, 21c as disclosed in Paragraphs [0046]-[0047]).
Nakamura et al. does not explicitly show the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor.
Kim clearly shows a spiral inductor (Figs. 2A-2B with teachings from Figs. 3-11) teaching and suggesting the plurality of turns (210, 213, 216) is formed from traces on different metal layers formed on a substrate (200, see Figs. 2A-2B, elements 210, 213, 216 is formed from traces/metal lines on different metal layers formed on element 200). Also, Kim shows a plurality of insulators (205a, 208a, 211a, 214a) configured to electrically insulate each of the plurality of turns (see Figs. 2A-2B, elements 205a, 208a, 211a, 214a configured to electrically insulate elements 210, 213, 216).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of turns is formed from traces on different metal layers formed on a substrate as taught by Kim for the inductor as disclosed by Nakamura et al. to facilitate mechanical stability and support to reduce the loss due to eddy current or displaced current and improving the quality of the inductor (Paragraph [0007]).
Nakamura et al. in view of Kim does not explicitly show the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor.
Park et al. shows an inductor (Figs. 12-22) teaching and suggesting the apparatus (see Figs. 12-22) includes one or more metal layers (30, 30c, element 150 that forms element 30, Paragraphs [0049]-[0050]) within an interior volume of the co-spiral inductor (see Figs. 12-22).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor as taught by Park et al. for the inductor as disclosed by Nakamura et al. in view of Kim to reduce a step difference between the region on which the coil pattern is formed and the region on which the coil pattern is not formed such that planarization process does not need to be performed and reliability of a lithography process may be enhanced (Paragraphs [0056], [0061]).
Regarding Claim 2, Nakamura et al. shows the plurality of interconnects (vias) are configured to couple each of the plurality of turns in series (vias are configured to couple elements 21a, 21b, 21c in series as disclosed in Paragraphs [0046]-[0047]).
Kim shows the plurality of interconnects are configured to couple each of the plurality of turns in series (Paragraphs [0020]-[0022]).
Regarding Claim 3, Nakamura et al. in view of Kim shows the claimed invention as applied above but does not explicitly disclose having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel.
However, having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel would have been an obvious design choice based on intended and/or environmental use to achieve desirable inductance values.
Regarding Claim 4, Nakamura et al. shows the plurality of turns are hexagonal, circular, square, or rectangular in shape (Paragraph [0090], see Fig. 2A).
Kim shows the plurality of turns are hexagonal, circular, square, or rectangular in shape (see Figs. 2A-2B, Paragraphs [0020]-[0022]).
Regarding Claim 5, Nakamura et al. shows the plurality of turns are tapered with a first turn of the plurality of turns having a smallest length and a last turn of the plurality of turns having a greatest length (see Figs. 2A-2C and Fig. 3C, elements 21a, 21b, 21c are tapered with element 21c having a smallest length and element 21a having a greatest length).
Kim shows the plurality of turns are tapered with a first turn of the plurality of turns having a smallest length and a last turn of the plurality of turns having a greatest length (see Figs. 2A-2B, Paragraph [0021]).
Regarding Claim 6, Nakamura et al. shows each of the plurality of turns is formed on a separate layer from any other turn of the plurality of turns (see Fig. 3C, elements 21a, 21b, 21c is formed on a separate layer from any other turn of elements 21a, 21b, 21c).
Kim shows each of the plurality of turns is formed on a separate layer from any other turn of the plurality of turns (see Figs. 2A-2B, elements 210, 213, 216 is formed on a separate layer from any other turn of elements 210, 213, 216).
Regarding Claim 10, Nakamura et al. shows at least two of the plurality of turns have different thicknesses (see Fig. 3C, elements 21a, 21b have different thicknesses, Paragraph [0049]).
Kim shows at least two of the plurality of turns have different thicknesses (see Figs. 22-23, at least two of the plurality of turns have different thicknesses).
Regarding Claim 11, Nakamura et al. shows a first turn (21a) closest to the substrate (Paragraphs [0016], [0033], [0041], [0049], [0082], claim 1) has a smaller thickness than a last turn (21c) furthest away from the substrate (see Fig. 3C, element 21a closest to the substrate has a smaller thickness than element 21c furthest away from the substrate as disclosed Paragraphs [0016], [0033], [0041], [0049], [0082], claim 1).
Kim shows a first turn (outer turn as shown in Fig. 23) closest to the substrate (400) has a smaller thickness than a last turn (inner turn as shown in Fig. 23) furthest away from the substrate (see Fig. 23).
Regarding Claim 12, Nakamura et al. shows at least one outer turn is formed from at least two stacked metal layers of different metal layers (see Figs. 7B-7C upside down, at least one outer turn is formed from at least two stacked metal layers elements 51d, 51e of different metal layers).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have at least one outer turn is formed from at least two stacked metal layers of different metal layers as taught by Nakamura et al. in the embodiment of Figs. 7B-7C for the inductor as disclosed by Nakamura et al. in the embodiment of Fig. 3C to reduce total eddy current loss, suppressing series resistance, reduce capacitance, and improve Q factor (Paragraph [0088]).
Kim shows at least one outer turn is formed from at least two stacked metal layers of different metal layers (see Fig. 2B, at least one outer turn is formed from at least two stacked metal layers [either metal layers at elements 211a, 214a or metal layers at elements 208a, 211a] of different metal layers).
Kim also shows at least one outer turn is formed from at least two stacked metal layers of different metal layers (see Fig. 23, at least one outer turn is formed from at least two stacked metal layers of different metal layers).
Regarding Claim 13, Nakamura et al. shows the at least one outer turn has at least one via layer (52d) that couples the at least two stacked metal layers (see Figs. 7B-7C).
Regarding Claim 14, Kim shows the at least two stacked metal layers are on same metal layers as at least one other turn of the plurality of turns (see Fig. 2B, the at least two stacked metal layers [either metal layers at elements 211a, 214a or metal layers at elements 208a, 211a] are on same metal layers as at least one other turn of the plurality of turns).
Kim also shows the at least two stacked metal layers are on same metal layers as at least one other turn of the plurality of turns (see Fig. 23, the at least two stacked metal layers are on same metal layers as at least one other turn of the plurality of turns).
Regarding Claim 16, Nakamura et al. in view of Kim shows the claimed invention as applied above but does not explicitly disclose having the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof.
However, having the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof would have been an obvious design choice based on intended and/or environmental use to achieve desirable conductivity and inductance values.
Claim(s) 1-6, 10-14, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim [U.S. Pub. No. 2008/0157913] in view of Nakamura et al. [U.S. Pub. No. 2009/0273429] and Annen [U.S. Pub. No. 2020/0043645].
Regarding Claim 1, Kim shows an apparatus including a co-spiral inductor (Figs. 2A-2B with teachings from Figs. 3-11) comprising:
a plurality of turns (210, 213, 216), each of the plurality of turns being displaced both vertically and horizontally from a next successive turn (see Figs. 2A-2B, elements 210, 213, 216 are displaced both vertically and horizontally from a next successive turn), wherein the plurality of turns is formed from traces on different metal layers formed on a substrate (200, see Figs. 2A-2B, elements 210, 213, 216 is formed from traces/metal lines on different metal layers formed on element 200);
a plurality of insulators (205a, 208a, 211a, 214a) configured to electrically insulate each of the plurality of turns (see Figs. 2A-2B, elements 205a, 208a, 211a, 214a configured to electrically insulate elements 210, 213, 216).
Kim does not explicitly disclose having a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn and the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor.
Nakamura et al. shows an inductor (Fig. 3C with teachings from Figs. 2A-2C, 4A-4C, 5A-6D, 7A-7C) teaching and suggesting a plurality of interconnects (vias) configured to couple each of the plurality of turns to at least one other turn (vias are configured to couple elements 21a, 21b, 21c as disclosed in Paragraphs [0046]-[0047]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have a plurality of interconnects configured to couple each of the plurality of turns to at least one other turn as taught by Nakamura et al. for the inductor as disclosed by Kim to facilitate electrical connection of the plurality of turns to achieve desirable inductance value and improve Q factor (Paragraph [0021]).
Kim in view of Nakamura et al. does not explicitly disclose having the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor.
Annen shows an inductor (Figs. 1-2) teaching and suggesting the apparatus (see Figs. 1-2) includes one or more metal layers (51, 52, 53, 54, Paragraph [0059]) within an interior volume of the co-spiral inductor (see Figs. 1-2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the apparatus includes one or more metal layers within an interior volume of the co-spiral inductor as taught by Annen for the inductor as disclosed by Kim in view of Nakamura et al. to suppress the decrease in the adhesion strength, whereby an effect of suppression of the interfacial peeling is more effectively exhibited (Paragraphs [0018], [0054], [0085]).
Regarding Claim 2, Kim shows the plurality of interconnects are configured to couple each of the plurality of turns in series (Paragraphs [0020]-[0022]).
Nakamura et al. shows the plurality of interconnects (vias) are configured to couple each of the plurality of turns in series (vias are configured to couple elements 21a, 21b, 21c in series as disclosed in Paragraphs [0046]-[0047]).
Regarding Claim 3, Kim in view Nakamura et al. shows the claimed invention as applied above but does not explicitly disclose having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel.
However, having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel would have been an obvious design choice based on intended and/or environmental use to achieve desirable inductance values.
Regarding Claim 4, Kim shows the plurality of turns are hexagonal, circular, square, or rectangular in shape (see Figs. 2A-2B, Paragraphs [0020]-[0022]).
Nakamura et al. shows the plurality of turns are hexagonal, circular, square, or rectangular in shape (Paragraph [0090], see Fig. 2A).
Regarding Claim 5, Kim shows the plurality of turns are tapered with a first turn of the plurality of turns having a smallest length and a last turn of the plurality of turns having a greatest length (see Figs. 2A-2B, Paragraph [0021]).
Nakamura et al. shows the plurality of turns are tapered with a first turn of the plurality of turns having a smallest length and a last turn of the plurality of turns having a greatest length (see Figs. 2A-2C and Fig. 3C, elements 21a, 21b, 21c are tapered with element 21c having a smallest length and element 21a having a greatest length).
Regarding Claim 6, Kim shows each of the plurality of turns is formed on a separate layer from any other turn of the plurality of turns (see Figs. 2A-2B, elements 210, 213, 216 is formed on a separate layer from any other turn of elements 210, 213, 216).
Nakamura et al. shows each of the plurality of turns is formed on a separate layer from any other turn of the plurality of turns (see Fig. 3C, elements 21a, 21b, 21c is formed on a separate layer from any other turn of elements 21a, 21b, 21c).
Regarding Claim 10, Kim shows at least two of the plurality of turns have different thicknesses (see Figs. 22-23, at least two of the plurality of turns have different thicknesses).
Nakamura et al. shows at least two of the plurality of turns have different thicknesses (see Fig. 3C, elements 21a, 21b have different thicknesses, Paragraph [0049]).
Regarding Claim 11, Kim shows a first turn (outer turn as shown in Fig. 23) closest to the substrate (400) has a smaller thickness than a last turn (inner turn as shown in Fig. 23) furthest away from the substrate (see Fig. 23).
Nakamura et al. shows a first turn (21a) closest to the substrate (Paragraphs [0016], [0033], [0041], [0049], [0082], claim 1) has a smaller thickness than a last turn (21c) furthest away from the substrate (see Fig. 3C, element 21a closest to the substrate has a smaller thickness than element 21c furthest away from the substrate as disclosed Paragraphs [0016], [0033], [0041], [0049], [0082], claim 1).
Regarding Claim 12, Kim shows at least one outer turn is formed from at least two stacked metal layers of different metal layers (see Fig. 2B, at least one outer turn is formed from at least two stacked metal layers [either metal layers at elements 211a, 214a or metal layers at elements 208a, 211a] of different metal layers).
Kim also shows at least one outer turn is formed from at least two stacked metal layers of different metal layers (see Fig. 23, at least one outer turn is formed from at least two stacked metal layers of different metal layers).
Nakamura et al. shows at least one outer turn is formed from at least two stacked metal layers of different metal layers (see Figs. 7B-7C upside down, at least one outer turn is formed from at least two stacked metal layers elements 51d, 51e of different metal layers).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have at least one outer turn is formed from at least two stacked metal layers of different metal layers as taught by Nakamura et al. in the embodiment of Figs. 7B-7C for the inductor as disclosed by Nakamura et al. in the embodiment of Fig. 3C to reduce total eddy current loss, suppressing series resistance, reduce capacitance, and improve Q factor (Paragraph [0088]).
Regarding Claim 13, Nakamura et al. shows the at least one outer turn has at least one via layer (52d) that couples the at least two stacked metal layers (see Figs. 7B-7C).
Regarding Claim 14, Kim shows the at least two stacked metal layers are on same metal layers as at least one other turn of the plurality of turns (see Fig. 2B, the at least two stacked metal layers [either metal layers at elements 211a, 214a or metal layers at elements 208a, 211a] are on same metal layers as at least one other turn of the plurality of turns).
Kim also shows the at least two stacked metal layers are on same metal layers as at least one other turn of the plurality of turns (see Fig. 23, the at least two stacked metal layers are on same metal layers as at least one other turn of the plurality of turns).
Regarding Claim 16, Kim in view of Nakamura et al. shows the claimed invention as applied above but does not explicitly disclose having the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof.
However, having the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof would have been an obvious design choice based on intended and/or environmental use to achieve desirable conductivity and inductance values.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Groves et al. [U.S. Pub. No. 2012/0188047].
Regarding Claim 3, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not explicitly disclose having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel.
However, having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel would have been an obvious design choice based on intended and/or environmental use to achieve desirable inductance values.
Groves et al. shows an inductor structure (Fig. 2) teaching and suggesting at least one of the plurality of interconnects (208) is configured to couple at least two of the plurality of turns (102, 104) in parallel (Paragraph [0026]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel as taught by Groves et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to achieve desirable inductance values as required by design requirements.
Claim(s) 3 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Vanukuru et al. [U.S. Pub. No. 2020/0312514].
Regarding Claim 3, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not explicitly disclose having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel.
However, having at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel would have been an obvious design choice based on intended and/or environmental use to achieve desirable inductance values.
Vanukuru et al. shows an inductor (Figs. 2-5) teaching and suggesting at least one of the plurality of interconnects (48) is configured to couple at least two of the plurality of turns (12, 14, 16) in parallel (Paragraph [0016]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have at least one of the plurality of interconnects is configured to couple at least two of the plurality of turns in parallel as taught by Vanukuru et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to achieve desirable inductance values as required by design requirements.
Regarding Claim 15, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not explicitly disclose the plurality of insulators is formed of one or more of silicon dioxide (SiO2), an organic polymeric dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), Polybenzoxazoles (PBO), or silicone based polymeric dielectrics.
Vanukuru et al. shows an inductor (Figs. 2-5) teaching and suggesting the plurality of insulators (62-78) is formed of one or more of silicon dioxide (SiO2) (Paragraph [0028]), an organic polymeric dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), Polybenzoxazoles (PBO), or silicone based polymeric dielectrics.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of insulators is formed of one or more of silicon dioxide (SiO2), an organic polymeric dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), Polybenzoxazoles (PBO), or silicone based polymeric dielectrics as taught by Vanukuru et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate insulation to prevent unwanted connection and short-circuiting (Paragraph [0028]).
Regarding Claim 16, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not explicitly disclose the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof.
Vanukuru et al. shows an inductor (Figs. 2-5) teaching and suggesting the plurality of turns is formed of one or more of copper (Cu) (Paragraph [0028]), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof as taught by Vanukuru et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate conductivity and reduce cost based on the inexpensive material of copper to achieve desirable operating characteristics and inductance values (Paragraph [0028]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Okamoto et al. [U.S. Pub. No. 2019/0103213].
Regarding Claim 5, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above.
In addition, Okamoto et al. shows an electronic device (Figs. 13A-13B) teaching and suggesting the plurality of turns (31B, 32B, 33B, 34B) are tapered with a first turn of the plurality of turns having a smallest length and a last turn of the plurality of turns having a greatest length (see Figs. 13A-13B, elements 31B, 32B, 33B, 34B are tapered with element 34B having a smallest length and element 31B having a greatest length).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of turns are tapered with a first turn of the plurality of turns having a smallest length and a last turn of the plurality of turns having a greatest length as taught by Okamoto et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to form a conical coil which the interline capacitance between loop shaped conductors is reduced or prevented (Paragraph [0120]).
Claim(s) 7-9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Jin et al. [U.S. Pub. No. 2012/0147578].
Regarding Claim 7, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the substrate is part of a flip-chip.
Jin et al. shows a packaging (Figs. 1-2) teaching and suggesting the substrate (46, 110, or 212) is part of a flip-chip (Paragraphs [0011], [0022], claim 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the substrate is part of a flip-chip as taught by Jin et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate stacking of electrical components to reduce area to reduce RF loss and eliminate yield loss and ESD damage caused by formation of bond wires (Paragraph [0020]).
Regarding Claim 8, Jin et al. shows a package substrate (26) coupled to the substrate on a first side of the package substrate that faces the co-spiral inductor (see Figs. 1-2, element 26 is mechanically coupled to element 46, 110, or 212 on a first side of element 26 that faces element 116, 216, Paragraphs [0011], [0012]).
Regarding Claim 9, Jin et al. shows a printed circuit board (20) coupled to the package substrate on a second side of the package substrate that is opposite the first side (see Figs. 1-2, element 20 is coupled to element 26 on a second side of element 26 that is opposite the first side).
Regarding Claim 17, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the substrate is formed of one or more of silicon (Si), High-resistivity silicon (HRSi), glass, aluminum oxide (Alumina), compounds or combinations thereof.
Jin et al. shows a packaging (Figs. 1-2) teaching and suggesting the substrate (110) is formed of one or more of silicon (Si), High-resistivity silicon (HRSi), glass, aluminum oxide (Alumina), compounds or combinations thereof (Paragraph [0013]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the substrate is formed of one or more of silicon (Si), High-resistivity silicon (HRSi), glass, aluminum oxide (Alumina), compounds or combinations thereof as taught by Jin et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate mechanical stability, insulation to prevent unwanted connection and stacking of electrical components to reduce area to reduce RF loss and eliminate yield loss and ESD damage caused by formation of bond wires (Paragraph [0020]).
Claim(s) 7-9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Sridharan et al. [U.S. Pub. No. 2003/0017646].
Regarding Claim 7, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the substrate is part of a flip-chip.
Sridharan et al. shows a packaging (Figs. 1-8) teaching and suggesting the substrate (68) is part of a flip-chip (Paragraphs [0045]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the substrate is part of a flip-chip as taught by Sridharan et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate stacking of electrical components to reduce area to achieve an advanced packaging systems to obtain desirable operating characteristics and performance (Paragraph [0009]).
Regarding Claim 8, Sridharan et al. shows a package substrate (100) coupled to the substrate on a first side of the package substrate that faces the co-spiral inductor (see Figs. 1-8, element 100 is mechanically coupled to element 68 on a first side of element 100 that faces element 30 in elements 72, 74, 76, Paragraphs [0035], [0036]).
Regarding Claim 9, Sridharan et al. shows a printed circuit board (134, Paragraph [0048]) coupled to the package substrate on a second side of the package substrate that is opposite the first side (see Figs. 1-8, element 134, Paragraph [0048], is coupled to element 100 on a second side of element 100 that is opposite the first side).
Regarding Claim 17, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the substrate is formed of one or more of silicon (Si), High-resistivity silicon (HRSi), glass, aluminum oxide (Alumina), compounds or combinations thereof.
Sridharan et al. shows a packaging (Figs. 1-8) teaching and suggesting the substrate (110) is formed of one or more of silicon (Si), High-resistivity silicon (HRSi), glass, aluminum oxide (Alumina), compounds or combinations thereof (Paragraph [0044]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the substrate is formed of one or more of silicon (Si), High-resistivity silicon (HRSi), glass, aluminum oxide (Alumina), compounds or combinations thereof as taught by Jin et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate mechanical stability, improve fabrication, insulation to prevent unwanted connection and stacking of electrical components to reduce area to achieve an advanced packaging systems to obtain desirable operating characteristics and performance (Paragraphs [0009], [0044]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Wang [U.S. Pub. No. 2005/0190035].
Regarding Claim 15, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the plurality of insulators is formed of one or more of silicon dioxide (SiO2), an organic polymeric dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), Polybenzoxazoles (PBO), or silicone based polymeric dielectrics.
Wang shows an inductor (Fig. 3) teaching and suggesting the plurality of insulators (101, 103, 105) is formed of one or more of silicon dioxide (SiO2) (Paragraph [0022]), an organic polymeric dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), Polybenzoxazoles (PBO), or silicone based polymeric dielectrics.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of insulators is formed of one or more of silicon dioxide (SiO2), an organic polymeric dielectric, polyimide (PI), polynorbornene, benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), Polybenzoxazoles (PBO), or silicone based polymeric dielectrics as taught by Wang for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate insulation to prevent unwanted connection and short-circuiting (Paragraph [0022]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Yosui et al. [U.S. Pub. No. 2018/0151287].
Regarding Claim 16, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof.
Yosui et al. shows a multilayer substrate (Fig. 1) teaching and suggesting the plurality of turns (22-1 to 22-4) is formed of one or more of copper (Cu) (Paragraph [0050]), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the plurality of turns is formed of one or more of copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (P1), aluminum (Al), Titanium (Ti), tin (Sn), alloys or combinations thereof as taught by Yosui et al. for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to facilitate conductivity and reduce cost based on the inexpensive material and low-specific resistance of copper to achieve desirable operating characteristics and inductance values (Paragraph [0050]).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Kim et al. [U.S. Pub. No. 2018/0033537] (hereinafter as “Kim ‘537”).
Regarding Claim 18, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, a RF front end (RFFE) circuit, a power combiner, or a diplexer.
Kim ‘537 shows a co-spiral inductor (Figs. 1-9) teaching and suggesting the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, a RF front end (RFFE) circuit (150), a power combiner, or a diplexer (Paragraphs [0028], [0031], [0032], [0035], [0037], [0051], claims 10, 15).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, a RF front end (RFFE) circuit, a power combiner, or a diplexer as taught by Kim ‘537 for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to achieve an inductor structure for high quality Q-factor radio frequency (RF) application (Paragraphs [0002], [0029]-[0030]).
Regarding Claim 19, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the co-spiral inductor is formed in a back end of line (BEOL) stack or the BEOL stack and one or more redistribution layers (RDL).
Kim ‘537 shows a co-spiral inductor (Figs. 1-9) teaching and suggesting the co-spiral inductor is formed in a back end of line (BEOL) stack (Paragraph [0025]) or the BEOL stack and one or more redistribution layers (RDL).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the co-spiral inductor is formed in a back end of line (BEOL) stack or the BEOL stack and one or more redistribution layers (RDL) as taught by Kim ‘537 for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to improve semiconductor fabrication enabling performance and structural booster to achieve an inductor structure for high quality Q-factor radio frequency (RF) application (Paragraphs [0002], [0029]-[0030]).
Regarding Claim 20, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle.
Kim ‘537 shows a co-spiral inductor (Figs. 1-9) teaching and suggesting the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle (Paragraphs [0028], [0031], [0032], [0035], [0037], [0051], claims 10, 15).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle as taught by Kim ‘537 for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to achieve an inductor structure for high quality Q-factor radio frequency (RF) application (Paragraphs [0002], [0029]-[0030]).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen as applied to claim 1 above, and further in view of Kim et al. [U.S. Pub. No. 2017/0200550] (hereinafter as “Kim ‘550”).
Regarding Claim 18, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, a RF front end (RFFE) circuit, a power combiner, or a diplexer.
Kim ‘550 shows a co-spiral inductor (Figs. 1-10) teaching and suggesting the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, a RF front end (RFFE) circuit, a power combiner, or a diplexer (Paragraphs [0063], [0064], claims 10, 15).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the apparatus comprises at least one of a hybrid integrated passive device (HIP), an active component integrated with a HIP, a radio frequency (RF) filter, a RF front end (RFFE) circuit, a power combiner, or a diplexer as taught by Kim ‘550 for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to achieve an inductor structure for high quality Q-factor radio frequency (RF) application (Paragraphs [0002], [0029]-[0030]).
Regarding Claim 19, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the co-spiral inductor is formed in a back end of line (BEOL) stack or the BEOL stack and one or more redistribution layers (RDL).
Kim ‘550 shows a co-spiral inductor (Figs. 1-10) teaching and suggesting the co-spiral inductor is formed in a back end of line (BEOL) stack (Paragraph [0027]) or the BEOL stack and one or more redistribution layers (RDL).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the co-spiral inductor is formed in a back end of line (BEOL) stack or the BEOL stack and one or more redistribution layers (RDL) as taught by Kim ‘550 for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to improve semiconductor fabrication enabling performance and structural booster to achieve an inductor structure for high quality Q-factor radio frequency (RF) application (Paragraphs [0002], [0029]-[0030]).
Regarding Claim 20, Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen shows the claimed invention as applied above but does not show the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle.
Kim ‘550 shows a co-spiral inductor (Figs. 1-10) teaching and suggesting the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle (Paragraphs [0063], [0064], claims 10, 15).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to have the apparatus is selected from a group comprising at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, or a device in an automotive vehicle as taught by Kim ‘550 for the inductor as disclosed by Nakamura et al. in view of Kim and Park et al. OR Kim in view of Nakamura et al. and Annen to achieve an inductor structure for high quality Q-factor radio frequency (RF) application (Paragraphs [0002], [0029]-[0030]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZFUNG J CHAN whose telephone number is (571)270-7981. The examiner can normally be reached M-TH 8:00AM-6:00PM.
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/TSZFUNG J CHAN/Primary Examiner, Art Unit 2837