DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 requires the limitation “a one-piece, continuous heat spreader between the SOC package and the memory package, wherein the heat spreader is in direct contact with a back surface of the logic die away from the pads or the bottom surface of the second substrate”. It is unclear whether the claim requires that the heat spreader is in direct contact with either the back surface of the logic die or the bottom surface of the second substrate, or that the claim requires that the heat spreader is in direct contact with the back surface of the logic die and is away from both the pads and the bottom surface of the second substrate. The Examiner suggests adding the appropriate punctuation to clearly require what Applicant intends of the claim.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 12-23 are rejected under 35 U.S.C. 103 as being unpatentable over embodiments of Kim (“Kim ‘849” US 2014/0340849) in view of Kim et al. (“Kim ‘774” US 2016/0300774).
Regarding claim 1, Kim ‘849 discloses a semiconductor package assembly (Figure 1), comprising:
a system-on-chip (SOC) package (20), comprising:
a logic die (25, para. [0046]) having pads (28); and
a first substrate (21) electrically connected to the logic die (25) by the pads (28, see Figure 1, para. [0047]);
a memory package (40) stacked on the SOC package (20, see Figure 1), comprising:
a second substrate (41) having a top surface and a bottom surface (see Figure 1);
a memory die (45) mounted on the top surface of the second substrate (41) and electrically connected to the second substrate (41) using bonding wires (48, see para. [0050]); and
conductive structures (73U, see manufacturing step in Figure 18 and para. [0112]) disposed on the bottom surface of the second substrate (41) and electrically connected to the SOC package (through 73B, see Figure 18 and para. [0112]); and
a one-piece, continuous heat spreader (11) between the SOC package (20) and the memory package (40), wherein the heat spreader is [in direct contact with a back surface of the logic die] away from the pads (28, see Figure 1) [or the bottom surface of the second substrate], and wherein the conductive structures (73U) of the memory package (40) are located outside or exposed from the heat spreader (11, see Figures 1 and 18).
Figure 1 of Kim ‘849 does not disclose the heat spreader being in direct contact with the logic die or the bottom surface of the second substrate, instead there is a thermal interface material (81) between the heat sink and the back surface of the logic die and the bottom surface of the second substrate (see Figure 1).
However, Kim ‘849 discloses in the embodiment of Figure 24 a heat spreader (11, portion 14) in direct contact with a back surface of a logic die (25, see Figure 24).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of the embodiment of Figure 24 of Kim ‘849 into the embodiment of Figure 1 of Kim ‘849 to include the heat spreader directly contacting the logic die for the purpose of increased transferring of heat from the logic die to the heat spreader (Kim ‘774, para. [0106]).
Regarding claim 2, The embodiment of Figure 24 of Kim ‘849 discloses an underfill (81D, while disclosed as a thermal interface material, the material may include a curable resin, see para. [0059], which is known in the art as a common material for an underfill material, thus the thermal interface material 81D may be considered as an underfill) filling a gap between the SOC package (20) and the memory package (40, see Figure 24), wherein the underfill (81D) is in contact with the heat spreader (11, see Figure 24).
Regarding claim 3, The embodiment of Figure 24 of Kim ‘849 discloses wherein the heat spreader (11) is between the underfill (81D) and the back surface of the logic die (25, see Figure 24).
Regarding claim 4, Kim ‘849 discloses wherein the heat spreader (11) partially overlaps the bottom surface of the second substrate (41, see Figure 1).
Regarding claim 5, Kim ‘849 discloses wherein the heat spreader (11) covers the entire memory die (45, Figure 1 shows the heat spreader 11 vertically covering the entire top surface of the memory die 45).
Regarding claim 6, Kim ‘849 discloses wherein the heat spreader (11) is wrapped around the memory package (40, Figure 1 shows the heat spreader 11 wrapped around the left side of the memory package 40) and partially covers a top surface and side surfaces of the memory package (40, Figure 1 shows the heat spreader partially covering the top surface and the right side surface combined, since the heat spreader does not necessarily cover the right side of the memory package 40).
Regarding claim 7, Kim ‘849 discloses wherein the heat spreader (11) is wrapped around the memory package (40) and fully covers a top surface and side surfaces of the memory package (40, the heat spreader 11 fully covers the top surface and the left side surface combined).
Regarding claim 8, Kim ‘849 discloses wherein the heat spreader (11) is wrapped around side surfaces of the SOC package (20, top surfaces are considered side surfaces of the SOC package) and partially covers a top surface of the SOC package (20, see Figure 1).
Regarding claim 9, Kim ‘849 discloses wherein the SOC package (20) comprises:
a molding compound (29) surrounding the logic die (25), being in contact with the first substrate (21) and the logic die (25, see Figure 1); and
first conductive structures (73B, see manufacturing step of Figure 18, which shows the bottom part 73B of the structures 73 before joining together) passing through the molding compound (29) and electrically connected to the memory package (40, through 73U), wherein the first conductive structures (73B) of the SOC package (20) are separated from the heat spreader (11, see Figure 1).
Regarding claim 10, Kim ‘849 discloses wherein the conductive structures (73U) of the memory package (40) are electrically connected to the first conductive structures (73B) of the SOC package (20, see Figure 1 and para. [0112]), and wherein the conductive structures (73U) of the memory package (40) are separated from the heat spreader (11, see Figure 1).
Regarding claim 12, Kim ‘849 discloses wherein the heat spreader (11) comprises a conductive material (see para. [0058]).
Regarding claim 13, Kim ‘849 further discloses an adhesive (83) between the heat spreader (11) and the memory package (40, see Figure 1, although 83 is disclosed as a thermal interface material, it may include a curable resin which in the art is a known adhesive, additionally the thermal interface material 83 is disposed between the memory package 40 and the heat spreader 11, thus must also function as a means for adhesion between the memory package and the heat spreader).
Regarding claim 14, Kim ‘849 discloses a semiconductor package assembly (Figure 1), comprising:
a system-on-chip (SOC) package (20), comprising:
a logic die (25, see para. [0046]), wherein a back surface of the logic die (25) is exposed from a top surface of the SOC package (20, see Figure 1); and
a first substrate (21) electrically connected to the logic die (25);
a memory package (40) stacked on the SOC package (20, see Figure 1), comprising:
a second substrate (41) having a top surface and a bottom surface (see Figure 1);
a memory die (45) mounted on the top surface of the second substrate (41) and electrically connected to the second substrate (41) using bonding wires (48, see para. [0050]); and
conductive structures (73U, see manufacturing step of Figure 18, which shows connection part 73U on the bottom surface of the second substrate 41) of the memory package (40) disposed on the bottom surface of the second substrate (41, see Figure 18) and electrically connected to the SOC package (20, through 73B, see Figures 1, 18, and para. [0112]); and
a one-piece, continuous heat spreader (11) partially overlapping the bottom surface of the second substrate (41, see Figure 1), [being in direct contact with the back surface of the logic die or the bottom surface of the second substrate,] and wherein the conductive structures (73U) of the memory package (20) are located outside or exposed from the heat spreader (11, see Figures 1 and 18).
Figure 1 of Kim ‘849 does not disclose the heat spreader being in direct contact with the logic die or the bottom surface of the second substrate, instead there is a thermal interface material (81) between the heat sink and the back surface of the logic die and the bottom surface of the second substrate (see Figure 1).
However, Kim ‘849 discloses in the embodiment of Figure 24 a heat spreader (11, portion 14) in direct contact with a back surface of a logic die (25, see Figure 24).
It would have been obvious to one of ordinary skill in the art to incorporate the teachings of the embodiment of Figure 24 of Kim ‘849 into the embodiment of Figure 1 of Kim ‘849 to include the heat spreader directly contacting the logic die for the purpose of increased transferring of heat from the logic die to the heat spreader (Kim ‘774, para. [0106]).
Regarding claim 15, Kim ‘849 discloses wherein the heat spreader (11) is disposed between the SOC package (20) and the memory package (40, see Figure 1).
Regarding claim 16, Kim ‘849 discloses wherein the heat spreader (11) fully covers the back surface of the logic die (25, see Figure 1).
Regarding claim 17, Kim ‘849 discloses wherein the heat spreader (11) is wrapped around the SOC package (20) or the memory package (40, see Figure 1 which shows the heat spreader 11 wrapped around the left side of the memory package 40).
Regarding claim 18, Kim ‘849 discloses wherein the heat spreader is wrapped around the memory package and covers portions of a top surface and side surfaces of the memory package.
Kim ‘849 discloses wherein the heat spreader (11) is wrapped around the memory package (40, Figure 1 shows the heat spreader 11 wrapped around the left side of the memory package 40) and covers portions of a top surface and side surfaces of the memory package (40, Figure 1 shows the heat spreader fully covering the top surface and the left side surface combined, which are portions of the top surface and side surfaces of the memory package 40).
Regarding claim 19, Kim ‘849 discloses wherein the heat spreader (11) is wrapped around the memory package (40) and fully covers a top surface and side surfaces of the memory package (40, the heat spreader fully covers the top surface and the left side surface of the package 40, see Figure 1).
Regarding claim 20, Kim ‘849 discloses wherein the heat spreader (11) is wrapped around side surfaces of the SOC package (20, top surfaces are considered side surfaces of the SOC package) and partially covers a top surface of the SOC package (20, see Figure 1).
Regarding claim 21, Figure 24 of Kim ‘849 further discloses an underfill (81D, while disclosed as a thermal interface material, the material may include a curable resin, see para. [0059], which is known in the art as a common material for an underfill material, thus the thermal interface material 81D may be considered as an underfill) filling a gap between the SOC package (20) and the memory package (40, see Figure 24), wherein the heat spreader (11) is adjacent to the underfill (81D, see Figure 24).
Regarding claim 22, Figure 24 of Kim ‘849 discloses wherein the heat spreader (11) is between the underfill (81D) and the back surface of the logic die (25, see Figure 24).
Regarding claim 23, Kim ‘849 discloses wherein the SOC package (20) comprises:
a molding compound (29) surrounding the logic die (25), being in contact with the first substrate (21) and the logic die (25, see Figure 1); and
first conductive structures (73B, see manufacturing step of Figure 18, which shows the bottom part 73B of the structures 73 before joining together) passing through the molding compound (29) and electrically connected to the memory package (40, through 73U), wherein the first conductive structures (73B) of the SOC package (20) are separated from the heat spreader (11, see Figure 1).
Claims 11 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over embodiments of Kim ‘849 and Kim ‘774 as applied to claims 10 and 23, respectively, above, and further in view of Chang et al. (“Chang” US 2022/0028842) in view of Lee et al. (“Lee” US 2015/0125993).
Regarding claim 11, Kim ‘849 does not disclose an underfill surrounding the conductive structures of the memory package.
Chang discloses in Figure 14A, however, conductive structures (152) of the memory package (200) are surrounded by an underfill (250) between the SOC package (100) and the memory package (200, see Figure 14A).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chang into the teachings of Kim ‘849 to include the underfill surrounding the conductive structures of the memory package for the purpose of insulating conductive terminals from one another and firmly fixing the conductive terminals by the underfill material (Lee, para. [0059]).
Regarding claim 24, Kim ‘849 discloses wherein the conductive structures (73U) of the memory package (40) are [surrounded by an underfill and] electrically connected to the first conductive structures (73B) of the SOC package (20), and wherein the conductive structures (73U) of the memory package (40) are separated from the heat spreader (11, see Figures 1 and 18).
Kim ‘849 does not disclose an underfill surrounding the conductive structures of the memory package.
Chang discloses in Figure 14A, however, conductive structures (152) of the memory package (200) are surrounded by an underfill (250) between the SOC package (100) and the memory package (200, see Figure 14A).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Chang into the teachings of Kim ‘849 to include the underfill surrounding the conductive structures of the memory package for the purpose of insulating conductive terminals from one another and firmly fixing the conductive terminals by the underfill material (Lee, para. [0059]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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