Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Reference character 252 in Figs. 10 and 14 is not described in the specification.
In reply to the above drawing objection, applicant replied on 12/23/2025 that Figs. 10 and 14 have been amended and replacement sheets have been submitted. However, no replacement drawings have been submitted.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 2020/0295003 A1, of record), and further in view of Tsai et al. (US 2019/0140105 A1, of record).
Re Claim 1, Dewey teaches a stacked semiconductor device comprising:
a lower transistor (130-1, Figs. 1A-1B, para [0018]) comprising a fin channel (106-1, Figs. 1A-1B, para [0020]), a lower source/drain (S/D) region (118-1, Fig. 1B, para [0021]) that contacts an end surface of the fin channel (see Fig. 1A), and a lower gate structure (124-1+122-1, Fig. 1A, paras [0023] – [0024], also see annotated Fig. 1A below) that contacts a sidewall of the fin channel (see Fig. 1A);
an upper transistor (130-2, Figs. 1A-1B, para [0018]) stacked vertically above the lower transistor (130-1), the upper transistor (130-2) comprising a nano channel (106-2, Figs. 1A-1B, para [0020]), an upper S/D region (118-2, Fig. 1B, para [0021]) that contacts an end surface of the nano channel (see Fig. 1B), and an upper gate structure (124-2+122-2, Fig. 1A, paras [0023] – [0024], also see annotated Fig. 1A below) that wraps around and contacts the nano channel (106-2, see Fig. 1A).
and an S/D insulator (120, Fig. 1B, para [0021]) formed within a lower portion of an S/D recess (S/D recess 148, compare Figs. 1B and 7B, para [0035]) and upon the lower S/D region (118-1, Fig. 1B).
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Dewey is silent about the nano channel of the upper transistor being diamond-shaped.
In a related semiconductor art, Tsai teaches a diamond-shaped nanochannel (162, Fig. 2F, para [0073]) which is formed by forming an additional layer 160 (Fig. 2F, para [0074]) around the original nanowire 158 (Fig. 2F, para [0074]). The diamond-shaped nanochannel (162) is better than just having the nanowire (158) because the current flowing through the diamond-shaped nanochannel (162) under a given voltage is increased and the drain-induced barrier lowering issue is reduced (para [0074]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the nanochannels (106-2) of Dewey during the channel formation stage (Fig. 14A, Dewey), so that the channels are diamond-shaped as disclosed by Tsai because the current flowing through the diamond-shaped nanochannel under a given voltage is increased and the drain-induced barrier lowering issue is reduced (para [0074], Tsai).
Re Claim 10, Dewey teaches a stacked semiconductor device comprising:
a lower transistor (130-1, Figs. 1A-1B, para [0018]) comprising a fin channel (106-1, Figs. 1A-1B, para [0020]), a lower source (marked “118-1S” in annotated Fig. 1B below, para [0021]) that contacts an end surface of the fin channel (106-1, see annotated Fig. 1B below), a lower drain (marked “118-1D” in annotated Fig. 1B below, para [0021]) that contacts a distal end surface of the fin channel (106-1, see annotated Fig. 1B below), and lower gate (124-1+122-1, Fig. 1A, paras [0023] – [0024], also see annotated Fig. 1A above) that contacts a sidewall of the fin channel (106-1);
an upper transistor (130-2, Figs. 1A-1B, para [0018]) stacked vertically above the lower transistor (130-1), the upper transistor (130-2) comprising a nano channel (106-2, Figs. 1A-1B, para [0020]), an upper source (marked “118-2S” in annotated Fig. 1B below, para [0021]) that contacts an end surface of the nano channel (106-2, see annotated Fig. 1B below), an upper drain (marked “118-2D” in annotated Fig. 1B below, para [0021]) that contacts a distal end surface of the nano channel (106-2, see annotated Fig. 1B below), and an upper gate (124-2+122-2, Fig. 1A, paras [0023] – [0024], also see annotated Fig. 1A above) that wraps around and contacts a perimeter of the nano channel (106-2, see Fig. 1A); and
one or more source/drain (S/D) insulators (120, Fig. 1B, para [0021]) formed within lower portions of one or more S/D recesses (S/D recesses 148, compare Figs. 1B and 7B, para [0035]) and upon one of the lower source (“118-1S”) and the lower drain (“118-1D”).
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Dewey is silent about the nano channel of the upper transistor being diamond-shaped.
In a related semiconductor art, Tsai teaches a diamond-shaped nanochannel (162, Fig. 2F, para [0073]) which is formed by forming an additional layer 160 (Fig. 2F, para [0074]) around the original nanowire 158 (Fig. 2F, para [0074]). The diamond-shaped nanochannel (162) is better than just having the nanowire (158) because the current flowing through the diamond-shaped nanochannel (162) under a given voltage is increased and the drain-induced barrier lowering issue is reduced (para [0074]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the nanochannels (106-2) of Dewey during the channel formation stage (Fig. 14A, Dewey), so that the channels are diamond-shaped as disclosed by Tsai because the current flowing through the diamond-shaped nanochannel under a given voltage is increased and the drain-induced barrier lowering issue is reduced (para [0074], Tsai).
Re Claim 19, Dewey teaches a stacked semiconductor device fabrication method comprising:
forming a fin channel (106-1, Figs. 1A-1B, para [0020]) of a lower transistor (130-1, Figs. 1A-1B, para [0018]);
forming a lower gate structure (124-1+122-1, Fig. 1A, paras [0023] – [0024], also see annotated Fig. 1A above) of the lower transistor (130-1) upon a sidewall of the fin channel (160-1, see Figs. 1A-1B);
forming a lower source/drain (S/D) region (118-1, Fig. 1B, para [0021]) of the lower transistor (130-1);
forming an S/D insulator (120, Fig. 1B, para [0021]) within a lower portion of a S/D recess (S/D recess 148, compare Figs. 1B and 7B, para [0035]) and upon the lower S/D region (118-1);
forming a channel (106-2, Figs. 1A-1B, para [0020]) of an upper transistor (130-2, Figs. 1A-1B, para [0018]) that is vertically stacked above the lower transistor (130-1, see Figs. 1A-1B); and
forming an upper gate structure (124-2+122-2, Fig. 1A, paras [0023] – [0024], also see annotated Fig. 1A above) of the upper transistor (130-2) upon and around the channel (106-2, see Fig. 1A).
Dewey is silent about the channel of the upper transistor being diamond-shaped.
In a related semiconductor art, Tsai teaches a diamond-shaped nanochannel (162, Fig. 2F, para [0073]) which is formed by forming an additional layer 160 (Fig. 2F, para [0074]) around the original nanowire 158 (Fig. 2F, para [0074]). The diamond-shaped nanochannel (162) is better than just having the nanowire (158) because the current flowing through the diamond-shaped nanochannel (162) under a given voltage is increased and the drain-induced barrier lowering issue is reduced (para [0074]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the nanochannels (106-2) of Dewey during the channel formation stage (Fig. 14A, Dewey), so that the channels are diamond-shaped as disclosed by Tsai because the current flowing through the diamond-shaped nanochannel under a given voltage is increased and the drain-induced barrier lowering issue is reduced (para [0074], Tsai).
Claims 2-3 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 2020/0295003 A1, of record) and Tsai et al. (US 2019/0140105 A1, of record), and further in view of Smith et al. (US 2019/0172755 A1, of record).
Re Claim 2, Dewey modified by Tsai teaches the stacked semiconductor device of claim 1, but does not explicitly state that the lower transistor (118-1) is a p-type fin field-effect transistor (FinFET), and wherein the upper transistor (118-2) is a n-type nanostructure fin field-effect transistor (FET).
However, Dewey discloses that the transistors 118 can be either PMOS or NMOS (para [0022]). In a related semiconductor art, Smith teaches a stacked CMOS (Fig. 3E) where the lower transistor is a PMOS and the upper transistor is NMOS, which form a complimentary FET device and allow for unique processing between the NMOS and PMOS channels (para [0024]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey modified by Tsai, such that the lower transistor is a PMOS and the upper transistor is NMOS as disclosed by Smith, which will form a complimentary FET device and allow for unique processing between the NMOS and PMOS channels (para [0024], Smith).
Re Claim 3, Dewey modified by Tsai and Smith teaches the stacked semiconductor device of claim 2, wherein the fin channel (106-1, Dewey) is a Silicon Germanium (SiGe) fin channel (SiGe fin channel, Fig. 3E, Smith), and wherein the diamond-shaped nano channel (162, Tsai) is a Silicon diamond-shaped nano channel (162 is made of 158 and 160, which can be made of silicon, para [0069], Tsai).
Re Claim 11, Dewey modified by Tsai teaches the stacked semiconductor device of claim 10, but does not explicitly state that the lower transistor (118-1) is a p-type fin field-effect transistor (FinFET), and wherein the upper transistor (118-2) is a n-type nanostructure fin field-effect transistor (FinFET).
However, Dewey discloses that the transistors 118 can be either PMOS or NMOS (para [0022]). In a related semiconductor art, Smith teaches a stacked CMOS (Fig. 3E) where the lower transistor is a PMOS and the upper transistor is NMOS, which form a complimentary FET device and allow for unique processing between the NMOS and PMOS channels (para [0024]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey modified by Tsai, such that the lower transistor is a PMOS and the upper transistor is NMOS as disclosed by Smith, which will form a complimentary FET device and allow for unique processing between the NMOS and PMOS channels (para [0024], Smith).
Re Claim 12, Dewey modified by Tsai and Smith teaches the stacked semiconductor device of claim 11, wherein the fin channel (106-1, Dewey) is a Silicon Germanium (SiGe) fin channel (SiGe fin channel, Fig. 3E, Smith), and wherein the diamond-shaped nano channel (162, Tsai) is a Silicon diamond-shaped nano channel (162 is made of 158 and 160, which can be made of silicon, para [0069], Tsai).
Claims 4-6, 8-9 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 2020/0295003 A1, of record), Tsai et al. (US 2019/0140105 A1, of record), and Smith et al. (US 2019/0172755 A1, of record), and further in view of Gardner et al. (US 2023/0056372 A1, of record).
Re Claim 4, Dewey modified by Tsai and Smith teaches the stacked semiconductor device of claim 3, further comprising:
a dielectric isolation region comprising a middle-dielectric isolation (MDI) layer (116, Fig. 1B, para [0024], Dewey).
Dewey does not disclose a lower bottom-dielectric isolation (BDI) layer.
However, in a related semiconductor art, Gardner discloses a bottom-dielectric isolation layer (marked “131-1” in annotated Fig. 1B below, para [0058]) which will provide electrical isolation between the substrate (101, Fig. 1B, para [0051]) and the lower transistor (110A, Fig. 1B, para [0051]) and prevent any diffusion of dopants or charge carriers.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey modified by Tsai and Smith, such that a bottom dielectric isolation layer is formed as disclosed by Gardner, which will provide electrical isolation between the substrate and the lower transistor, and prevent any diffusion of dopants or charge carriers.
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Re Claim 5, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 4, wherein the MDI layer (116, Fig. 1B, Dewey) is directly disposed upon a top surface of the fin channel (106-1, see Fig. 1B, Dewey).
Re Claim 6, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 5, but does not disclose a gate insulator between the lower gate structure and the upper gate structure.
However, Gardner teaches a gate isolation structure (137, Fig. 1C, para [0058]) which separates the lower gate (113, which is made of gate metal 114 and gate dielectric 112, paras [0052] and [0054]) and the upper gate (123, which is made of gate metal 124 and gate dielectric 122, paras [0052] and [0054]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey modified by Tsai, Smith and Gardner, such that a gate insulator is formed between the lower gate structure and the upper gate structure as disclosed by Gardner. The gate insulator will isolate the upper and lower gate structures and thus they can be operated independently, providing more control of the transistor stack.
Re Claim 8, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 4, wherein the lower S/D region (118-1, Fig. 1B, Dewey, similar to 115, Fig. 1B of Gardner) is directly between the lower BDI layer (“131-1”, see annotated Fig. 1B of Gardner above) and the S/D insulator (120, Fig. 1B, Dewey).
Re Claim 9, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 8, wherein the fin channel (106-1, Dewey) comprises a (110) crystalline planar side surface (for PMOS fin channel made of SiGe, one uses the (110) plane to take advantage of the improved carrier transport, para [0026], Dewey) and the diamond-shaped nano channel comprises a (111) crystalline planar diamond-shaped surface (diamond-shaped channels, 162, have (111) crystal planes, para [0080], compare Figs. 2F and 3B, Tsai).
Re Claim 13, Dewey modified by Tsai and Smith teaches the stacked semiconductor device of claim 12, further comprising:
a dielectric isolation region comprising a middle-dielectric isolation (MDI) layer (116, Fig. 1B, para [0024], Dewey).
Dewey does not disclose a lower bottom-dielectric isolation (BDI) layer.
However, in a related semiconductor art, Gardner discloses a bottom-dielectric isolation layer (marked “131-1” in annotated Fig. 1B of Gardner above, para [0058]) which will provide electrical isolation between the substrate (101, Fig. 1B, para [0051]) and the lower transistor (110A, Fig. 1B, para [0051]) and prevent any diffusion of dopants or charge carriers.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey modified by Tsai and Smith, such that a bottom dielectric isolation layer is formed as disclosed by Gardner, which will provide electrical isolation between the substrate and the lower transistor, and prevent any diffusion of dopants or charge carriers.
Re Claim 14, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 13, wherein the MDI layer (116, Fig. 1B, Dewey) is directly formed upon a top surface of the fin channel (106-1, see Fig. 1B, Dewey) and wherein the lower BDI layer (“131-1”, see annotated Fig. 1B of Gardner above) is directly between a bottom surface of the fin channel (106-1, Fig. 1B of Dewey, similar to channel structure 111, Fig. 1B, para [0051] of Gardner) and a substrate (102, Fig. 1B, para [0018] of Dewey, similar to 101, Fig. 1B, para [0051] of Gardner).
Re Claim 15, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 14, but does not disclose a gate insulator between the lower gate structure and the upper gate structure.
However, Gardner teaches a gate isolation structure (137, Fig. 1C, para [0058]) which separates the lower gate (113, which is made of gate metal 114 and gate dielectric 112, paras [0052] and [0054]) and the upper gate (123, which is made of gate metal 124 and gate dielectric 122, paras [0052] and [0054]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey modified by Tsai, Smith and Gardner, such that a gate insulator is formed between the lower gate structure and the upper gate structure as disclosed by Gardner. The gate insulator will isolate the upper and lower gate structures and thus they can be operated independently, providing more control of the transistor stack.
Re Claim 16, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 15, further comprising a first source/drain (S/D) insulator (marked “120-1” in annotated Fig. 1B-v2 below, para [0021], Dewey), from the one or more S/D insulators (120, Fig. 1B, Dewey), between the lower drain (“118-1D”, Dewey) and the upper source (“118-2S”, Dewey) and a second S/D insulator (marked “120-2” in annotated Fig. 1B-v2 below, para [0021], Dewey), from the one or more S/D insulators (120, Fig. 1B, Dewey), between the lower source (“118-1S”, Dewey) and the upper drain (“118-2D”, Dewey).
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Re Claim 17, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 16, wherein the lower source and the lower drain (“118-1S” and “118-1D”, Dewey, similar to S/D regions 115, Fig. 1B of Gardner) are directly upon the lower BDI layer (“131-1”, see annotated Fig. 1B of Gardner).
Re Claim 18, Dewey modified by Tsai, Smith and Gardner teaches the stacked semiconductor device of claim 17, wherein the fin channel (106-1, Dewey) comprises a (110) crystalline planar side surface (for PMOS fin channel made of SiGe, one uses the (110) plane to take advantage of the improved carrier transport, para [0026], Dewey) and the diamond-shaped nano channel comprises a (111) crystalline planar diamond-shaped surface (diamond-shaped channels, 162, have (111) crystal planes, para [0080], compare Figs. 2F and 3B, Tsai).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 2020/0295003 A1, of record) and Tsai et al. (US 2019/0140105 A1, of record) as applied to claim 19 above, and further in view of Gardner et al. (US 2023/0056372 A1, of record).
Re Claim 20, Dewey modified by Tsai teaches the stacked semiconductor device fabrication method of claim 19, and the lower transistor (130-1, Dewey) and the upper transistor (130-2, Dewey) but does not disclose:
forming an electrical isolation structure upon the lower transistor and between the lower transistor and the upper transistor.
However, Gardner teaches a gate isolation structure (137, Fig. 1C, para [0058]) which separates the lower gate (113, which is made of gate metal 114 and gate dielectric 112, paras [0052] and [0054]) and the upper gate (123, which is made of gate metal 124 and gate dielectric 122, paras [0052] and [0054]). The gate isolation structure is formed upon the lower transistor and between the lower and the upper transistor (see Fig. 1C).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the transistor stack of Dewey, such that a gate insulator is formed between the lower gate structure and the upper gate structure as disclosed by Gardner. The gate insulator formed upon the lower transistor and between the lower and the upper transistor, will isolate the upper and lower gate structures, and thus they can be operated independently, providing more control of the transistor stack.
Response to Arguments
Applicant’s arguments with respect to claims 1, 10 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding amended claims 1, 10 and 19, applicant argued that the newly added limitation wherein, “an S/D insulator formed within a lower portion of an S/D recess and upon the lower S/D region”, is not taught by the references of record. The examiner respectfully disagrees with the applicant, since Dewey et al. (US 2020/0295003 A1, of record) clearly shows a S/D recess (S/D recess 148, compare Figs. 1B and 7B, para [0035]) where a S/D insulator (120, Fig. 1B, para [0021]) is formed within a lower portion of the S/D recess (S/D recess 148, compare Figs. 1B and 7B).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898