DETAILED ACTION
This non-final action is responsive to communications: 10/21/2025.
Claims 1-5, and 10 are pending. Claim 1 is independent.
Election/Restrictions
3. Applicant’s election without traverse of claims 1-5, and 10 (Group I) in the reply filed on 10/21/2025 is acknowledged. Claims 6-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/21/2025. Claims 1-5, and 10 are pending in the application.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
4. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
5. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
6. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 7/19/2022, 02/06/2023, and 11/18/2025. All IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1, and 3-5 is/are rejected under 35 U.S.C. 103 as being obvious over Hu (US 2017/0221558 A1), in view of Chih et al. (US 2022/0068378 A1).
Regarding independent claim 1, Hu teaches a high density embedded-artificial synaptic element (Fig. 3B: 300’ “apparatus” which is employed in Fig. 4B crossbar array; see para [0033], para [0035]. See EXAMINER’s MARKUP version of Figure 3B. See also Fig. 1-Fig. 8 for illustrated components, functionality), comprising:
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a semiconductor substrate (Fig. 4B: substrate of crossbar array. see Fig. 1: 130, see base or substrate of “crossbar array”/ memristor array);
a select transistor (Fig. 3B: 316) disposed on the semiconductor substrate (Fig. 4B: substrate of crossbar array) and comprising a first gate structure (Fig. 3B: G1), a drain region (Fig. 3B: D) and a source region (Fig. 3B: S),
wherein the drain region (Fig. 3B: D) and the source region (Fig. 3B: S) are located on two opposite sides of the first gate structure (Fig. 3B: G. See Fig. 3B arrangement), respectively;
a metal layer (Fig. 3B: Vx wire generally fabricated from metal layer) electrically connected to the drain region (Fig. 3B: D) of the select transistor (Fig. 3B: 316); and
a memory transistor (Fig. 3B: 306) disposed on the semiconductor substrate (Fig. 4B: substrate of crossbar array) and coplanar with the select transistor (see Fig. 3B, Fig. 4B, Fig. 1: 130: crossbar array “apparatus” are located on Fig. 1: 130),
wherein the memory transistor (Fig. 3B: 306) comprises a second gate structure (Fig. 3B: G2), a first electrode region (Fig. 3B: 314 electrode), a second electrode region (Fig. 3B: 310 electrode), a first memristor (Fig. 3B: 304 “memristor B”) and a second memristor (Fig. 3B: 302 “memristor A”),
the second gate structure (Fig. 3B: G2) is electrically connected to the metal layer (Fig. 3B: Vx),
the first memristor (Fig. 3B: 304 “memristor B”) is formed between the second gate structure (Fig. 3B: G2) and the first electrode region (Fig. 3B: 314 electrode), and
the second memristor (Fig. 3B: 302 “memristor A”) is formed between the second gate structure (Fig. 3B: G2) and the second electrode region (Fig. 3B: 310 electrode).
Hu is silent with respect to a memory transistor disposed on the semiconductor substrate and coplanar with the select transistor.
Chih teaches a select transistor (Fig. 6A: 630A) disposed on the semiconductor substrate (Fig. 6A: 610) and comprising a first gate structure (Fig. 6A: SG), a drain region (Fig. 6A: 620B) and a source region (Fig. 6A: 620A), wherein the drain region and the source region are located on two opposite sides of the first gate structure (see Fig. 6A: transistor layout), respectively; a metal layer (Fig. 6A: 680) electrically connected to the drain region of the select transistor;
a memory transistor (Fig. 6A: 630B transistor with programmable resistors) disposed on the semiconductor substrate (Fig. 6A: 610) and coplanar (see Fig. 6A arrangement) with the select transistor (Fig. 6A: 630A. See para [0040], para [0041]).
Hu and Chih are in analogous field of art since they are in the same field of endeavor of integration mechanism of memory cells including select transistor and memory transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Chih’s transistor layout and fabrication teachings into the apparatus of Hu such that memory transistor coplanar with the select transistor can be fabricated on the substrate in order to simplify manufacturing "…allowing the memory cell to be formed in a compact manner through a simplified the fabrication process...." (Chih Abstract, para [0024]).
Regarding claim 3, Hu and Chih teach the high density embedded-artificial synaptic element of claim 1. Chih teaches wherein the first gate structure comprises: a gate electrode (Fig. 6A: SG); and a spacer surrounding the gate electrode (Fig. 6A: spacer shown on two sides of SG), wherein the drain region and the source region are aligned with the spacer on two opposite sides of the gate electrode (See Fig. 6A arrangement of drain, source of transistor 630A).
Regarding claim 4, Hu and Chih teach the high density embedded-artificial synaptic element of claim 1. Chih teaches further comprising: a shallow trench isolation region (Fig. 6A: 650A STI) disposed on the semiconductor substrate (Fig. 6A: 610) and located between the drain region of the select transistor (Fig. 6A: 620B) and the first electrode region of the memory transistor (Fig. 6A: storage node).
Regarding claim 5, Hu and Chih teach the high density embedded-artificial synaptic element of claim 1. Chih teaches further comprising: a first contact (Fig. 6A: tall contact connected to 620B and M1) connected between the metal layer (Fig. 6A: 680) and the drain region of the select transistor (Fig. 6A: 620B); and
a second contact (see Fig. 6A: contact shown above CG) connected (operably connected and physically located) between the metal layer (Fig. 6A: 680) and the second gate structure of the memory transistor (Fig. 6A: CG with 630B);
wherein a length of the first contact is greater than a length of the second contact (See Fig. 6A dimensions shown. This is also known to ordinary skill in the art).
11. Claim 2 is/are rejected under 35 U.S.C. 103 as being obvious over Hu (US 2017/0221558 A1) and Chih et al. (US 2022/0068378 A1), in view of Ramkumar et al. (US 20200350213 A1).
Regarding claim 2, Hu and Chih teach the high density embedded-artificial synaptic element of claim 1. Hu and Chih are silent with respect to select transistor being a High-K Metal Gate (HKMG) N-type field effect transistor.
Ramkumar teaches the select transistor (Fig. 1A: 96) is a High-K Metal Gate (HKMG) N-type field effect transistor (para [0017], para [0006], abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Ramkumar’s HKMG n-type select transistor into the apparatus of Hu and Chih such that select transistor with HKMG process can be employed to reduce overall cell leakage.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
KING (US 20230292533 A1): claims applicable for ODP double patenting rejection and this area will be revisited in the future.
LI (US 10847224 B1): Fig. 1-Fig. 9 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art of record does not appear to teach, suggest, or provide motivation for combination for
“…the second electrode region of the memory transistor of each of the high density embedded-artificial synaptic elements arranged in row is coupled to a second electrode line; and a plurality of diodes, wherein each of the diodes is coupled to the two metal layers of each two of the high density embedded-artificial synaptic elements adjacent to each other in a vertical direction, each of the diodes has an anode end, and the anode ends of the diodes arranged in row are connected to each other and gather an output current; wherein each of the diodes determines whether to conduct or not according to the two output voltages of the two metal layers of each two of the high density embedded-artificial synaptic elements adjacent to each other in the vertical direction…”
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825