Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 1-2, 4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (JP 2019096774) in further view of Dasgupta (PGPub No. 20180219087), and Yoshimi (US Patent No. 5698869).
Regarding claim 1, Yoshida teaches a semiconductor device comprising: a substrate including a first main surface (Fig. 1 and [0011] point to a high-electron-mobility transistor (HEMT) including a substrate 10.); a semiconductor layer provided on the first main surface of the substrate (Id.; see nitride-semiconductor layer 18.), the semiconductor layer including an electron transport layer provided on the substrate (Id.; see channel layer 12.), the electron transport layer including a first upper surface, an electron supply layer provided on the electron transport layer (Id.; see barrier layer (electron supply layer) 13.), a source region containing a first electrically conductive impurity, the source region being provided in a first opening, and a drain region containing the first electrically conductive impurity, the drain region being provided in a second opening (Fig. 1 and [0017] point to high-concentration regions 15 (source region) and 16 (drain region), which both have an impurity concentration (first electrically conductive impurity).); an electrically insulating layer provided on the semiconductor layer (Fig. 1 and [0011] point to a SiN layer 21.); a source electrode and a drain electrode, each of the source electrode and the drain electrode being provided on the semiconductor layer, the source electrode being provided on the source region, and the drain electrode being provided on the drain region (Id.; see source electrode 31 and drain electrode 32, located on regions 15 and 16 respectively.); and a gate electrode provided on the electrically insulating layer (Id.; see gate electrode 33.), wherein the first opening and the second opening are each formed in the electron supply layer and the electron transport layer (Fig. 1 and [0016] point to recesses 18a and 18b extending through the electron supply layer 13 and into the channel (electron transport) layer 12.), the first opening having a first edge toward the second opening, the second opening having a second edge toward the first opening (Id.; both recesses 18a and 18b include a sidewalls/edge that faces the other.), a bottom of the first opening and a bottom of the second opening are positioned lower than the first upper surface, so as to be toward the substrate (Id.; see recesses 18a/18b and channel layer 12.), a third opening connected to the first opening, and a fourth opening connected to the second opening are each formed in the electrically insulating layer (Fig. 1 and [0019] point to openings 21a and 21b provided in the SiN layer 21.), the third opening having a third edge toward the fourth opening, and the fourth opening having a fourth edge toward the third opening (Id.; both openings 21a and 21b include a sidewall/edge that faces the other.), a portion of the source region overlaps the electrically insulating layer (Fig. 1 points to a portion of the high concentration (source) region 15 overlapping the SiN (electrically insulating) layer 21.), and a portion of the drain region overlaps the electrically insulating layer (Id.; see high concentration (drain) region 16 and SiN (electrically insulating) layer 21.), wherein a portion of an upper surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of an upper surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer (Fig. 1 points to both high concentration regions 15 (source region) and 16 (drain region) having upper surfaces extend through the lower surface of the SiN layer (electrically insulating layer) 21.).
Yoshida fails to teach in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is, the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is, and the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge, and a second layer portion that spans the second opening from the second edge to the fourth edge.
Dasgupta teaches in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is (Fig. 1A and [0035] point to an epitaxial island 115 with an overhang length of L2. The innermost point of L2, which meets with L1, is interpreted to mean the same as “the first edge of the first opening”, while the outermost point of L2, i.e., the outer edge of peripheral region 120, is interpreted to mean the same as “the third edge of the third opening”.), and the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is (Id.; the innermost point of L2, which meets with L1, is interpreted to also mean the same as “the second edge of the second opening”, while the outermost point of L2, i.e., the outer edge of peripheral region 120, is interpreted to also mean the same as “the fourth edge of the fourth opening”.). Dasgupta is considered analogous to the claimed invention due to Dasgupta disclosing the growth of III-N semiconductor heterostructures on said epitaxial island(s) 115, such as HEMTs and MOS HEMTs (Figs. 4A-4C; [0002]). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yoshida and Dasgupta, such that the first and second openings extend further inward towards each other and partially undercut the existing structure in order to lower the resistance between the source and drain regions and by extension enhance their performance.
Yoshida in further view of Dasgupta still fails to teach the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge, and a second layer portion that spans the second opening from the second edge to the fourth edge.
Yoshimi teaches the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge (Fig. 4A points to an insulated-gate transistor comprising a gate electrode 205 formed on a second insulating film/gate oxide film 204 (insulating layer), with said film 204 spanning leftward (first layer portion) from an inner edge (first edge), defined by a SOI film 203 and a n+ source region 206, to an outer edge (third edge), defined by said n+ source region 206 and a SixGe1-x layer 207.), and a second layer portion that spans the second opening from the second edge to the fourth edge (Id. points to the same second insulating film/gate oxide film 204 (insulating layer) spanning rightward (second layer portion) from an inner edge (second edge), defined by a SOI film 203 and a n+ source region 206, to an outer edge (fourth edge), defined by said n+ source region 206 and a SixGe1-x layer 207.). Thus, it would have been obvious to combine the teachings of Yoshida et al. and Yoshimi, such that the insulating layer extends outwards over the undercut openings in order to provide protection to the gate electrode while still allowing control of the electric current flowing through the source and drain regions.
Regarding claim 2, Dasgupta teaches wherein in the plan view viewed in the direction perpendicular to the first main surface, a distance between the first edge and the third edge is greater than or equal to 0.2 µm and less than or equal to 1.5 µm, and a distance between the second edge and the fourth edge is greater than or equal to 0.2 µm and less than or equal to 1.5 µm. Specifically, Dasgupta teaches an embodiment of a semiconductor heterostructure where the overhang length L2 (“a distance between the first edge and the third edge”; “a distance between the second edge and the fourth edge”) is at least 500nm, or 0.5µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to combine the teachings of Yoshida and Dasgupta, such that the distances between the first and third edges and the second and fourth edges, respectively, is such that the performances of the source and drain regions is maximized such that the stability of the overall structure is not impaired.
Regarding claim 4, Yoshida teaches wherein the gate electrode is in Schottky contact with the semiconductor layer (Fig. 1 and [0020] point to the gate electrode 33 being in Schottky contact with the semiconductor layer 18.).
Regarding claim 8, Yoshida teaches a semiconductor device comprising: a substrate including a first main surface (Fig. 1 and [0011] point to a high-electron-mobility transistor (HEMT) including a substrate 10.); a semiconductor layer provided on the first main surface of the substrate (Id.; see nitride-semiconductor layer 18.), the semiconductor layer including an electron transport layer provided on the substrate (Id.; see channel layer 12.), the electron transport layer including a first upper surface, an electron supply layer provided on the electron transport layer (Id.; see barrier layer (electron supply layer) 13.), a source region containing a first electrically conductive impurity, the source region being provided in a first opening, and a drain region containing the first electrically conductive impurity, the drain region being provided in a second opening (Fig. 1 and [0017] point to high-concentration regions 15 (source region) and 16 (drain region), which both have an impurity concentration (first electrically conductive impurity).); an electrically insulating layer provided on the semiconductor layer (Fig. 1 and [0011] point to a SiN layer 21.); a source electrode and a drain electrode, each of the source electrode and the drain electrode being provided on the semiconductor layer, the source electrode being provided on the source region, and the drain electrode being provided on the drain region (Id.; see source electrode 31 and drain electrode 32, located on regions 15 and 16 respectively.); and a gate electrode provided on the electrically insulating layer (Id.; see gate electrode 33.), wherein the first opening and the second opening are each formed in the electron supply layer and the electron transport layer (Fig. 1 and [0016] point to recesses 18a and 18b extending through the electron supply layer 13 and into the channel (electron transport) layer 12.), the first opening having a first edge toward the second opening, the second opening having a second edge toward the first opening (Id.; both recesses 18a and 18b include a sidewalls/edge that faces the other.), a bottom of the first opening and a bottom of the second opening are positioned lower than the first upper surface, so as to be toward the substrate (Id.; see recesses 18a/18b and channel layer 12.), a third opening connected to the first opening, and a fourth opening connected to the second opening are each formed in the electrically insulating layer (Fig. 1 and [0019] point to openings 21a and 21b provided in the SiN layer 21.), the third opening having a third edge toward the fourth opening, and the fourth opening having a fourth edge toward the third opening (Id.; both openings 21a and 21b include a sidewall/edge that faces the other.),a portion of the source region overlaps the electrically insulating layer (Fig. 1 points to a portion of the high concentration (source) region 15 overlapping the SiN (electrically insulating) layer 21.), and a portion of the drain region overlaps the electrically insulating layer (Id.; see high concentration (drain) region 16 and SiN (electrically insulating) layer 21), wherein a portion of a horizontal upper surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of a horizontal upper surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer (Fig. 1 points to both high concentration regions 15 (source region) and 16 (drain region) having upper surfaces extend through the lower surface of the SiN layer (electrically insulating layer) 21.).
Yoshida fails to teach in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is, the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is, and the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge, and a second layer portion that spans the second opening from the second edge to the fourth edge.
Dasgupta teaches in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is (Fig. 1A and [0035] point to an epitaxial island 115 with an overhang length of L2. The innermost point of L2, which meets with L1, is interpreted to mean the same as “the first edge of the first opening”, while the outermost point of L2, i.e., the outer edge of peripheral region 120, is interpreted to mean the same as “the third edge of the third opening”.), and the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is (Id.; the innermost point of L2, which meets with L1, is interpreted to also mean the same as “the second edge of the second opening”, while the outermost point of L2, i.e., the outer edge of peripheral region 120, is interpreted to also mean the same as “the fourth edge of the fourth opening”.). Dasgupta is considered analogous to the claimed invention due to Dasgupta disclosing the growth of III-N semiconductor heterostructures on said epitaxial island(s) 115, such as HEMTs and MOS HEMTs (Figs. 4A-4C; [0002]). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yoshida and Dasgupta, such that the first and second openings extend further inward towards each other and partially undercut the existing structure in order to lower the resistance between the source and drain regions and by extension enhance their performance.
Yoshida in further view of Dasgupta still fails to teach the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge, and a second layer portion that spans the second opening from the second edge to the fourth edge.
Yoshimi teaches the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge (Fig. 4A points to an insulated-gate transistor comprising a gate electrode 205 formed on a second insulating film/gate oxide film 204 (insulating layer), with said film 204 spanning leftward (first layer portion) from an inner edge (first edge), defined by a SOI film 203 and a n+ source region 206, to an outer edge (third edge), defined by said n+ source region 206 and a SixGe1-x layer 207.), and a second layer portion that spans the second opening from the second edge to the fourth edge (Id. points to the same second insulating film/gate oxide film 204 (insulating layer) spanning rightward (second layer portion) from an inner edge (second edge), defined by a SOI film 203 and a n+ source region 206, to an outer edge (fourth edge), defined by said n+ source region 206 and a SixGe1-x layer 207.). Thus, it would have been obvious to combine the teachings of Yoshida et al. and Yoshimi, such that the insulating layer extends outwards over the undercut openings in order to provide protection to the gate electrode while still allowing control of the electric current flowing through the source and drain regions.
Response to Arguments
Applicant's arguments filed 01/07/2026 have been fully considered but they are not persuasive. Specifically, Applicant argues 1) that reference Yoshida fails to teach “wherein a portion of an upper surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of an upper surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer” as previously rejected in claim 3 and now added into amended claim 1, and 2) no motivation exists to combine references Yoshida, Dasgupta, and Yoshimi.
Regarding the first argument, Examiner argues that Applicant has incorrectly applied a narrow interpretation to a broad term. Specifically, the term “an upper surface” as used in the claimed invention appears to have been interpreted by the Applicant to mean the topmost surfaces of the concentration regions 15 and 16 as shown in the annotated Fig. 1 of Yoshida provided (see pg. 2 of Remarks). However, Applicant’s argument appears to mistake “an upper surface” with “an uppermost surface”, as the term “upper” as used here is more broadly defined as any surface that is situated above another surface of the respective concentration region. For example, the horizontal surface(s) as indicated below are each considered “an upper surface” as each is located above the lower surface(s) that also make up regions 15/16:
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Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection.
Regarding the second argument, Examiner argues that Applicant is presenting a piecemeal analysis. Specifically, Applicant argues that the none of the references Yoshida, Dasgupta, and Yoshimi teach a physical barrier (mask) that physically suppresses abnormal upward growth, as enabled by the features of claim 1. However, Applicant is reminded that it is the combination of all three references that was used to teach the structure presented in claim 1 and as such, it is said combination that would teach this feature. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Since the combination of references teaches the same structure as described in claim 1, it also teaches the same features that would occur, such as the physical suppression of abnormal upward growth as mentioned in [0033] in the claimed invention. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899