Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 1-2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (JP 2019096774) in further view of Dasgupta (PGPub No. 20180219087), Yoshimi (US Patent No. 5698869), and Nakata (PGPub No. 20170092747).
Regarding claim 1, Yoshida teaches a semiconductor device comprising: a substrate including a first main surface (Fig. 1 and [0011] point to a high-electron-mobility transistor (HEMT) including a substrate 10.); a semiconductor layer provided on the first main surface of the substrate (Id.; see nitride-semiconductor layer 18.), the semiconductor layer including an electron transport layer provided on the substrate (Id.; see channel layer 12.), the electron transport layer including a first upper surface, an electron supply layer provided on the electron transport layer (Id.; see barrier layer (electron supply layer) 13.), a source region containing a first electrically conductive impurity, the source region being provided in a first opening, and a drain region containing the first electrically conductive impurity, the drain region being provided in a second opening (Fig. 1 and [0017] point to high-concentration regions 15 (source region) and 16 (drain region), which both have an impurity concentration (first electrically conductive impurity).); an electrically insulating layer provided on the semiconductor layer (Fig. 1 and [0011] point to a SiN layer 21.); a source electrode and a drain electrode, each of the source electrode and the drain electrode being provided on the semiconductor layer, the source electrode being provided on the source region, and the drain electrode being provided on the drain region (Id.; see source electrode 31 and drain electrode 32, located on regions 15 and 16 respectively.); and a gate electrode provided on the electrically insulating layer (Id.; see gate electrode 33.), wherein the first opening and the second opening are each formed in the electron supply layer and the electron transport layer (Fig. 1 and [0016] point to recesses 18a and 18b extending through the electron supply layer 13 and into the channel (electron transport) layer 12.), the first opening having a first edge toward the second opening, the second opening having a second edge toward the first opening (Id.; both recesses 18a and 18b include a sidewalls/edge that faces the other.), a bottom of the first opening and a bottom of the second opening are positioned lower than the first upper surface, so as to be toward the substrate (Id.; see recesses 18a/18b and channel layer 12.), a third opening connected to the first opening, and a fourth opening connected to the second opening are each formed in the electrically insulating layer (Fig. 1 and [0019] point to openings 21a and 21b provided in the SiN layer 21.), the third opening having a third edge toward the fourth opening, and the fourth opening having a fourth edge toward the third opening (Id.; both openings 21a and 21b include a sidewall/edge that faces the other.), a portion of the source region overlaps the electrically insulating layer (Fig. 1 points to a portion of the high concentration region 15 (source region) overlapping the SiN (electrically insulating) layer 21.), and a portion of the drain region overlaps the electrically insulating layer (Id.; see high concentration region 16 (drain region) and SiN (electrically insulating) layer 21.), and wherein each of the source region in the first opening of the semiconductor layer and the drain region in the second opening of the semiconductor layer is an epitaxial regrowth layer in contact with side wall surfaces of the electron transport layer and the electron supply layer, the epitaxial regrowth layer being formed on the electron transport layer or the substrate as a base (Fig. 4B and [0031] points to a regrowth step by which the high concentration regions 15 (source region) and 16 (drain region) are epitaxially grown on the recessed portions 18a and 18b of the channel layer 12 (electron transport layer) such that the sidewalls of both regions are in contact with surfaces of the channel layer 12 and the barrier layer 13 (electron supply layer).).
Yoshida fails to teach in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is, the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is, wherein a portion of an uppermost surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of an uppermost surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer, and the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge, and a second layer portion that spans the second opening from the second edge to the fourth edge.
Dasgupta teaches in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is (Fig. 1A and [0035] point to an epitaxial island 115 with an overhang length of L2. The innermost point of L2, which meets with L1, is interpreted to mean the same as “the first edge of the first opening”, while the outermost point of L2, i.e., the outer edge of peripheral region 120, is interpreted to mean the same as “the third edge of the third opening”.), and the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is (Id.; the innermost point of L2, which meets with L1, is interpreted to also mean the same as “the second edge of the second opening”, while the outermost point of L2, i.e., the outer edge of peripheral region 120, is interpreted to also mean the same as “the fourth edge of the fourth opening”.). Dasgupta is considered analogous to the claimed invention due to Dasgupta disclosing the growth of III-N semiconductor heterostructures on said epitaxial island(s) 115, such as HEMTs and MOS HEMTs (Figs. 4A-4C; [0002]). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Yoshida and Dasgupta, such that the first and second openings extend further inward towards each other and partially undercut the existing structure in order to lower the resistance between the source and drain regions and by extension enhance their performance.
Yoshida et al. still fails to teach the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge, and a second layer portion that spans the second opening from the second edge to the fourth edge, and wherein a portion of an uppermost surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of an uppermost surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer.
Yoshimi teaches the insulating layer includes a first layer portion that spans the first opening from the first edge to the third edge (Fig. 4A points to an insulated-gate transistor comprising a gate electrode 205 formed on a second insulating film/gate oxide film 204 (insulating layer), with said film 204 spanning leftward (first layer portion) from an inner edge (first edge), defined by a SOI film 203 and a n+ source region 206, to an outer edge (third edge), defined by said n+ source region 206 and a SixGe1-x layer 207.), and a second layer portion that spans the second opening from the second edge to the fourth edge (Id. points to the same second insulating film/gate oxide film 204 (insulating layer) spanning rightward (second layer portion) from an inner edge (second edge), defined by a SOI film 203 and a n+ source region 206, to an outer edge (fourth edge), defined by said n+ source region 206 and a SixGe1-x layer 207.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yoshida et al. and Yoshimi, such that the insulating layer extends outwards over the undercut openings in order to provide protection to the gate electrode while still allowing control of the electric current flowing through the source and drain regions.
Yoshida et al. still fails to teach wherein a portion of an uppermost surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of an uppermost surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer.
Nakata teaches wherein a portion of an uppermost surface of the source region is in contact with a portion of a lower surface of the electrically insulating layer, and a portion of an uppermost surface of the drain region is in contact with another portion of the lower surface of the electrically insulating layer (Fig. 1 points to a HEMT 1A comprising a n-type region 16a (source region), a n-type region 16b (drain region), and a passivation layer 41 (electrically insulating layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yoshida et al. and Nakata, such that the electrically insulating layer is formed to have portions of its lower surface(s) in contact with the uppermost surfaces of the source and drain regions respectively in order to cover at least a portion of the exposed surfaces of each region and prevent any externally-based reactions such as corrosion.
Regarding claim 2, Dasgupta teaches wherein in the plan view viewed in the direction perpendicular to the first main surface, a distance between the first edge and the third edge is greater than or equal to 0.2 µm and less than or equal to 1.5 µm, and a distance between the second edge and the fourth edge is greater than or equal to 0.2 µm and less than or equal to 1.5 µm. Specifically, Dasgupta teaches an embodiment of a semiconductor heterostructure where the overhang length L2 (“a distance between the first edge and the third edge”; “a distance between the second edge and the fourth edge”) is at least 500nm, or 0.5µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Yoshida and Dasgupta, such that the distances between the first and third edges and the second and fourth edges, respectively, is such that the performances of the source and drain regions is maximized such that the stability of the overall structure is not impaired.
Regarding claim 4, Yoshida teaches wherein the gate electrode is in Schottky contact with the semiconductor layer (Fig. 1 and [0020] point to the gate electrode 33 being in Schottky contact with the semiconductor layer 18.).
Response to Arguments
Applicant's arguments filed 04/27/2026 with regards to the use of references Yoshida, Dasgupta, ad Yoshimi have been fully considered but they are not persuasive. Specifically, Applicant argues that 1) the previously presented subject matter in claim 1 discussing the first-fourth openings and their relationship to one another is in fact not taught by the references, and 2) that no motivation exists to combine Yoshida, Dasgupta, and Yoshimi.
Regarding the first argument, Examiner argues that Applicant has provided a piecemeal analysis that focuses on Dasgupta rather than Yoshida et al. as a whole. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Specifically, Applicant argues that the lengths L1 and L2 taught in Dasgupta do not refer to an insulating layer and thus the reference fails to teach “in a plan view viewed in a direction perpendicular to the first main surface, the first edge of the first opening is positioned closer to the second opening than the third edge of the third opening is, the second edge of the second opening is positioned closer to the first opening than the fourth edge of the fourth opening is”. However, Examiner argues that Yoshida already presented the formation of the opening(s) in reference to an insulating layer, and that Dasgupta was used to teach the relationship between each opening in terms of positioning as described. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection.
Regarding the second argument, Examiner argues that Applicant has provided a conclusory statement with no supporting evidence. Specifically, Applicant simply states that there is no motivation to combine the references without providing any further evidence or reasoning. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejection.
Applicant’s arguments, see Remarks, filed 04/27/2026, with respect to the rejection(s) of amended claim(s) 1 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yoshida et al. in further view of Nakata (PGPub No. 20170092747).
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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