Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18, 23, 25-26 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (Pub. No.: US 2015/0102280) in view of Koh (Pub. No.: US 2011/0044093),
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1466
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Re claim 18, LEE, FIG. 4 teaches a phase change memory, comprising:
a first semiconductor element comprising:
a bit line (BL);
a memory unit (MC) on the bit line;
a P-N diode (SE) on the memory unit; and
an insulating layer (40b/40c/40a/11a/10) burying the bit line, the memory unit (MC) and the P-N diode (SE); and
a second semiconductor element [SSE] disposed below the first semiconductor element [FSE] and having a first contact region [FCR] and a second contact region [SCR],
wherein a first surface of the first semiconductor element (bottom surface of [FSE]) is bonded with a first surface of the second semiconductor element (top surface of [SSE]).
LEE fails to teach the limitation as listed right immediately below.
Koh teaches wherein the bit line (137, FIG. 4) of the first semiconductor element [FSE] is aligned and connected with the first contact region (11d) of the second semiconductor element [SSE];
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increasing reliability and/or program efficiency of the flash memory cell as taught by Koh, [0004].
Re claim 23, in the combination, LEE, FIG. 4 teaches the phase change memory of claim 18, wherein the first semiconductor element further comprises:
a first contact hole (occupied by MC/20T) formed in the insulating layer; and
a word line (WL) disposed on the P-N diode (SE) and formed in the insulating layer (40a/40b/40c/11a/10),
wherein the word line is connected to the P-N diode (SE), and connected to the second contact region [SCR] of the second semiconductor element through the first contact hole.
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485
911
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Re claim 25, LEE, FIG. 4 teaches the phase change memory of claim 18, wherein the first semiconductor element further comprises:
a first connection channel having a first connection region [FCoR] and a second connection region [SCoR] electrically isolated from each other and disposed below the bit line (B),
wherein the first connection region [FCoR] is connected to the bit line (B) through a first connection hole, and
wherein the first connection region [FCR] and the second connection region [SCoC] of the first semiconductor element are aligned (parallel in vertical direction) and connected with the first contact region [FCR] and the second contact region (DT right immediately below VC1) of the second semiconductor element, respectively.
Re claim 26, LEE, FIG. 4 teaches the phase change memory of claim 25, wherein the first semiconductor element further comprises:
a second contact hole (occupied by WC) formed in the insulating layer (40/40a/40b); and
a word line (WL) disposed on the P-N diode (SE) and formed in the insulating layer,
wherein the word line is connected to the P-N diode (SE), and connected to the second contact region [SCR] of the second semiconductor element [SSE] through the second connection region (20) and the second contact hole.
Re claim 32, LEE, FIG. 4 teaches the phase change memory of claim 18, wherein the memory unit (MC) comprises a phase change memory material (30, [0028]).
Response to Arguments
Applicant's arguments filed 12/04/2026 have been fully considered but they are not persuasive because LEE, FIG. 4 teaches a phase change memory, comprising:
a first semiconductor element comprising:
a bit line (BL);
a memory unit (MC) on the bit line;
a P-N diode (SE) on the memory unit; and
an insulating layer (40b/40c/40a) burying the bit line, the memory unit (MC) and the P-N diode (SE); and
a second semiconductor element [SSE] disposed below the first semiconductor element [FSE] and having a first contact region [FCR] and a second contact region [SCR],
wherein a first surface of the first semiconductor element (bottom surface of [FSE]) is bonded with a first surface of the second semiconductor element (top surface of [SSE]).
LEE fails to teach the limitation as listed right immediately below.
Koh teaches wherein the bit line (137, FIG. 4) of the first semiconductor element [FSE] is aligned and connected with the first contact region (11d) of the second semiconductor element [SSE];
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of increasing reliability and/or program efficiency of the flash memory cell as taught by Koh, [0004].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893