DETAILED ACTION
This action is responsive to the application No. 17/814,517 filed on July 24, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 07/26/2025 responding to the Office action mailed on 05/22/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 8, 9, and 12-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-9 and 12-15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai (CN 108735608).
Regarding Claim 1, Cai (see, e.g., Fig. 4-12), teaches a semiconductor structure, comprising:
A semiconductor substrate 210, wherein the semiconductor substrate is composed of a deep N-well 220, and a P-well 230 located on the deep N-well 220, and the semiconductor structure is formed on the P-well 230, and a first trench 270 and a second trench (i.e., trench where isolation structure 250 is) are provided in the semiconductor substrate 210, and a gate 281 is formed in the first trench 270, and a depth of the second trench is greater than a depth of the first trench 270 (see, e.g., pars. 0079-0080); and
a doped layer 260, wherein the doped layer 260 is located in the semiconductor substrate 210 on an outer side of the first trench 270 (see, e.g., par. 0080);
wherein:
in a direction perpendicular to the semiconductor substrate 210, the doped layer 260 comprises a transition layer 263 and an ion implantation layer 265 located on the transition layer 263 (see, e.g., par. 0079);
a doping concentration of the transition layer 263 is less than a doping concentration of the ion implantation layer 265 (see, e.g., pars. 0077, 0082); and
in the direction perpendicular to the semiconductor substrate 210, a top surface of the transition layer 263 is not lower than a bottom surface of the gate 281.
Regarding Claim 2, Cai teaches all aspects of claim 1. Cai (see, e.g., Fig. 4-12), teaches that in the direction perpendicular to the semiconductor substrate 210, the top surface of the transition layer 263 is not lower than a top surface of the gate 281.
Regarding Claim 3, Cai teaches all aspects of claim 1. Cai (see, e.g., Fig. 4-12), teaches that the gate comprises a gate oxide layer 280 and a gate conductive layer 281;
wherein:
the gate oxide layer 280 covers an inner wall surface of the first trench 270 (see, e.g., par. 0080); and
the gate conductive layer 281 is located in the first trench 270 that is covered with the gate oxide layer 280.
Regarding Claim 4, Cai teaches all aspects of claim 2. Cai (see, e.g., Fig. 4-12), teaches an insulating layer 282 is further comprised in the first trench 270;
wherein the insulating layer 282 covers the gate 281 (see, e.g., par. 0050).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cai (CN 108735608) in view of Lu (US 2022/0157824).
Regarding Claim 5, Cai teaches all aspects of claim 1. Cai does not show a contact structure formed on the doped layer 260.
Lu (see, e.g., Fig. 3), in similar DRAM devices to Cai, on the other hand, teaches a contact structure 50/42A formed on the doped layer 340/350, to electrically couple the bit line 44 and the storage capacitors 20 to the access transistors 30 and to effectively reduce a contact resistance between the access transistor 30 the contact structure 50/42A (see, e.g., pars. 0039, 0049).
It would have been obvious to one of ordinary skill in the art at the time of filing to include a contact structure in Cai’s device, as taught by Lu, to electrically couple the bit line and the storage capacitors to the access transistors and to effectively reduce a contact resistance between the access transistor the contact structure.
Regarding Claim 6, Cai and Lu teach all aspects of claim 5. Yilmaz (see, e.g., Figs. 2P, 7, 8J), teaches that the contact structure 50/42A comprises a bit line contact structure 42A and a storage node contact structure 50 that are discretely formed at either side of the first trench 106, wherein the bit line contact structure 42A and the storage node contact structure 50 are discretely formed in the ion implantation layer 340/350 (see, e.g., par. 0055).
With respect to claim 6, note that a “product-by-process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product-by-process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process steps that “a bit line contact structure and a storage node contact structure that are discretely formed at either side of the trench, wherein the bit line contact structure and the storage node contact structure are discretely formed in the ion implantation layer”, these are considered intermediate method steps that do not affect the structure of the final device.
As to the grounds of rejection under section 103, see MPEP §2113 which discusses the handling of “product-by-process” claims and recommends the alternative (§ 102/§ 103) grounds of rejection.
Note that applicant has the burden of proof in such case, as the above case law makes clear.
Regarding Claim 7, Cai and Lu teach all aspects of claim 6. Cai (see, e.g., Fig. 4-12), teaches that the semiconductor structure further comprises:
an isolation layer 250;
wherein the isolation layer 250 is located in the second trench (i.e., trench where isolation structure 250 is); and
a depth of the isolation layer 250 is greater than or equal to a depth of the first trench 270.
Response to Arguments
Applicant’s arguments filed on 07/26/2025 with respect to the rejection of claim 1 have been fully considered but are moot in view of the grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814