DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
August 2, 2025 has been entered.
Response to Arguments
RE: the rejection of claim(s) 1-10 under 35 USC 112(a), Applicant’s arguments and/or amendments have been fully considered and resolve the issues relating to the written description requirement. Accordingly, the rejection of claim(s) 1-10 under 35 USC 112(a) has been withdrawn.
RE: the rejection of claim(s) claims 1-10 under 35 USC 112(b), Applicant’s arguments and/or amendments have been considered but do not completely resolve the issues of indefiniteness. Claim 1 includes “the second pattern is in direct physical contact with the second doped region but not attached to the first doped region or the channel region,” and it is unclear how the second pattern can be in direct physical contact with the second doped region (and therefore the semiconductor channel layer as it includes the second doped region) but not attached to the first doped region or the channel region, which are part of the semiconductor channel layer. Therefore, the second pattern would still be indirectly attached to the first doped region and the channel region.
RE: the rejection of claim(s) 1-10 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new ground of rejection presented herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 includes “the second pattern is in direct physical contact with the second doped region but not attached to the first doped region or the channel region,” and it is unclear how the second pattern can be in direct physical contact with the second doped region (and therefore the semiconductor channel layer as it includes the second doped region) but not attached to the first doped region or the channel region, which are part of the semiconductor channel layer. Therefore, the second pattern would still be indirectly attached to the first doped region and the channel region. For the purposes of examination, this will be interpreted to mean “the second pattern is in direct physical contact with the second doped region but not in direct physical contact with the first doped region or the channel region.”
Claim 9 includes “wherein in the channel region, a blocking member is disposed on a side of the semiconductor channel layer away from the substrate, and a resistance of a portion of the semiconductor channel layer overlapping with the blocking member in a thickness direction of film layers is lower than a resistance of a portion of the semiconductor channel layer staggered from the blocking member in the thickness direction of the film layers” and claim 1 includes “the semiconductor channel layer comprises a channel region” and it is unclear if the channel region is inside the semiconductor channel layer or if the channel region includes other regions outside the semiconductor channel layer since based on the above, the blocking member is in the channel region and on the channel layer. It is therefore unclear if the blocking member is in inside the channel region or not. It is further unclear if “film layers” refers to “semiconductor channel layer,” “ohmic contact layer,” and/or “source-drain layer” from claim 1, or if this refers to other layers. For the purposes of examination, the channel region will be considered to be inside the semiconductor channel layer for claim 1, and for claim 9, the above limitation will be interpreted to mean “wherein on the channel region, a blocking member is disposed on a side of the semiconductor channel layer away from the substrate, and a resistance of a portion of the semiconductor channel layer overlapping with the blocking member in a thickness direction of the semiconductor channel layer, the ohmic contact layer, and the source-drain layer is lower than a resistance of a portion of the semiconductor channel layer staggered from the blocking member in the thickness direction of the semiconductor channel layer, the ohmic contact layer, and the source-drain layer.”
Claims 2-8 and 10 are rejected due to their dependency from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20090008634A1 (“Tessler”), in view of US20210391474A1 (“Mo”), further in view of US 20090303406 A1 (“Takasawa”).
RE: Claim 1, Tessler discloses A thin film transistor (TFT) device (1000A in FIG. 15A), comprising:
a substrate (18);
a semiconductor channel layer (14) disposed on the substrate, wherein the semiconductor channel layer comprises a channel region (middle portion of 14 under middle islands of 64, [0133]), a first region (leftmost portion of 14 under leftmost 62), and a second region (rightmost portion of 14 under rightmost 62), and the first region and the second region are disposed on both sides of the channel region (FIG. 15A shows the leftmost portion of 14 and the rightmost portion of 14 are disposed on both sides of the middle portion of 14);
an ohmic contact layer (leftmost portion of 62 and rightmost portion of 62 in FIG. 15A; 62 improves ohmic contact, [0133] and is therefore considered an ohmic contact layer) disposed on the semiconductor channel layer at a surface (upper surface of 14) thereof that faces away from the substrate (FIG. 15A shows upper surface of 14 faces away from 18), wherein the ohmic contact layer comprises a first pattern (leftmost portion of 62 in FIG. 15A) and a second pattern (rightmost portion of 62 in FIG. 15A),
wherein the first pattern is attached to the first region but not in direct physical contact with the second region (FIG. 15A shows leftmost portion of 62 is attached to the leftmost portion of 14 but not in direct physical contact with the rightmost portion of 62 ), and the second pattern is in direct physical contact with the second region (FIG. 15A shows the rightmost portion of 62 is in direct physical contact with the rightmost portion of 14 but not in direct physical contact with the leftmost portion of 62);
a source-drain layer (10, 16) comprising a source (10) and a drain (16), wherein the source is disposed on the first pattern at a surface thereof that faces away from the substrate (FIG. 15A shows 10 is disposed on leftmost portion of 62 at an upper surface thereof that faces away from 18), and the drain is disposed on the second pattern at a surface thereof that faces away from the substrate (FIG. 15A shows 16 is disposed on rightmost portion of 62 at an upper surface thereof that faces away from 18); and
a compensation pattern (the middle portions of 62 included in 64; 64 are electrically conductive islands, [0133]), disposed only on the channel region at a surface thereof that faces away from the substrate (FIG. 15A shows middle portions of 62 in 64 are disposed only on the middle portion of 14 at an upper surface thereof that faces away from 18), and the compensation pattern is a same type of semiconductor as the first pattern and the second pattern (60, 62 are patterned to define 64, [0133]; accordingly, the leftmost, rightmost portions of 62 and the middle portions of 62 in 64 are of the same type of semiconductor, n-type Si, [0133]);
wherein the first pattern and the second pattern are not in direct physical contact with the compensation pattern (FIG. 15A shows leftmost and rightmost portions of 62 are not in direct physical contact with the middle portions of 62 in 64).
Tessler does not explicitly disclose:
the first pattern is not in direct physical contact with the channel region;
the second pattern is not in direct physical contact with the channel region;
the leftmost and rightmost portions of 14 are doped regions;
wherein the compensation pattern and the semiconductor channel layer are different types of semiconductors.
However, in the same field of endeavor, Mo discloses (referring to FIG. 6 for assistance), after the source electrode 610 and the drain electrode 620 are formed, the active layer 40 and the semiconductor composite layer 50 are subjected to dry etching treatment with the source electrode 610 and the drain electrode 620 as etching barrier layers, so as to obtain a second recess (not labeled in FIG. 6) corresponding to the first recess 81. The second groove penetrates through the semiconductor composite layer 50 and partially penetrates to the active layer 40. “Partially penetrating” means that the part of the active layer in the second recess is not etched away completely, [0067].Mo further discloses by placing the channel region in a preset gas atmosphere for heating treatment, the damage of the channel region can be repaired, weak bonds in the amorphous silicon can be reduced, the illumination and illumination stability of the active switch can be enhanced and the drift of the threshold voltage is reduced, [0041].
FIG. 6 of Mo shows the doped regions 50 in direct physical contact with the non-recessed portions of the layer 40, and not in direct physical contact with the middle recessed portion of 40.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel layer 14 to have a recess / groove as taught by Mo in order to better control the current in the channel with the gate and reduce the drift of the threshold voltage of the device. As a result, the recessed portion of the channel layer 14 would correspond to the claimed channel region, the left non-recessed portion of 14 would correspond to the claimed first region, the right non-recessed portion of 14 would correspond to the claimed second region, the leftmost and rightmost portions of 62 would be in direct physical contact with the non-recessed portions of the channel layer 14, and the leftmost and rightmost portions of 62 would not be in direct physical contact with the recessed portion of the channel layer 14.
Tessler further discloses the layer 62 is n-type, [0133].
FIG. 15A shows the leftmost portion of 62 directly contacting the source electrode 10. Accordingly, the leftmost portion of 62 is considered a source contact layer.
FIG. 15A shows the rightmost portion of 62 directly contacting the drain electrode 16. Accordingly, the rightmost portion of 62 is considered a drain contact layer.
In the same field of endeavor, Takasawa discloses The drain semiconductor layer 47 and the source semiconductor layer 48 are of the same electroconductive type of a p-type or n-type for electroconductive type, and the channel semiconductor layer 46 is of the same electroconductive type or an opposite electroconductive type relative to the drain semiconductor layer 47 and the source semiconductor layer 48, [0076].
First Modification:
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dope the channel layer 14 so that it has the opposite conductivity type (i.e., p-type) relative to the source and drain contact layer 62 (which is n-type) as taught by Takasawa in order to increase the conductivity of the channel layer 14, resulting in a first doped region (leftmost portion of 14 which is non-recessed) and a second doped region (rightmost portion of 14 which is non-recessed) disposed on both sides of the middle portion of 14 (which is recessed); wherein the compensation pattern and the semiconductor channel layer are different types of semiconductors (portion of 62 in 64 is n-type, [0133]; As modified, 14 would be p-type).
Alternative Modification:
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conductivity type of the source and drain contact layer 62 by making the layer 62 p-type as taught by Takasawa since this would have been obvious to try since there was a need to select a conductivity type for the source and drain contact layer 62 before the effective filing date of the claimed invention, and a p-type source and drain contact layer is one solution out of a finite number of solutions for the conductivity type in a source and drain contact layer identified by Takasawa and this would have had a reasonable expectation of success, see MPEP 2143.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dope the channel layer 14 so that it has the opposite conductivity type (i.e., n-type) relative to the source and drain contact layer 62 (which is modified to p-type) as taught by Takasawa in order to increase the conductivity of the channel layer 14, resulting in a first doped region (leftmost portion of 14 which is non-recessed) and a second doped region (rightmost portion of 14 which is non-recessed) disposed on both sides of the middle portion of 14 (which is recessed); wherein the compensation pattern and the semiconductor channel layer are different types of semiconductors (As modified, the portion of 62 in 64 is p-type, 14 is n-type).
RE: Claim 2, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 1, wherein the semiconductor channel layer is a hole-type semiconductor, and the first pattern, the second pattern, and the compensation pattern are electron-type semiconductors (As modified in the First Modification above, the channel layer 14 is p-type; Tessler discloses layer 62 is n-type, [0133] and therefore the leftmost, middle, and rightmost portions of 62 would be n-type).
RE: Claim 3, Tessler in view of Mo, Takasawa discloses The TFT device according to claim1, wherein the semiconductor channel layer is an electron-type semiconductor, and the first pattern, the second pattern, and the compensation pattern are hole-type semiconductors (As modified in the Alternative Modification above, the channel layer 14 is n-type and layer 62 is p-type, therefore the leftmost, middle, and rightmost portions of 62 would be p-type).
RE: Claim 4, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 2, wherein the compensation pattern, the first pattern, and the second pattern are arranged in a same layer (In Tessler FIG. 15A shows the leftmost, middle, and rightmost portions of 62 are in the same layer 62; As modified, the same layer 62 would be patterned to form the leftmost, middle, and rightmost portions of 62).
RE: Claim 5, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 4, wherein a thickness of the compensation pattern, a thickness of the first pattern, and a thickness of the second pattern are equal (In Tessler FIG. 15A shows thicknesses of the leftmost, middle, and rightmost portions of 62 are equal).
RE: Claim 6, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 5, wherein a distance between the compensation pattern and the first pattern is equal to a distance between the compensation pattern and the second pattern (In Tessler FIG. 15A shows a distance between the leftmost portion of 62 and the left middle portion of 62 in 64 is equal to a distance between the rightmost portion of 62 and the right middle portion of 62 in 64).
RE: Claim 7, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 4, wherein the compensation pattern comprises at least two sub-compensation patterns, and two adjacent sub-compensation patterns have a same thickness (In Tessler FIG. 15A shows two middle portions of 62 in 64 which are adjacent and have the same vertical thickness).
RE: Claim 8, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 7, wherein the sub-compensation patterns are uniformly arranged, and distances between adjacent sub-compensation patterns are equal (Annotated FIG. 15A of Tessler below shows the patterns 62 in 64 are uniformly arranged, and a first distance between upper portions of adjacent sub-compensation patterns 62 is equal to a second distance between lower portions of adjacent sub-compensation patterns 62).
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Annotated FIG. 15A of Tessler
RE: Claim 9, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 1, wherein on the channel region, a blocking member (In FIG. 15A, the portion of 60 in 64; 60 is mislabeled in FIG. 15A but correctly labeled in FIGs. 15C, 15D, 15E to refer to the black layer which forms 10, 16, and the upper layer of 64; 60 and 62 are patterned to define islands 64, [0133]; 60 is a metal layer, [0133] which forms a block and also acts to block or obstruct portions of 66 from contacting 14; As the term “blocking member” is not defined in the instant specification, under a broad reasonable interpretation, the metal portion(s) of 60 in 64 is/are considered a blocking member) is disposed on a side (top side of 14) of the semiconductor channel layer away from the substrate, and a resistance of a portion of the semiconductor channel layer overlapping with the blocking member in a thickness direction of the semiconductor channel layer, the ohmic contact layer, and the source-drain layer is lower than a resistance of a portion of the semiconductor channel layer staggered from the blocking member in the thickness direction of the semiconductor channel layer, the ohmic contact layer, and the source-drain layer (Tessler discloses 64 are conductive regions, [0133]; FIG. 15D shows n+ regions 62’/64 in the middle of the channel layer 14, [0136]; Tessler further discloses The second approach is based on a standard lateral configuration, but where the channel length is effectively shortened. This can be achieved by including highly conductive regions in the channel. Shortening the effective length that the charge needs to pass through in the semiconductor reduces the overall channel resistance and results in a higher current, [0023]; Tessler further discloses The channel element may comprise a layer of the first, lower electrical conductivity material selectively doped with a second material of the higher electrical conductivity within said spaced-apart regions arranged in the two-dimensional array, [0051].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to, for the Alternative Modification above, include conductive regions 62’/64 in the middle of the channel layer 14 as taught by Tessler to increase the conductivity of the channel layer 14 in regions that overlap with the gate. As a result, the resistance of a portion of 62’, 64 in the channel layer 14 overlapping with 60 in 64 that is disposed over 14 in the thickness direction would be lower than other portions of the channel layer 14 staggered from 60 in 64 that is disposed over 14 in the thickness direction. As a result, the conductivity type of the channel 14 would remain n-type).
RE: Claim 10, Tessler in view of Mo, Takasawa discloses The TFT device according to claim 1, wherein material of the compensation pattern comprises at least one of amorphous silicon, phosphorus, and boron (Tessler identifies a-Si as amorphous silicon, [0016]; 62 is a-Si, [0133] and therefore comprises amorphous silicon).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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