Prosecution Insights
Last updated: July 17, 2026
Application No. 17/814,593

Semiconductor Device and Method of Making an Optical Semiconductor Package

Final Rejection §103
Filed
Jul 25, 2022
Priority
Jul 30, 2021 — provisional 63/203,759
Examiner
CHOUDHRY, MOHAMMAD M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UTAC Headquarters Pte. Ltd.
OA Round
4 (Final)
82%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
575 granted / 702 resolved
+13.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
33 currently pending
Career history
736
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
93.6%
+53.6% vs TC avg
§102
1.6%
-38.4% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 702 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7, 21, 23-25, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Webster (US 2013/0265486, hereinafter Webster) in view of Chen et al. (US 2022/0037566, hereinafter Chen) and further in view of Luan (US 2016/0190380, hereinafter Luan). With respect to claim 7, Webster discloses a method of making a semiconductor device (Fig. 16), comprising: providing a substrate (102); disposing a semiconductor die (106) comprising a photosensitive circuit (Para 0023 – image sensor is photosensitive) over the substrate; forming a bond wire (114) to electrically couple the semiconductor die to the substrate (114 couples 106 to the substrate 102); disposing a lens (Para 0079 – lens) over the photosensitive circuit (Fig. 12), wherein the lens includes a planar surface (Fig. 12 – 1210 has a planar surface); depositing an encapsulant over the substrate, semiconductor die, and lens, wherein the encapsulant covers the bond wire, and a side surface of the lens perpendicular to the planar surface (Para 0022-0024; 0034-0036; Fig. 16). Webster does not explicitly disclose a protective layer completely covering the planar surface; and wherein the lens already has the protective layer covering the planar surface prior to disposing the lens over the photosensitive circuit; the encapsulant covers the protective layer; and removing the protective layer after depositing the encapsulant. In an analogous art, Chen discloses a protective layer completely covering the planar surface (Para 0041 – protection layer); and wherein the lens already has the protective layer covering the planar surface prior to disposing the lens over the photosensitive circuit (Para 0032; 0041 and 0050). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster’s method by having Chen’s disclosure in order to protect the lens during fabrication of a semiconductor device. Webster/Chen does not explicitly disclose that the encapsulant covers the protective layer; and removing the protective layer after depositing the encapsulant. In an analogous art, Luan discloses that the encapsulant covers the protective layer (Fig. 3C); and removing the protective layer after depositing the encapsulant (Fig. 3D- Para 0040). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen’s method by having Luan’s disclosure in order to protect the lens during fabrication of a semiconductor device. With respect to claim 21, Webster discloses a method of making a semiconductor device (Fig. 16), comprising: providing a substrate (102); disposing a semiconductor die (106) including a photosensitive circuit over the substrate (Para 0023 – image sensor is photosensitive), wherein the semiconductor die is electrically coupled to the substrate (bonding wire 114 connects 106 with substrate 102); disposing a lens (Para 0079 – lens) over the semiconductor die (Fig. 12), depositing an encapsulant over the substrate, semiconductor die, and lens (Para 0022-0024; 0034-0036; Figs. 15 & 16). Webster does not explicitly disclose wherein the lens includes a protective layer formed over the lens prior to disposing the lens over the semiconductor die; and wherein the lens is recessed within the encapsulant, and wherein the encapsulant physically contacts the substrate, the semiconductor die, and the lens. In an analogous art, Chen discloses wherein the lens includes a protective layer (Para 0041 – protection layer) formed over the lens prior to disposing the lens over the semiconductor die (Para 0032; 0041 and 0050). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster’s method by having Chen’s disclosure in order to protect the lens during fabrication of a semiconductor device. Webster/Chen does not explicitly disclose wherein the lens is recessed within the encapsulant, and wherein the encapsulant physically contacts the substrate, the semiconductor die, and the lens. In an analogous art, Luan discloses wherein the lens is recessed within the encapsulant (Fig. 3D), and wherein the encapsulant physically contacts the substrate, the semiconductor die, and the lens (Fig. 3C). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen’s method by having Luan’s disclosure in order to protect the lens during fabrication of a semiconductor device. With respect to claim 23, Webster/Chen does not explicitly disclose removing the protective layer after depositing the encapsulant. In an analogous art, Luan discloses removing the protective layer after depositing the encapsulant (Fig. 3D- Para 0040). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen’s method by having Luan’s disclosure in order to protect the lens during fabrication of a semiconductor device. With respect to claim 24, Webster/Chen does not explicitly disclose forming the protective layer to include a surface that is coplanar to a surface of the encapsulant. In an analogous art, Luan discloses forming the protective layer to include a surface that is coplanar to a surface of the encapsulant (Fig. 3C). depositing the encapsulant to cover a top surface of the protective layer. Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen’s method by having Luan’s disclosure in order to protect the lens during fabrication of a semiconductor device. With respect to claim 25, Webster/Chen does not explicitly disclose depositing the encapsulant to cover a top surface of the protective laye In an analogous art, Luan discloses depositing the encapsulant to cover a top surface of the protective layer (Para 0040-0041). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen’s method by having Luan’s disclosure in order to protect the lens during fabrication of a semiconductor device. With respect to claim 27, Webster further discloses including mounting the substrate to a printed circuit board of an electronic device (Para 0080 & 0090), wherein the semiconductor die is electrically coupled to the printed circuit board through the substrate (Para 0096 and 0126). Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Webster/Chen/Luan in view of Suetake (US 2010/0133419, hereinafter Suetake) With respect to claim 8, Webster/Chen/Luan does not explicitly disclose laminating the protective layer onto the lens In an analogous art, Suetake discloses laminating the protective layer onto the lens (Fig. 3b – layer 7 is laminated over the lens). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen/Luan’s method by having Suetak’s disclosure in order to protect the lens of an optical device. With respect to claim 10, Webster/Chen/Luan does not explicitly disclose removing the encapsulant from over the lens prior to removing the protective layer. In an analogous art, Suetake discloses removing the encapsulant from over the lens prior to removing the protective layer (Fig. 3D– encapsulant is removed prior to removing layer 7). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen/Luan’s method by having Suetak’s disclosure in order to protect the lens of an optical device. Claims 9 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Webster/Chen/Luan in view of Dagdeviren et al. (US 2021/0100460, hereinafter Dagdeviren). With respect to claims 9 & 26, Webster/Chen/Luan does not explicitly disclose that the protective layer includes a washable epoxy. In an analogous art, Dagdeviren discloses that the protective layer includes a washable epoxy (Para 0089). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen/Luan’s method by having Dagdeviren’s disclosure in order to have the flexibility of easily removing the adhesive when it’s needed during manufacturing process. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Webster/Chen/Luan/Suetake in view of Park et al. (US 2014/0078763, hereinafter Park). With respect to claim 12, Webster/Chen/Luan/Suetake does not explicitly disclose mounting the lens to the semiconductor die with an ultra- violet (UV) cured adhesive; and curing the adhesive by emitting a UV light through the lens. In an analogous art, Park discloses mounting the lens to the semiconductor die with an ultra- violet (UV) cured adhesive (Para 0092); and curing the adhesive by emitting a UV light through the lens (Para 0051; 0092 and 0101). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen/Luan/Suetake’s method by having Park’s disclosure in order to attach different components with each other of a semiconductor device. . Claims 13-14, 22 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Webster/Chen/Luan in view of Takada (US 2004/0223074, hereinafter Takada). With respect to claim 13, Webster/Chen/Luan does not explicitly disclose forming a step cut on an edge of the lens. In an analogous art, Takada discloses forming a step cut on an edge of the lens (Fig. 48 – Para 0388). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen/Luan’s method by having Takada’s disclosure in order to attach the lens with other components. With respect to claim 14, Webster discloses depositing the encapsulant over the step cut (Fig. 16 – encapsulant covers the entire surface, it’s obvious if there is a cut in the lens then 5a will cover that too). With respect to claim 22, Webster/Chen/Luan does not explicitly disclose wherein the lens includes a step cut. In an analogous art, Takada discloses wherein the lens includes a step cut. (Fig. 48 – Para 0388). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Webster/Chen/Luan’s method by having Takada’s disclosure in order to attach the lens with other components. With respect to claim 28, Webster further discloses mounting the substrate to a printed circuit board of an electronic device (Para 0080 & 0090), wherein the semiconductor die is electrically coupled to the printed circuit board through the substrate (Para 0096 and 0126). Response to Arguments Based on new ground of rejection, applicant’s arguments regarding amended claims are moot. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Show 1 earlier event
May 21, 2025
Non-Final Rejection mailed — §103
Jul 30, 2025
Response Filed
Oct 23, 2025
Final Rejection mailed — §103
Nov 13, 2025
Request for Continued Examination
Nov 19, 2025
Response after Non-Final Action
Dec 17, 2025
Non-Final Rejection mailed — §103
Feb 19, 2026
Response Filed
May 29, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+11.9%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 702 resolved cases by this examiner. Grant probability derived from career allowance rate.

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