DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 5-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made, as explained above, without traverse in the replies filed on 1.8.2025 and 1.29.2025.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “under-bump metallization layers respectively coupled to a top and a bottom of the one or more first bump-bonds, wherein a one of the under-bump metallization layers is directly connected to a silicon wafer of the Josephson wafer on a first side and a second one of the under-bump metallization layers is directly connected to a through-substrate via and a second silicon wafer on a second side” (claim 1) and “under-bump metallization layers respectively coupled to a top and a bottom one or more bump-bonds bump-bonded to the first wafer and the second wafer, wherein a one of the under-bump metallization layers is directly connected to the first wafer, which is associated with the Josephson wafer, and a second one of the under-bump metallization layers is directly connected to the second wafer” (claim 21) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Note: the under-bump metallizations (118) are coupled to solder bumps (116) and not to bump-bonds (114) as claimed per Fig. 1 and because 118 is part of 114 – “each of the set of bump-bonds 114 can be comprised of a solder bump 116 that is sandwiched between two under-bump metallizations 118” per the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims are objected to because of the following informalities:
In claim 1, “a one of the under-bump metallization layers” should read --a first one of the under-bump metallization layers-- for clarity.
In claim 1, “the Josephson wafer” should read –the parametric Josephson wafer--.
In claim 21, “to a top and a bottom one or more bump-bonds” should read --to a top and a bottom of one or more bump-bonds--.
In claim 21, “a one of the under-bump metallization layers” should read –a first one of the under-bump metallization layers--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 21, the “under-bump metallization layers respectively coupled to a top and a bottom of the one or more first bump-bonds, wherein a one of the under-bump metallization layers is directly connected to a silicon wafer of the Josephson wafer on a first side and a second one of the under-bump metallization layers is directly connected to a through-substrate via and a second silicon wafer on a second side” (claim 1) and “under-bump metallization layers respectively coupled to a top and a bottom one or more bump-bonds bump-bonded to the first wafer and the second wafer, wherein a one of the under-bump metallization layers is directly connected to the first wafer, which is associated with the Josephson wafer, and a second one of the under-bump metallization layers is directly connected to the second wafer” (claim 21) causes the claims to fail to comply with the written description requirement.
The under-bump metallizations (118) are coupled to solder bumps (116) and not to bump-bonds (114) as claimed per Fig. 1 and because 118 is part of 114 – “each of the set of bump-bonds 114 can be comprised of a solder bump 116 that is sandwiched between two under-bump metallizations 118” per the specification.
Hence the claims are directed to an embodiment which is not supported by the specification; claims 2-4 are dependents of claim 1 and do not address this deficiency.
Claims 1-4 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 21, the “under-bump metallization layers respectively coupled to a top and a bottom of the one or more first bump-bonds, wherein a one of the under-bump metallization layers is directly connected to a silicon wafer of the Josephson wafer on a first side and a second one of the under-bump metallization layers is directly connected to a through-substrate via and a second silicon wafer on a second side” (claim 1) and “under-bump metallization layers respectively coupled to a top and a bottom one or more bump-bonds bump-bonded to the first wafer and the second wafer, wherein a one of the under-bump metallization layers is directly connected to the first wafer, which is associated with the Josephson wafer, and a second one of the under-bump metallization layers is directly connected to the second wafer” (claim 21) are indefinite because they are not consistent with the specification wherein inconsistencies between the claimed subject matter and the specification are the basis for indefiniteness per MPEP 2173.03 (“A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty”).
The under-bump metallizations (118) are coupled to solder bumps (116) and not to bump-bonds (114) as claimed per Fig. 1 and because 118 is part of 114 – “each of the set of bump-bonds 114 can be comprised of a solder bump 116 that is sandwiched between two under-bump metallizations 118” per the specification.
Hence, the inconsistency between the claimed subject matter and the specification renders the claims indefinite; claims 2-4 are dependents of claim 1 and do not address this deficiency.
For purposes of examination, it will be treated as presented or as disclosed in Fig. 1.
Regarding claim 1, “a superconducting qubit wafer” and “a second silicon wafer” refer to the same element with different language which renders the claim indefinite.
Fig. 1 and a related text disclose “the high-density flip-chip co-package 100 can include…a silicon wafer 104” and “a set of superconducting qubits 124 can be fabricated on the first side 110 of the silicon wafer 104”. Hence, per the specification the second silicon wafer is part of the superconducting qubit wafer which is not what is being claimed as “a superconducting qubit wafer” and “a second silicon wafer” are not connected by any claim language; the examiner suggests and treats as --a second silicon wafer of the superconducting qubit wafer--.
None of dependent claims 2-4 address this deficiency.
Regarding claim 21, “associated with the Josephson wafer” is indefinite because “the Josephson wafer” lacks proper antecedent basis. The examiner suggests and treats as -- associated with the one or more parametric Josephson devices--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Oliver et al. (of record, US 10199553 B1) in view of Gilleo et al. (of record, US 6194788 B1) and Mutus et al. (US 20180366634 A1)
Regarding claim 1, Oliver discloses (Fig. 6) a device, comprising:
a superconducting qubit wafer (620, “…620 (e.g., a Qubit chip)”, “In FIG. 6, superconducting IC 640 and/or superconducting IC 650 can be at least part of a resonator, a Josephson junction, a qubit, an inductor, a capacitor, a bias line and combinations thereof”) coupled, by one or more first bump-bonds (634), to a parametric Josephson wafer (610, “…610 (e.g., a silicon (Si) substrate)”, “…640 (e.g., a superconducting resonator device) is disposed over a selected portion of the second surface of first semiconductor structure 610”, “In FIG. 6, superconducting IC 640 and/or superconducting IC 650 can be at least part of a resonator, a Josephson junction, a qubit, an inductor, a capacitor, a bias line and combinations thereof”);
under-bump metallization layers (632 and 636/621, “at least one of first section 632 and third section 636 may be provided as an under bump metal (UBM)”) respectively coupled to a top and a bottom of the one or more first bump-bonds (634), wherein a one of the under-bump metallization layers (632) is
Oliver fails to disclose (a) a first underfill that surrounds the one or more first bump-bonds and (b) wherein a one of the under-bump metallization layers is directly connected to a silicon wafer on a first side and a second one of the under-bump metallization layers is directly connected to a through-substrate via and a second silicon wafer on a second side.
Regarding (a), Gilleo discloses a first underfill (16) that surrounds the one or more first bump-bonds (14, Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an underfill as claimed in the device of Oliver in view of Gilleo so as to (i) eliminate separate underfill and fluxing steps (Oliver, Abstract), (ii) provide “a flux/underfill material that can harden quickly while offering both excellent fluxing properties and excellent underfill properties” as disclosed by Oliver, and/or, (iii) so as to mechanically protect bumps.
Regarding (b), Mutus discloses (Fig. 1) wherein a one of the under-bump metallization layers (120/116) is directly connected to a silicon wafer (114, [0035]) on a first side (bottom) and a second one of the under-bump metallization layers (120/116) is directly connected to a through-substrate via (118) and a second silicon wafer (110, [0034]) on a second side (top).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arrangement of Mutus in Oliver/Gilleo and arrive at the claimed invention so as to enable “achieving 3D integration, without introducing lossy processing/dielectrics, is to couple the chips using bump bonding, in which the chips are joined to one another by superconducting bump bonds” (Mutus, [0033]).
Regarding claim 2, Oliver/Gilleo/Mutus discloses wherein the first underfill (16) is a composite material comprising an epoxy polymer (“epoxy resins”, “polymerization catalysts”) and a filler (“A mineral filler such as silicon dioxide”), wherein the filler is at least one material selected from the group consisting of silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and graphene.
Regarding claim 21, Oliver discloses a flip-chip package (Fig. 6), comprising:
a first wafer (610) bump-bonded to a second wafer (620), wherein the first wafer includes one or more parametric Josephson devices (640), and wherein the second wafer includes one or more superconducting qubits (650);
under-bump metallization layers (632 and 636/621) respectively coupled to a top and a bottom one or more bump-bonds (634) bump-bonded to the first wafer and the second wafer, wherein a one of the under-bump metallization layers (632) is
Oliver fails to disclose (a) an underfill that separates the first wafer from the second wafer, wherein the one or more parametric Josephson devices are located between the underfill and the first wafer and (b) wherein a one of the under-bump metallization layers is directly connected to the first wafer.
Regarding (a), Gilleo discloses an underfill (16) that separates the first wafer (e.g., 12) from the second wafer (e.g., “The use of a standard flip chip bonder would allow a flip chip to be assembled to a board that already contained mounted component”, Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an underfill as claimed in the device of Oliver in view of Gilleo so as to (i) eliminate separate underfill and fluxing steps (Oliver, Abstract), (ii) provide “a flux/underfill material that can harden quickly while offering both excellent fluxing properties and excellent underfill properties” as disclosed by Oliver, and/or, (iii) mechanically protect bumps.
The underfill disclosed by Gilleo in Oliver suggests “an underfill that separates the first wafer from the second wafer” since said underfill of Gilleo would be placed between wafers 610 and 620.
Regarding “wherein the one or more parametric Josephson devices are located between the underfill and the first wafer”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to place element 640 between the underfill and 610, arriving at the claimed invention, in the device of Oliver/Gilleo so as to mechanically protect active devices with the underfill.
Regarding (b), Mutus discloses (Fig. 1) wherein a one of the under-bump metallization layers (116/120) is directly connected to the first wafer (114).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arrangement of Mutus in Oliver/Gilleo and arrive at the claimed invention so as to enable “achieving 3D integration, without introducing lossy processing/dielectrics, is to couple the chips using bump bonding, in which the chips are joined to one another by superconducting bump bonds” (Mutus, [0033]).
Claims 1-4 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Mutus et al. (of record, US 10497853 B2) and Zarbock et al. (of record, US 7588968 B1).
Regarding claims 1 and 2, Mutus discloses (claim 1) a device (Fig. 1), comprising:
a superconducting qubit wafer (110, “first circuit elements 108 can include, e.g., quantum circuit elements for use in performing quantum processing operations”) coupled, by one or more first bump-bonds (106), to a parametric Josephson wafer (114, “second circuit elements 112 include classical circuit elements. Classical circuit elements generally process data in a deterministic manner and include, e.g., circuit elements such as rapid single flux quantum (RSFQ) devices. RSFQ is a digital electronics technology that uses superconducting devices, namely Josephson junctions”).
under-bump metallization layers (120/116) respectively coupled to a top and a bottom of the one or more first bump-bonds (106), wherein a one of the under-bump metallization layers (120/116) is directly connected to a silicon wafer of the Josephson wafer (114, “the substrate 114 can be formed from a low loss dielectric material suitable for quantum circuit elements, such as single crystalline silicon or sapphire”) on a first side (bottom) and a second one of the under-bump metallization layers (120/116) is directly connected to a through-substrate via (118) and a second silicon wafer (110, “the substrate 110 for quantum circuit elements can be formed from a low loss dielectric material, such as single crystalline silicon or sapphire”) on a second side (top);
Mutus fails to disclose (claim 1) a first underfill that surrounds the one or more first bump-bonds, and, (claim 2) wherein the first underfill is a composite material comprising an epoxy polymer and a filler, wherein the filler is at least one material selected from the group consisting of silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and graphene.
Zarbock discloses (claim 1) a first underfill (124) that surrounds the one or more first bump-bonds (109/111, Fig. 1), and, (claim 2) wherein the first underfill is a composite material comprising an epoxy polymer and a filler, wherein the filler is at least one material selected from the group consisting of silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and graphene (“underfill 124 may comprise a variety of materials, such as, for instance, an epoxy polymer, with or without filler such as ceramic material and/or silica”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an underfill as claimed in the device of Mutus in view of Zarbock so as to mechanically protect bumps.
Regarding claim 3, Mutus/Zarbock discloses (Fig. 1) wherein at least one first parametric Josephson device (112) is located on (over) a first side (bottom) of the parametric Josephson wafer (114), wherein at least one superconducting qubit (108) is located on (over) a first side (top) of the superconducting qubit wafer (110), wherein the superconducting qubit wafer includes at least one first through-substrate via (118) electrically connecting (inherent) the first side (top) of the superconducting qubit wafer (110) to a second side (bottom) of the superconducting qubit wafer (110), and wherein the one or more first bump-bonds (at least 106) couple (mechanically indirectly) the first side (bottom) of the parametric Josephson wafer (114) to the second side (bottom) of the superconducting qubit wafer (110).
Regarding claim 4, Mutus/Zarbock fails to disclose wherein the at least one first parametric Josephson device includes a Josephson parametric amplifier, a Josephson travelling-wave parametric amplifier, a Josephson directional amplifier, a Josephson parametric converter, a Josephson circulator, or a Josephson isolator.
However, Mutus discloses “second circuit elements 112 include classical circuit elements. Classical circuit elements generally process data in a deterministic manner and include, e.g., circuit elements such as rapid single flux quantum (RSFQ) devices. RSFQ is a digital electronics technology that uses superconducting devices, namely Josephson junctions”
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to include a device as claimed in the device of Mutus/Zarbock and arrive at the claimed invention so as to facilitate the processing of quantum data, achieve signal boosting and/or noise mitigation, and/or, because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 21, Mutus discloses a flip-chip package (Fig. 1), comprising:
a first wafer (114) bump-bonded to a second wafer(110), wherein the first wafer includes one or more parametric Josephson devices (114, “second circuit elements 112 include classical circuit elements. Classical circuit elements generally process data in a deterministic manner and include, e.g., circuit elements such as rapid single flux quantum (RSFQ) devices. RSFQ is a digital electronics technology that uses superconducting devices, namely Josephson junctions”), and wherein the second wafer includes one or more superconducting qubits (110, “first circuit elements 108 can include, e.g., quantum circuit elements for use in performing quantum processing operations”);
under-bump metallization layers (116/120) respectively coupled to a top and a bottom one or more bump-bonds (106) bump-bonded to the first wafer and the second wafer, wherein a one of the under-bump metallization layers (116/220) is directly connected to the first wafer (114), which is associated with the Josephson wafer (114), and a second one of the under-bump metallization layers (116/120) is directly connected to the second wafer (110).
Mutus fails to disclose an underfill that separates the first wafer from the second wafer, wherein the one or more parametric Josephson devices are located between the underfill and the first wafer.
Zarbock discloses an underfill (124) that separates the first wafer (103) from the second wafer (101),
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include an underfill as claimed in the device of Mutus in view of Zarbock so as to mechanically protect bumps.
Regarding “wherein the one or more parametric Josephson devices are located between the underfill and the first wafer”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to place elements 112 between the underfill and 114, arriving at the claimed invention, in the device of Mutus/Zarbock so as to mechanically protect active devices with the underfill.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Mutus et al. (of record, US 10497853 B2) and Zarbock et al. (of record, US 7588968 B1) as applied to claim 3, and further in view of Applicants Admission of Prior Art (of record, AAPA, MPEP 2129).
Regarding claim 4, Mutus/Zarbock fails to disclose wherein the at least one first parametric Josephson device includes a Josephson parametric amplifier, a Josephson travelling-wave parametric amplifier, a Josephson directional amplifier, a Josephson parametric converter, a Josephson circulator, or a Josephson isolator.
However, AAPA discloses “Superconducting quantum computing hardware systems utilize parametric Josephson devices for signal boosting and/or noise mitigation purposes”.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include a device as claimed in the device of Mutus/Zarbock in view of AAPA and arrive at the claimed invention so as to achieve signal boosting and/or noise mitigation, and/or, because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Response to Arguments
Applicant's arguments filed 11.14.2025 have been fully considered but they are not persuasive.
The applicant alleges the prior art of record does not disclose or suggest amended claims 1 and 21; this is not persuasive per the rejections above.
The applicant alleges AAPA does not disclose wherein the at least one first parametric Josephson device includes a Josephson parametric amplifier, a Josephson travelling-wave parametric amplifier, a Josephson directional amplifier, a Josephson parametric converter, a Josephson circulator, or a Josephson isolator; this is not persuasive since AAPA discloses “Superconducting quantum computing hardware systems utilize parametric Josephson devices for signal boosting and/or noise mitigation purposes” wherein “signal boosting” and “noise mitigation” includes or renders obvious an amplifier.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Patent Examiner, Art Unit 2818
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