DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 5-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected inventions/species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the replies filed on 1.8.2025 and 1.29.2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim is indefinite for multiple reasons:
First, the limitation “wherein each of the plurality of bump-bonds comprises” followed by the limitation “a solder bump of the one or more solder bumps” (emphasis added) is indefinite because there cannot be a plurality of bump-bonds with only one solder bump; the claim(s) must recite a plurality of solder bumps.
Second, the limitation “a UBM of the under-bump metallization (UBM) layers, wherein a first one the UBM layers is on the top of the solder bump of the one or more solder bumps and a second one of the UBM is on the bottom of the solder bump of the one or more solder bumps” (emphasis added) is indefinite because (a) the claim interchangeably switches between “UBM” and “UBM layers”; consistency of language is required to avoid ambiguity and (b) it is unclear what the relationship is between “a UBM”, “a first one of the UBM layers” and “a second one of the UBM”; if there is already a first/second UBM on a top/bottom of a solder bump, what is then “a UBM”? The claim appears to be using three different terms to refer to two separate elements.
Third, the limitations “a first one the UBM layers is on the top of the solder bump of the one or more solder bumps” (emphasis added) and “a first one of the UBM layers is directly connected to a parametric Josephson wafer” (emphasis added) is indefinite because (a) it recites twice “a first one of the UMB layers” and it is unclear if there are two different layers or one and (b) there is no same UBM (118) in the specification which is connected to both a top of a solder bump (116) and the parametric Josephson wafer (102/120) because said wafer is actually on a bottom of the solder bump (116, Fig. 1).
Fourth, the limitation “a first one of the UBM layers is directly connected to the parametric Josephson wafer on a first side of the parametric Josephson wafer, is directly connected to the one or more first solder bumps”(emphasis added) is unclear because (a) “first solder bumps” lacks proper antecedent basis and (b) per the specification, a single UBM (118) can only be connected to a single solder bump (116, Fig. 1).
Fifth, the limitation “a first one of the UBM layers is directly connected to the parametric Josephson wafer on a first side of the parametric Josephson wafer, is directly connected to the one or more first solder bumps, and is not directly connected to a through-substrate via of a plurality of through-substrate vias on the first side of the parametric Josephson wafer” (emphasis added) is indefinite because it requires the through-substrate vias (122) to be formed on the parametric Josephson wafer (102/120) wherein, per the specification said vias (122) are formed on a separate wafer (104, Fig. 1).
Sixth, the limitation “a second one of the UBM layers is directly connected….” (emphasis added) is indefinite because the claim previously recites “a second one of the UBM is on the bottom…” (emphasis added) and it is unclear if they refer to the same or different UBMs.
Seventh, “a first underfill that encapsulates the parametric Josephson wafer” is unclear as per the specification (Fig. 1) the underfill (126) encapsulates parametric Josephson devices (120) and not a wafer.
Eighth, “the parametric Josephson wafer is disposed between two of the plurality of bump-bonds” is unclear as per the specification (Fig. 1) is unclear as per the specification (Fig. 1) a wafer is not between two bump-bonds (114) but rather two parametric Josephson devices (120) are between two bump-bonds (114).
None of dependent claims 2-4 address these deficiencies and are rejected along with base claim 1.
The level of indefiniteness of claim 1 precludes a prior art rejection per MPEP 2173.06 – “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art”.
Regarding claim 3, “wherein the parametric Josephson wafer of a plurality of parametric Josephson wafers is located on the first side of the parametric Josephson wafer” is unclear as per Fig. 1 there appears to be only one parametric Josephson wafer and because it is unclear how a wafer can be place of a first side of itself. The claim appears to be confusing parametric Josephson wafer with parametric Josephson wafer devices.
Also, “at least one superconducting qubit is located on the second side of the superconducting qubit wafer” is indefinite as the qubits (124) are not located on the second side (bottom per base claim 1) the superconducting qubit wafer (104/124).
In addition, the claim recites “at least one through-substrate via” while base claim 1 recites a singular and a plurality thereof; it is unclear if the via of claim 3 is related or not to the vias of claim 1.
In addition, “the third side of the superconducting qubit wafer” lacks proper antecedent basis.
Dependent claim 4 does not address these deficiencies.
Regarding claim 4, “the at least one parametric Josephson device” lacks proper antecedent basis.
Regarding claim 21, the claim is indefinite for multiple reasons:
First, “one or more parametric Josephson devices (insert “are”?) disposed on a first surface of the first wafer” and “one or more superconducting qubits (insert “are”?) disposed on a second surface of the second wafer” are grammatically confusing. Examiner’s suggestions in parenthesis.
Second, “under-bump metallization layers respectively coupled to a top and a bottom of one or more solder bumps and bump-bonded to the first surface of the first wafer and a third surface of the second wafer” (emphasis added) is indefinite because, per Fig. 1, only wafers 102 and 104 are bump-bonded via bump-bonds 114. UBMs 118 are not bump-bonded to any structure because UBMs 118 are part of the bump-bonds 114.
The second reason of indefiniteness precludes a prior art rejection per MPEP 2173.06 – “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art”.
Response to Arguments
Applicant's arguments filed 8.25.2026 have been fully considered but they are not persuasive.
The applicant alleges that claims 1 and 21, as amended, are definite (see pg. 8). This is not persuasive as the claims are indefinite in view of the amendment filed 8.25.2026; see rejections above.
The applicant alleges that claims 1 and 21, as amended, are allowable (see pg. 10). A determination of allowability could not be made in view of the indefiniteness rejections included above. Furthermore, a prior art rejection is not included herein because, per MPEP 2173.06, “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Patent Examiner, Art Unit 2818
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