DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 23 January 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim 1 and its dependent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. See 35 USC § 103 rejection below.
In summary, the application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-6, 8, 10-13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Uchida ‘869 (US 2009/0027869 A1) in view of Yoshida (WO 2019/208127 A1; see NPL for English translation).
Regarding claim 1, Uchida ‘869 teaches a semiconductor package (Figs. 10A-10B, ¶ [0027]), comprising:
a semiconductor die (Fig. 10B, ¶ [0035]: 101; Fig. 2A, ¶ [0044] shows 101 is from wafer 101a; hence 101 is a semiconductor die) including an interface region (101b is a photo acceptor unit; see Fig. 10B, ¶ [0035], [0044], ¶ [0092]) at a top side (top surface of 101) of the semiconductor die (Fig. 10B shows 101b on top of 101);
a polymer structure (Fig. 10B, ¶ [0092]: 502 is a frame member; also ¶ [0041]: frame member made of photo-reactive resins such as acrylic resins, known in the art as polymers) formed on the top side (Fig. 10B shows 502 on the top surface of 101), the polymer structure surrounding the interface region (Fig. 10B shows 502 surrounding 101b) and extending from the top side to a first height (Fig. 10B shows 502 extending from top of 101 to a vertical height), wherein the polymer structure has an inner sidewall profile (inner sidewall of 502) that forms a cavity (Fig. 10B shows a cavity formed by the inner sidewall of 502); and
an encapsulation structure (Fig. 10B, ¶ [0035], ¶ [0090]: 106) surrounding the polymer structure (Fig. 10B shows 106 surrounds 502) and encasing the semiconductor die (Fig. 10B shows 106 encase 101), wherein the encapsulation structure extends from the top side to a second height (Fig. 10B shows 106 extending from top of 101 to a vertical height) less than the first height (Fig. 10B and ¶ [0089] shows height of 106 is less than the height of 502).
Uchida ‘869 further teaches the interface region to be a sensor (¶ [0037] ). However, Uchida ‘869 does not teach a semiconductor package wherein the inner side wall profile of the structure that forms the cavity over the interface region to be is an uneven inner side wall comprising two or more troughs such that the uneven inner sidewall profile includes a first diameter and a second diameter different than the first diameter.
Yoshida, in the same field of invention, teaches a semiconductor package (210, see Figs. 5-6) with a sensor (16d) in the interface region (top surface of 16) of a die (16), wherein the inner side wall profile (A, B, and C; see Examiner Fig. 1) of the structure (22&224) that forms the cavity (cavities of 22a, 224a, and 224c) over the interface region (16d) to be is an uneven inner side wall (A, B, and C all have different diameters) comprising two or more troughs (22a and 224c; note: A is a sidewall of trough 22a and C is a sidewall of an trough 224c) such that the uneven inner sidewall profile includes a first diameter (diameter of A varies) and a second diameter (diameter of 224c) different than the first diameter.
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Examiner Fig. 1. Taken from Yoshida Fig. 5.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yoshida into the device of Uchida ‘869 to form the inner side wall of the polymer structure to have two or more troughs having different diameters. The ordinary artisan would have been motivated to modify Uchida ‘869 in the manner set forth above for at least the purpose of enabling a sensor device (Yoshida ¶ [0100] of English translation ) that is waterproof, through the use of an O-ring (OR, see Fig. 6), while suppressing any performance reduction (¶ [0060]).
Regarding claim 2, Uchida ‘869 et al. teach the semiconductor package of claim 1, wherein the polymer structure comprises of a light-sensitive polymer material (Uchida ‘869 ¶ [0041]: 102 is made of photo-reactive resin materials curable by light, such as acrylic resins).
However, Uchida ‘869 et al. do not teach the polymer structure comprising of two or more layers stacked on top of another.
Uchida ‘869, through a different embodiment (Figs. 11A-11C, ¶ [0028]), teaches a polymer structure (Fig. 11F, ¶ [0101]: 602) comprising of two or more layers (Fig. 11C, ¶ [0098]: 602a & 602b) stacked on top of another (as shown in Figs. 11C-11F, 602a & 602b are vertically stack on top of another to form 602).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Uchida ‘869 into the device of Uchida ‘869 et al. to have a polymer structure be comprised of a stack two or more layers of light-sensitive polymer material on top of another. The ordinary artisan would have been motivated to modify Uchida ‘869 et al. in the manner set forth above for at least the purpose of using a dual-layered polymer structure to increase the over-all thickness of the polymer structure to an optimized height of greater than 0.08 mm (Uchida ‘869 ¶ [0102], see also Fig. 4A and ¶ [0039], ¶ [0053]) for the further purpose of reducing the complexity of removing a solvent used in handling the resin from which the polymer is manufactured from (Uchida ‘869 ¶ [0102]).
Regarding claim 4, the semiconductor package of claim 2, wherein a thickness of individual light-sensitive polymer layers is approximately 50 to 70 microns (Uchida ‘869 Fig. 11C and ¶ [0099] teaches the over-all thickness of layer 602c is 0.12 mm; since 602c is composed of two layers 602a& 602b, then the average thickness of each layer is 0.06 mm, which translates to 60 microns).
Regarding claim 5, the semiconductor package of claim 1, wherein the interface region is exposed to an environment of the semiconductor package through the cavity (Uchida ‘869 Fig. 10B shows 110b is exposed to outside environment through the cavity of 502, with the cavity of 502 allowing light to enter; see also Uchida ‘869 ¶ [0038]; alternatively, Yoshida teaches the device having a through hole Ga that allows communication between the outside and the interior of the device; see Fig. 3A and ¶ [0041] of the English translation ) .
Regarding claim 6, the semiconductor package of claim 1, wherein the cavity has a first opening (224a; see Yoshida Figs. 5-6) with a first area (the cross-sectional area of 224a) and a second opening (22a) with a second area (the smallest cross-sectional area of 22a) less than the first area (as shown in Yoshida Fig. 6, the smallest cross-sectional area of 22a is less than the cross-sectional area of 224a).
Regarding claim 8, the semiconductor package of claim 6, wherein the second area (smallest cross-sectional area of 22, see Yoshida Fig. 6) of the second opening (22a) includes the interface region of the semiconductor die (Yoshida Fig. 6 shows 16d within the second area of the second opening 22a).
Regarding claim 10, the semiconductor package of claim 1, wherein the uneven inner sidewall profile includes U-shaped corrugations (Yoshida Figs. 5-6 shows 224c to be a U-shaped trough and 224a/22a to be a U-shaped trough), a ribbed surface, an undulating surface, or a combination thereof.
Regarding claim 11, the semiconductor package of claim 1, wherein the uneven inner sidewall profile includes at least one groove (224c, see Yoshida Fig. 5 & 6) configured to capture a mold compound (Uchida ‘869 ¶ [0035]: resin, which forms 106 in Uchida ‘869 Fig. 10B) of the encapsulation structure (Uchida ‘869 in view of Yoshida teaches this since Yoshida has an O-ring in 224c ).
Regarding claim 12, the semiconductor package of claim 1, wherein the encapsulation structure includes a mold compound (Uchida ‘869 ¶ [0035]: resin, which forms 106 in Uchida ‘869 Fig. 10B), and wherein the cavity is free of the mold compound (Uchida ‘869 Fig 10B shows 106 is not found in the cavity formed by 502; alternatively, Uchida ‘869 in view of Yoshida teaches this since Yoshida has an O-ring in 224c).
Regarding claim 13, the semiconductor package of claim 1, further comprising:
a die pad (Uchida ‘869 Fig. 10B: die pad portion of lead frame 104 is under 101)
at least one lead finger (Uchida ‘869 Fig. 10B and ¶ [0035]: portions leadframe 104 that are connected to metal filaments 105) of a lead frame (Uchida ‘869 Fig. 10B, ¶ [0035]: 104); and
at least one bond wire (Uchida ‘869 Fig. 10B, ¶ [0035]: 105), wherein:
the semiconductor die is attached to the die pad of the lead frame (as shown in Uchida ‘869 Fig. 10B, 101 is attached to the die pad portion of 104), the top side of the semiconductor die facing away from the die pad (as shown in Uchida ‘869 Fig. 10B, the top side of 101 faces away from the die pad); and the
at least one bond wire couples the semiconductor die to the at least one lead finger of the lead frame (as shown in Uchida ‘869 Fig. 10B and ¶ [0051], 105 couples 101 to the lead finger of 104).
However, the embodiment of Uchida ‘869 Fig. 10B does not explicitly teach: a bond pad provided on the top of the semiconductor die.
Uchida ‘869, through a different embodiment (Fig. 12, ¶ [0006]), teaches a bond pad (¶ [0006]: 81a) provided on the top of the semiconductor die (¶ [0006]: 81; as shown in Fig. 12, 81a is on top of 81).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of a different embodiment of Uchida ‘869 into the device of Uchida ‘869 et al. to provide bond pads on the top of a semiconductor die in a semiconductor package at least comprising of a die pad and a lead finger of the lead frame, the semiconductor die attached to the die pad, and as least one bond wire coupling the bond pad of the semiconductor die to at least one lead finger of the lead frame. The ordinary artisan would have been motivated to modify Uchida ‘869 et al. in the manner set forth above for at least the purpose of providing electrical connections to the semiconductor die using the bond pad as a coupling agent between the semiconductor die and the bonding wire (Uchida ‘869 ¶ [0006]).
Regarding claim 15, Uchida ‘869 et al. teach the semiconductor package of claim 1, but does not explicitly teach wherein the first height of the polymer structure is approximately 120 to 180 microns.
Uchida ‘869, through a different embodiment (Figs. 1A-1B), teaches a semiconductor package wherein the first height of the polymer structure is approximately 120 to 180 microns (Uchida ‘869 ¶ [0039]: “a height of the frame member… more preferably equal to or larger than 0.1 mm”; this converts to greater than 100 microns)
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to routinely optimize the range of the height of the polymer structure according to the design specifications of a specific embodiment in order to prevent the wire bonds from contacting the metal molds 111a / 111b (Uchida ‘869 Fig. 4A-4B) that are used in manufacturing the device (see Uchida ‘869 Fig. 4A, ¶ [0039]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida ‘869 (US 2009/0027869 A1) and Yoshida (WO 2019/208127 A1) as applied to claim 2 above, and in further view of Liao (US 2020/0098736 A1).
Regarding claim 3, Uchida ‘869 et al. and another embodiment of Uchida ‘869 teaches the semiconductor package of claim 2, wherein the light-sensitive polymer material includes acrylic resin (Uchida ‘869 ¶ [0041]).
However, Uchida ‘869 et al. and another embodiment of Uchida ‘869 do not teach the light-sensitive polymer material includes polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or a combination thereof.
Liao, in the same field of invention, teaches a device wherein the light-sensitive polymer material includes polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or a combination thereof (¶ [0033]: optically connecting various elements using layer 502, which uses materials listed above).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the acrylic resin in the polymer structure of Uchida ‘869 with either a polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or a combination thereof, for the predictable result of providing optical coupling (Liao ¶ [0033]) or, alternatively, for the purpose of substituting equivalent materials known in the prior art for the same purpose of providing optical coupling (Liao ¶ [0033]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida ‘869 (US 20090027869 A1) and Yoshida (WO 2019/208127 A1) as applied to claim 6 above, and in further view of Uchida ‘169 (US 2010/0142169 A1).
Regarding claim 9, Uchida ‘869 et al. teach the semiconductor package of claim 6, wherein the polymer structure forms a ring shape (Uchida ‘869 Fig. 10A shows 502 having a ring shape). However, Uchida ‘869 et al. do not teach: wherein: the first opening of the cavity has a diameter of approximately 120 to 140 microns; and the second opening of the cavity has a diameter of approximately 80 to 100 microns.
Uchida ‘169, in the same field of invention, teaches having two different diameters for the ring shape (Fig. 7A-7B, ¶ [0069]-[0076]: “a frame material 302… in which the width is decreased as approaching the bottom section”; Figs. 8A-8B, ¶ [0077]-[0081]: “the frame material 302 is an inverse-trapezoid shaped, in which the width is decreased as approaching to the bottom section, the side surface of the frame material 302 is sloped toward downward and inward”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to routinely optimize the diameters of a first opening and a second opening of a cavity of a ring-shaped polymer structure, wherein the diameter of the second opening is smaller than the diameter of the first opening, in a semiconductor package at least comprising of a semiconductor die having an interface region at its top side, the ring-shaped polymer structure surrounding the interface region, with the polymer structure extending from the top side of the semiconductor die and having an uneven inner sidewall that forms the cavity, and an encapsulating structure surrounding the polymer structure. The ordinary artisan would have been motivated to modify Uchida ‘869 et al. in the manner set forth above for at least the purpose of using the larger diameter of the first opening (Uchida ‘169 ¶ [0070]) to allow more angled incident light to pass through the cavity ( Uchida ‘169 [0073]), with this light used for the curing of the polymer material during its manufacturing (Uchida ‘169 Fig 2C, ¶ [0072], ¶ [0048]) and for the further purpose of using the smaller diameter of the second opening to allow a smaller size of the photosensitive element (Uchida ‘169 ¶ [0076]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida ‘869 (US 20090027869 A1) in view of Yoshida (WO 2019/208127 A1, as applied to claim 1 above, and further in view of Maruyama (US 2019/0354013 A1).
Regarding claim 14, Uchida ‘869 et al. teach the semiconductor package of claim 1, wherein the interface region of the semiconductor die is a light receiving device (Uchida ‘869 [0040]: “photo acceptor unit 101b”) or a pressure sensing device (Yoshida ¶ [0002] of the English translation) .
However, Uchida ‘869 et al. do not explicitly teach the interface region of the semiconductor die includes a humidity sensor, a temperature sensor, a light emitting diode, a solid-state laser, a photodiode, or a combination thereof.
Maruyama, in the same field of invention, teaches a light receiving devices such as photodiodes (¶ [0104]: light-receiving devices such as photodiodes, optical sensors, and CMOS image sensors).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Maruyama into the device of Uchida ‘869 et al. to have an interface region of a semiconductor die to be comprising of a photodiode in a semiconductor package at least comprising of the semiconductor die having the interface region at the top of the semiconductor die, a polymer structure formed on the top of the semiconductor die and surrounding the interface region, wherein an inner side wall of the polymer structure forms a cavity over an interface region, and an encapsulation structure surrounding the polymer structure and encasing the semiconductor die. The ordinary artisan would have been motivated to modify Uchida ‘869 et al. in the manner set forth above for at least the purpose of enabling light-sensing optical packages by substituting a generic light-sensing interface region of Uchida ‘869 with a specific type of semiconductor device such as photodiodes, optical sensors, and CMOS image sensors (Maruyama ¶ [0104]).
Allowable Subject Matter
Claims 7 and its dependent claim 37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the Uchida ‘869 et al. teach the semiconductor package of claim 6, wherein the polymer structure comprises one or more base layers (22 & 224, see Yoshida Fig. 5) corresponding to the first opening (224a) of the cavity.
However, no prior art of record anticipates or renders obvious: one or more protruded layers corresponding to the second opening of the cavity, wherein individual base layers alternate with individual protruded layers.
Claims 27-36 and 38-40 are allowed.
Note: The discourse below uses the following prior art references: Nakanishi (US 2016/0068387 A1), Uchida ‘869 (US 2009/0027869 A1), and Tuttle (US 2005/0110889 A1).
Regarding claim 27, Nakanishi teaches a semiconductor package (Fig. 13), comprising:
a semiconductor die (101, see Fig. 11) including an interface region (102) on a surface of the semiconductor die;
a polymer wall (1350, see Fig. 13) formed on the surface, the polymer wall circumscribing the interface region and extending from the surface to a first height (vertical height of 1350), wherein the polymer wall includes two or more first layers (Fig. 13 shows two or more 1350) corresponding to a first cross-sectional area (internal cross-sectional area of the two 1350); and
a mold structure (160) encapsulating the semiconductor die.
However, Nakanishi does not teach: the mold structure extending from the surface to a second height less than the first height.
Uchida ‘869, in the same field of invention, teaches a semiconductor package (Fig. 10B) wherein the mold structure (106) extending from the surface (top surface of 101) to a second height (vertical height of the top surface of 106) less than the first height (vertical height of 502).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Uchida ‘869 into the device of Nakanishi to adjust the mold structure to extend to a height, with respect to the top surface of the semiconductor die, that is less than the height of the polymer wall. The ordinary artisan would have been motivated to modify Nakanishi in the manner set forth above for at least the purpose of preventing unwanted permeation of the resin that comprises of the mold structure into the hollow portion of the polymer wall (502; see Uchida ‘869 ¶ [0090], [0092] ) and for adjusting the pressure that the mold structure is forcing on the polymer wall (¶ [0091] ).
Nakanishi further teach the semiconductor package to be an imager (¶ [0064] ). However, Nakanishi et al. do not teach: one or more second layers corresponding to a second cross-sectional area different than the first cross- sectional area.
Tuttle, in the same field of invention, teaches a semiconductor package (Fig. 4) wherein one or more second layers (340 & 240) corresponding to a second cross-sectional area (internal cross-sectional area of 340 & 240) different than the first cross-sectional area (internal cross-sectional area of 233).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tuttle into the device of Nakanishi to add one or more second layers having a cross-sectional area different from the two or more first layers. The ordinary artisan would have been motivated to modify Tuttle in the manner set forth above for at least the purpose of using the one or more second layers to improve the accuracy of the optic member (320, see Tuttle ¶ [0043]) of a microelectronic imager by adjusting the focal distance of the optic member with respect to the image sensor (216, see ¶ [0042]), for simplifying the method of manufacturing the package (¶ [0044]), and for reducing the size of conventional imagers (¶ [0045]).
However, no prior art of record was found to anticipate or render obvious the above-mentioned semiconductor package wherein the two or more first layers alternating with the one or more second layers.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Examiner, Art Unit 2899