DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/17/2026 has been entered.
Status of the Application
The Amendment filed on 1/2/2026, responding to the Office action mailed on 11/17/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-16 and 31-34 are pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 31-32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 20210028145 A12)
Re Claim 31 Yu teaches a bonded structure (FIG. 8C) comprising:
a carrier (200) [0029] having a nonconductive layer (202) and conductive features (204) at least partially embedded in the nonconductive layer (202);
a first die stack (120 on left) [0017] having a first top die (top 122) and a first bottom die (bottom 122 row), the first top and first bottom dies of the first die stack (120) each having a respective nonconductive layer (126) [0017] and conductive features (122a ) [0017], the first bottom die of the first die stack (120) bonded to the carrier (200);
a protective layer (130) [0016] having an upper surface that is coplanar with a top surface of the first top die (top 122 on left in FIG. 8C) and adjacent to the first die stack (120 on left);
a bridging layer (140) [0019] comprising a nonconductive layer (142) and a conductive interconnect (144),
the bridging layer (140) deposited over the first top die (top 122 on left in FIG. 8C) of the first stack (120 on left) without an adhesive (no adhesive taught between 120 and 140); and
a second die stack (120 on right) having a second bottom die (bottom 122) direct hybrid bonded ([0040] states, “In some embodiments, the integrated circuits 110 and 120 are connected to the redistribution layer 140 through the connector 112, 124 by flip chip bonding, hybrid bonding…”) to an upper surface of the bridging layer (140),
wherein the conductive interconnect (144) of the bridging layer (140) provides electrical communication (120 on left and right are both connected to circuit 110 [0016]) between the first (120 on left) and second die stacks (120 on right, FIG. 8C).
The limitation “direct hybrid bonded” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Re Claim 32 Yu teaches the bonded structure of Claim 31, further comprising a third die stack (170 on left, FIG. 8C) [0022] bonded to the carrier (200), the bridging layer disposed (140) over a third top die (top die in 170 on left) of the third stack (170).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov (US 20220093517 A1) in view of Yu (US 20170301650 A1).
Re Claim 1 Aleksov teaches a bonded structure (FIG. 16) comprising:
a carrier (104) [0052];
a first plurality of die stacks (102-1 and 102-2) [0035], each die stack comprising a plurality of dies [0035], each die stack of the first plurality of die stacks bonded to the carrier (104);
a protective layer (126, [0026] “mold material”) having an upper surface that is coplanar with a top surface of a topmost die (102-1 and 102-2) of the first plurality of die stacks and adjacent to the first plurality of die stacks (FIG. 16); and
a bridging layer (106 and 112) [0030] comprising a nonconductive bridge layer (106) and a lateral conductive interconnect (112) deposited over the first plurality of die stacks (102-1 and 102-2);
wherein the lateral conductive interconnect (112) provides electrical communication between the first plurality of die stacks (102-1 and 102-2, FIG. 16).
Aleksov does not teach the bridging layer deposited over the first plurality of die stacks without an adhesive;
Yu teaches the bridging layer (46) [0033] deposited over the first plurality of die stacks (136) [0015] without an adhesive (FIG. 12 and 28);
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu into the structure of Aleksov since Yu is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Yu in combination with Aleksov in the above manner for the motivation of bonding the bridging layer to the die stacks without an adhesive. Not having an adhesive will allow for one to save space on the device during manufacturing because not using an adhesive requires less materials to go into the chip and will therefore save space. [0001] states, “With the evolving of semiconductor technologies, semiconductor chips/dies are becoming increasingly smaller. In the meantime, more functions need to be integrated into the semiconductor dies.”
Re Claim 2 Aleksov in view of Yu teaches the bonded structure of Claim 1, further comprising a plurality of contact features (Aleksov, 116) [0030] at least partially embedded in the nonconductive bridge layer (106),
wherein the lateral conductive interconnect (112) provides electrical communication between at least two of the plurality of contact features (116, FIG. 16).
Re Claim 3 Aleksov in view of Yu teaches the bonded structure of Claim 1, further comprising at least one die stack (Yu, 136) [0015] directly bonded without an adhesive to the bridging layer (46, FIG. 11).
Re Claim 11 Aleksov teaches a bonded structure (FIG. 16) comprising:
a first die stack (102-1) comprising a first plurality of dies [0035];
a second die stack (102-2) comprising a second plurality of dies [0035];
a protective layer (126, [0026] molding layer“) disposed at least about lateral sides of the first (102-1) and second die (102-2) stacks and between the first and second die stacks, the protective laver (126) having an upper surface that is coplanar with a top surface of a topmost die of the first and second die stacks (FIG. 16); and
a bridging layer (106 and 112) [0030] deposited over the first die stack (102-1), the second die stack (102-2), and the protective layer (126), the bridging layer (106 and 112) providing electrical communication between at least one die of the first die stack (102-1) and at least one die of the second die stack (102-2, FIG. 16).
Aleksov does not teach the bridging layer deposited over the first die stack, the second die stack, and the protective layer without an adhesive.
Yu teaches the bridging layer (46) [0033] deposited over the first die stack (136 on left) [0015], the second die stack (136 on right), and the protective layer (44) [0030] without an adhesive (FIG. 12 and 28).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu into the structure of Aleksov since Yu is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Yu in combination with Aleksov in the above manner for the motivation of bonding the bridging layer to the die stacks without an adhesive. Not having an adhesive will allow for one to save space on the device during manufacturing because not using an adhesive requires less materials to go into the chip and will therefore save space. [0001] states, “With the evolving of semiconductor technologies, semiconductor chips/dies are becoming increasingly smaller. In the meantime, more functions need to be integrated into the semiconductor dies.”
Claims 4-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov (US 20220093517 A1) in view of Yu (US 20170301650 A1) as applied to claim 1 above, and further in view of Yu (US 20210028145 A1, “Yu2” hereafter).
Re claim 4 Aleksov in view of Yu teaches the bonded structure of Claim 1, but does not teach the semiconductor device further comprising a second plurality of die stacks directly bonded to the bridging layer and a bridging element directly bonded to the second plurality of die stacks.
Yu2 teaches the semiconductor device further comprising a second plurality of die stacks (220, FIG. 1F) [0032] directly bonded to the bridging layer (200) [0032] and a bridging element directly bonded to the second plurality of die stacks ([0032], “In some embodiments, an underfill 226 is provided between the die 220 and the redistribution layer structure 200 to seal the region therebetween. However, in some alternative embodiments, the die 220 is a bare (unpackaged) die.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu2 into the structure of Aleksov in view of Yu since Yu2 is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Yu2 in combination with Aleksov in view of Yu in the above manner for the motivation of building a bonded structure semiconductor device. Yu2 [0002] states, “ . . . 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth . . .”
Re claim 5 Aleksov in view of Yu and Yu2 teaches the bonded structure of Claim 4, further comprising at least one test pad at least partially embedded in the bridging layer, wherein the test pad is in electrical communication (Yu2, [0056] says, “The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing. . . “) with the first plurality of stacks (220 on left) and the second plurality of stacks (220 on right, FIG. 2A).
Re claim 6 Aleksov in view of Yu and Yu2 teaches the bonded structure of Claim 1, further comprising a bridging element (Yu2, 208) ([0031], “plurality of under-ball metallurgy (UBM) patterns”) directly bonded (FIG. 2F), without an adhesive, to the bridging layer.
Re Claim 7 Aleksov in view of Yu and Yu2 teaches the bonded structure of Claim 6, further comprising a cavity (open space between 102-1 and 102-2) between a first stack and a second stack (FIG. 15).
Re claim 9 Aleksov in view of Yu and Yu2 teaches the bonded structure of Claim 1, the bonded structure of Claim 1, wherein a first nonconductive bonding layer of at least one stack (Yu2, 192) [0029] (FIG. 8A) of the plurality stacks is directly bonded to a second nonconductive bonding layer (202) [0027] of the carrier without an intervening adhesive, and wherein a first contact feature (194) [0026] of at least one stack of the plurality stacks is directly bonded to a second contact feature (204) [0027] of the carrier without an intervening adhesive.
Re claim 10 Tomishima in view of Yu and Yu2 teaches the bonded structure of claim 1, wherein a material of the protective layer (Yu2, 202) (FIG. 8C) is the same as a material of the bridging layer (192, Layers 202 and 192 are dielectric layers as stated in paragraphs [0027] & [0025].)
Claims 8 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Aleksov (US 20220093517 A1) in view of Yu (US 20170301650 A1) as applied to claims 1 & 11 above, and further in view of Tomishima (US 20210391301 A1).
Re Claim 8 Aleksov in view of Yu teaches the bonded structure of Claim 1, but does not teach each stack of the first plurality of stacks comprises a first die bonded to a second die, without an adhesive.
Tomishima teaches the bonded structure of Claim 1, wherein each stack of the first plurality of stacks comprises a first die bonded to a second die, without an adhesive (Tomishima, 1st and 2nd dies as shown below, [0033] says, “ . . . Interconnects 338 represent power supply interconnects, and interconnects 337 may represent communication interconnects . . . ”).
(Image below is a fragment of Tomishima, FIG. 3A showing the 1st and 2nd dies)
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Tomishima into the structure of Aleksov in view of Yu since Tomishima is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Tomishima in combination with Aleksov in view of Yu in the above manner for the motivation of bonding dies to each other without an adhesive to drive towards dies with increased computing performance. [0002] states, “The drive towards increased computing performance has yielded many different packaging solutions.”
Re Claim 12 Aleksov in view of Yu teaches the bonded structure of Claim 11, but does not teach the first plurality of dies within the first die stack are direct hybrid bonded.
Tomishima teaches the first plurality of dies within the first die stack (1st 330 from left, FIG. 3A [0031]) are direct hybrid bonded. ([0033] states, “. . . hybrid wafer bonding may be used to interconnect the stacked second dies.”) The limitation “direct hybrid bonded” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Tomishima into the structure of Aleksov in view of Yu since Tomishima is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Tomishima in combination with Aleksov in view of Yu in the above manner for the motivation of hybrid bonding dies to each other to drive towards dies with increased computing performance. [0002] states, “The drive towards increased computing performance has yielded many different packaging solutions.”
Re Claim 13 Aleksov in view of Yu and Tomishima teaches the bonded structure of claim 11, wherein the second plurality of dies (2nd 330 from left, FIG. 3A [0031]) within the second die stack are direct hybrid bonded. ([0033] states, “. . . hybrid wafer bonding may be used to interconnect the stacked second dies.”) The limitation “direct hybrid bonded” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Re Claim 14 Aleksov in view of Yu and Tomishima teaches the bonded structure of claim 11, wherein the first die stack (1st 330 from left, FIG. 3A) and the second die stack (2nd 330 from left) are direct hybrid bonded to a carrier (Tomishima, 320) (FIG. 3F) [0036]. The limitation “direct hybrid bonded” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Re Claim 15 Aleksov in view of Yu and Tomishima teaches the bonded structure of Claim 11, wherein the first die stack (1st 330 from left, FIG. 3A) and the second die (2nd 330 from left) stack are direct hybrid bonded to a bridging element (Tomishima, 325) (FIG. 3F). The limitation “direct hybrid bonded” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Aleksov (US 20220093517 A1) in view of Yu (US 20170301650 A1) and Tomishima (US 20210391301 A1) as applied to claims 11, 15 above, and further in view of Yu (US 20210028145 A1, “Yu2” hereafter).
Re Claim 16 Aleksov in view of Yu and Tomishima teaches the bonded structure of Claim 15, but does not teach a third die stack comprising a third plurality of dies, wherein the third die stack is direct hybrid bonded to the bridging layer, and a fourth die stack comprising a fourth plurality of dies, wherein the fourth die stack is direct hybrid bonded to the bridging layer.
Yu2 teaches further comprising a third die stack (see image below) comprising a third plurality of dies (220) [0032], wherein the third die stack is direct hybrid bonded to the bridging layer (192,194) (FIG. 6), and a fourth die stack (see image below) comprising a fourth plurality of dies (220), wherein the fourth die stack is direct hybrid bonded to the bridging layer (192,194). The limitation “direct hybrid bonded” is merely a product-by-process limitation. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
(Image below is a fragment of Yu2, FIG. 6 showing the 3rd and 4th die stacks)
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It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yu2 into the structure of Aleksov in view of Yu and Tomishima since Yu2 is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Yu2 in combination with Aleksov in view of Yu and Tomishima in the above manner for the motivation of building a bonded structure semiconductor device. Yu2 [0002] states, “ . . . 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth . . .”
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20210028145 A12) as applied to claim 31 above, and further in view of Gao (US 20200013754 A1).
Re Claim 33 Yu teaches the bonded structure of Claim 31, but does not teach the conductive interconnect of the bridging layer comprises a printed wire.
Gao teaches wherein the conductive interconnect (110) [0036] (FIG. 1) of the bridging layer (108) comprises a printed wire. [0036] states, “Bonding surfaces 108 of the die 102 can include conductive features 110, such as TSVs, traces, pads, . . . “
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Gao into the structure of Yu since Gao is about bonded die sacks.
The ordinary artisan would have been motivated to modify Gao in combination with Yu in the above manner for the motivation of building a bonded structure semiconductor device with the bridging layer containing a printed wire to allow the device to route signals within the semiconductor device. Gao [0004] states, “Packaged semiconductor dies can also be provided in “stacked” arrangements, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow a number of different dies or devices to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation . . .”
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20210028145 A12) as applied to claim 31 above, and further in view of Woychik (US 20150270209 A1).
Re Claim 34 Yu teaches the bonded structure of Claim 31, but does not teach a wire bond that connects the first and second die stacks.
Woychik teaches further comprising a wire bond (47) [0041] (FIG. 6G) that connects the first and second die stacks (301 & 302) [0069].
It would have been obvious to one of ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Woychik into the structure of Yu since Woychik is a patent about bonded die stacks.
The ordinary artisan would have been motivated to modify Woychik in combination with Yu in the above manner for the motivation of adding a wire bond the semiconductor device to connect the dies stacks, so the die stacks can share signals inside the semiconductor device. Woychik [0003] states, “An IC may include conductive elements, such as pathways, traces, tracks, vias, contacts, pads such as contact pads and bond pads, plugs, nodes, or terminals for example, that may be used for making electrical interconnections with a circuit platform. These arrangements may facilitate electrical connections used to provide functionality of ICs.”
Response to Arguments
Applicant’s arguments with respect to claims 1-16 and 31-34 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 5/27/26
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