DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 2, 2025 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the wherein the control voltage is a gate-programmed control voltage stored on the gate of both the first and the third TFT in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Therefore, the a combined first-third TFT stack in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Therefore, the wherein the programmed current is maintained during a hold in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Therefore, the wherein the second TFT is configured to couple a programmed gate control voltage to the first and third TFTs in claim 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. The limitation “wherein the control voltage is a gate-programmed control voltage stored on the gate of both the first and the third TFT”, wherein coupling the third TFT to the first TFT in series increases an effective output impedance of a combined first-third TFT stack to enable analog current-level control of to the power consuming device” and “wherein the programmed current is maintained during a hold” lack proper antecedent basis in the specifications.
Regarding claim 18. The limitation “wherein the second TFT is configured to couple a programmed gate control voltage to the first and third TFTs” lack proper antecedent basis in the specifications.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 1-3, 10, 12, 18 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1. Claim 1 recites the limitation “wherein the control voltage is a gate-programming control voltage stored on the gate of both of the first TFT and the third TFT” in the ninth line of the claim language.
Applicant does not have written support on the originally filed specifications for wherein the control voltage is a gate-programming control voltage stored on the gate of both of the first TFT and the third TFT.
Claims 2-3, 10, 12 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 1. Claim 1 recites the limitation “effective output impedance of a combined first-third TFT stack” in the last line of the claim language.
Applicant does not have written support on the originally filed specifications for effective output impedance of a combined first-third TFT stack.
Claims 2-3, 10, 12 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 1. Claim 1 recites the limitation “to enable analog current-level control of the power consuming device” in the last line of the claim language.
Applicant does not have written support on the originally filed specifications for to enable analog current-level control of the power consuming device.
Claims 2-3, 10, 12 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 1. Claim 1 recites the limitation “wherein the programmed current is maintained during a hold interval” in the last line of the claim language.
Applicant does not have written support on the originally filed specifications for wherein the programmed current is maintained during a hold interval.
Claims 2-3, 10, 12 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claim 18. Claim 18 recites the limitation “providing a first TFT and a third TFTs serially to form a current-drive pair having an increased effective output impedance” in the fourth and fifth line of the claim language.
Applicant does not have written support on the originally filed specifications for providing a first TFT and a third TFTs serially to form a current-drive pair having an increased effective output impedance.
Regarding claim 18. Claim 18 recites the limitation “wherein the second TFT is configured to couple a programmed gate control voltage to the first and third TFTs” in the tenth line of the claim language.
Applicant does not have written support on the originally filed specifications for wherein the second TFT is configured to couple a programmed gate control voltage to the first and third TFTs.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 10, 12, 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation " wherein the control voltage is a gate-programming control voltage stored on the gate of both of the first TFT and the third TFT" in the ninth and tenth line of the claim language.
It is unclear to the examiner as to what applicant is attempting to claim with this claim limitations.
Claims 2-3, 10, 12 rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 1. Claim 1 recites the limitation "the programmed current" in the last line of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-3, 10, 12 rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 1. Claim 1 recites the limitation "the programmed current" in the last line of the claim language.
It is unclear to the examiner as to what is encompassed by the programmed current.
Claims 2-3, 10, 12 rejected for dependence upon a 112(b) rejected instance claim.
Regarding claim 18. Claim 18 recite the limitation “providing a first TFT and a third TFTs serially to form a current-drive pair having an increased effective output impedance” in the fourth and fifth line of the claim language.
It is unclear to the examiner as to what is encompassed by providing a first TFT and a third TFTs serially to form a current-drive pair having an increased effective output impedance.
For the purpose of examination and compact prosecution, examiner shall interpret “providing a first TFT and a third TFTs serially to form a current-drive pair having an increased effective output impedance” to be providing a first TFT and a third TFTs serially provides control of the current to the power consuming device as support by applicant’s originally filed specifications ([Abstract])
Regarding claim 18. Claim 18 recites the limitation "a programmable gate control voltage" in the tenth line of the claim language.
It is unclear to the examiner as to what is encompassed by a programmable gate control voltage.
For the purpose of examination and compact prosecution, examiner shall interpret “a programmable gate control voltage” to be a control voltage as support by applicant’s originally filed specifications in [Abstract] for a control voltage to the first TFT for controlling an amount of the current.
Regarding claim 18. Claim 18 recites the limitation "the control voltage" in the eleventh line of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 12, 18 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Yamazaki et al (U.S. 2004/0252565).
Regarding claim 1. Yamazaki et al discloses a circuit (FIG. 2), comprising:
a first thin-film transistor (TFT) (FIG. 2, item 202) configured to output a current ([0030], i.e. two transistors 202 and 203 which control supply of current to the light emitting element) to a power consuming device (FIG. 2, item 204);
a third TFT (FIG. 2, item 203) coupled to the first TFT (FIG. 2, item 202) in series ([Abstract], i.e. the first transistor and the second transistor are all connected in series) and configured to provide the current ([0030], i.e. two transistors 202 and 203 which control supply of current to the light emitting element) to the power consuming device (FIG. 2, item 204),
a control voltage (FIG. 2, item Si; [0030], i.e. electric potential)
a second TFT configured (FIG. 2, item 201) to couple ([0032], i.e. One of the source and the drain of the switching transistor 201 is connected to a signal line Si (i=1 to x), and the other is connected to each gate of the driving transistor 202 and the current control transistor 203.) to the first TFT (FIG. 2, item 202) and the third TFT (FIG. 2, item 203), the control voltage (FIG. 2, item Si; [0030], i.e. electric potential of the video signal) controlling an amount of the current ([0022], i.e. it can be said that the current Id1 is determined only with Vgs) provided to the power consuming device (FIG. 2, item 204) by the first TFT (FIG. 2, item 202) and third TFT (FIG. 2, item 203),
Wherein the control voltage (FIG. 2, item Si; [0030], i.e. electric potential) is a gate-programming control voltage (FIG. 2, item Si; [0030], i.e. electric potential) stored ([0030]) a capacitor element 205 to store an electric potential) on the gate ([0034], i.e. The capacitor element 205 is provided to store a gate voltage of the driving transistor 202 and of the current control transistor 203) of both the first TFT (FIG. 2, item 202) and the third TFT (FIG. 2, item 203), and
wherein coupling the third TFT (FIG. 2, item 203) to the first TFT (FIG. 2, item 202) in series ([Abstract]) increases an effective output impedance of impedance of a combined first-third TFT stack to enable analog current level control ([0019]-[0021]) of the power consuming device (FIG. 2, item 204); and
a storage capacitor (FIG. 2, item 205) coupled to the first (FIG. 2, item 202), second (FIG. 2, item 201) and third (FIG. 2, item 203) TFTs, the storage capacitor (FIG. 2, item 205) configured to store the control voltage ([0034], i.e. The capacitor element 205 is provided to store a gate voltage of the driving transistor 202 and of the current control transistor 203),
wherein the programmed current is maintained during a hold interval(FIG. 1B; [0019]-[0021])
Yamazaki et al fails to explicitly disclose wherein coupling the third TFT (FIG. 2, item 203) to the first TFT (FIG. 2, item 202) in series ([Abstract]) increases an effective output impedance of impedance of a combined first-third TFT stack.
However Applicant discloses in ([0032] In some embodiments, the first TFT 202A and the third TFT 202B are connected in series (as illustrated in FIG. 2A) and configured to provide a current to the power consuming device 220
Yamazaki et al disclose wherein coupling the third TFT (FIG. 2, item 203) to the first TFT (FIG. 2, item 202) in series provides control of the current ([Abstract], i.e. a first transistor and second transistor controlling current to be supplied to the light emitting element in a pixel) to the power consuming device (FIG.2, item 204)
Therefore, Yamazaki et al inherently discloses wherein coupling the third TFT (FIG. 2, item 203) to the first TFT (FIG. 2, item 202) in series ([Abstract]) increases an effective output impedance of impedance of a combined first-third TFT stack (FIG. 2).
PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT
See also In re Ludtke, 441 F.2d 660, 169 USPQ 563 (CCPA 1971) (Claim 1 was directed to a parachute canopy having concentric circumferential panels radially separated from each other by radially extending tie lines. The panels were separated "such that the critical velocity of each successively larger panel will be less than the critical velocity of the previous panel, whereby said parachute will sequentially open and thus gradually decelerate." The court found that the claim was anticipated by Menget. Menget taught a parachute having three circumferential panels separated by tie lines. The court upheld the rejection finding that applicant had failed to show that Menget did not possess the functional characteristics of the claims.); Northam Warren Corp. v. D. F. Newfield Co., 7 F. Supp. 773, 22 USPQ 313 (E.D.N.Y. 1934) (A patent to a pencil for cleaning fingernails was held invalid because a pencil of the same structure for writing was found in the prior art.). See MPEP 2112.01 section I.
Regarding claim 3. Yamazaki et al discloses all the limitations of the circuit of claim 1 above.
Yamazaki et al further discloses further comprising a source follower ([0032], i.e. the driving transistor 202 and the current control transistor 203 are connected to a power supply line Vi (i=1 to x) and the light emitting element 204 so that a current which is supplied from the power supply line Vi is supplied to the light emitting element 204 as a drain current of the driving transistor 202 and of the current control transistor 203), wherein the source follower ([0032]) comprises the first TFT (FIG. 2, item 202).
Regarding claim 12. Yamazaki et al discloses all the limitations of the circuit of claim 1 above.
Yamazaki et al further discloses wherein the power consuming device (FIG. 12A, item Diode) is coupled between the third TFT (FIG. 12A, bottom transistor) and ground (FIG. 12A, item VSS; [0003], i.e. The electroluminescence in an electroluminescent layer includes a light emission when a singlet excited state returns to a ground state (fluorescence) and a light emission when a triplet excited state returns to a ground state (phosphorescence)).
Regarding claim 18. Yamazaki et al discloses a method for fabricating a circuit (FIG. 2) comprising:
providing a power consuming device (FIG. 2, item 204);
providing a first TFT (FIG. 2, item 202) and a third TFTs (FIG. 2, item 203) serially ([0030], i.e. two transistors 202 and 203 which control supply of current to the light emitting element) to form a current-drive pair having an increased effective output impedance;
Yamazaki et al does not explicitly disclose to form a current-drive pair having an increased effective output impedance.
However Applicant discloses in ([0032] In some embodiments, the first TFT 202A and the third TFT 202B are connected in series (as illustrated in FIG. 2A) and configured to provide a current to the power consuming device 220
Yamazaki et al discloses providing a first TFT (FIG. 2, item 202) and a third TFTs (FIG. 2, item 203) serially ([0030], i.e. two transistors 202 and 203 which control supply of current to the light emitting element) provides control of the current ([Abstract], i.e. a first transistor and second transistor controlling current to be supplied to the light emitting element in a pixel) to the power consuming device (FIG.2, item 204)
Therefore, Yamazaki et al inherently discloses providing a first TFT (FIG. 2, item 202) and a third TFTs (FIG. 2, item 203) serially ([0030], i.e. two transistors 202 and 203 which control supply of current to the light emitting element) to form a current-drive pair (FIG. 2, items 202 and 203) having an increased effective output impedance ([0022]-[0025]).
PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT
See MPEP 2112.01 section I.
coupling the first TFT (FIG. 2, item 202) and third TFTs (FIG. 2, item 203) to the power consuming device (FIG. 2, item 204), wherein the first TFT (FIG. 2, item 202) and third TFTs are is configured to output a current ([0030]) to the power consuming device (FIG. 2, item 204);
providing a second TFT (FIG. 2, item 201);
coupling ([0032], i.e. One of the source and the drain of the switching transistor 201 is connected to a signal line Si (i=1 to x), and the other is connected to each gate of the driving transistor 202 and the current control transistor 203.) the second TFT (FIG. 2, item 201) to the first TFT(FIG. 2, item 202) and the third TFT (FIG. 2, item 203), wherein the second TFT (FIG. 2, item 201) is configured ([0032]) to couple a programmable gate (FIG. 2, item Si; [0030], i.e. electric potential) control voltage (FIG. 2, item Si; [0030], i.e. electric potential) to the first (FIG. 2, item 202) and third (FIG. 2, item 202) TFTs, the control voltage (FIG. 2, item Si; [0030]) controlling an amount of the current ([0022], i.e. it can be said that the current Id1 is determined only with Vgs) provided to the power consuming device (FIG. 2, item 204);
providing a storage capacitor (FIG. 2, item 205) to store the control voltage ([0034], i.e. The capacitor element 205 is provided to store a gate voltage of the driving transistor 202 and of the current control transistor 203); and
coupling the storage capacitor (FIG. 2, item 205) to the first (FIG. 2, item 202), second (FIG. 2, item 201) and third (FIG. 2, item 202) TFTs.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (U.S. 2004/0252565) as applied to claim 1 above, and further in view of Lan et al (U.S. 2006/0118869).
Regarding claim 2. Yamazaki et al and Nakatani et al discloses all the limitations of the circuit of claim 1 above.
Yamazaki et al further discloses wherein the power consuming device comprises an light emitting device ([Abstract])
Yamazaki et al and Nakatani et al fails to explicitly disclose wherein the power consuming device comprises an infrared emitting device.
However, Lan et al teaches wherein the power consuming device (FIG. 3, item 328) comprises an infrared emitting device ([0061], i.e. The term "radiation-emitting component" is intended to mean an electronic component, which when properly biased, emits radiation at a targeted wavelength or spectrum of wavelengths. The radiation may be within the visible-light spectrum or outside the visible-light spectrum (ultraviolet ("UV") or infrared ("IR")).
Lan et al further discloses light emitting devices ([0053]).
Since Yamazaki et al and Lan et al teach light emitting devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the circuit as disclosed to modify Yamazaki et al with the teachings of wherein the power consuming device comprises an infrared emitting device as disclosed by Lan et al. The use of radiation may be within the visible-light spectrum or outside the visible-light spectrum (ultraviolet ("UV") or infrared in Lan et al provides for improved reliability and lifetime of the electronic device (Lan et al, [0147]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (U.S. 2004/0252565) as applied to claim 1 above, and further in view of Yamazaki et al (U.S. 2002/0134979).
Regarding claim 10. Yamazaki et al (‘565) discloses all the limitations of the circuit of claim 1 above.
Yamazaki et al (‘565) further discloses further comprising a substrate ([0063], FIG. 8B, item 4001), wherein the first (FIG. 8B, item 4202) and second (FIG. 1, item 4201) TFTs are disposed on the substrate ([0063], FIG. 8B, item 4001)
Yamazaki et al (‘565) fails to explicitly disclose further comprising a glass substrate
However, Yamazaki et al (‘979) further discloses further comprising a glass substrate ([0034], i.e. Substrates usable as the substrate 11 include a glass substrate), wherein the first (FIG. 1, item 202) and second (FIG. 1, item 201) TFTs are disposed on the glass substrate (FIG. 1, item 11).
Since Yamazaki et al (‘565) and Yamazaki et al (‘979) teach light emitting devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the circuit as disclosed to modify Yamazaki et al (‘565) with the teachings of further comprising a glass substrate as disclosed by Yamazaki et al (‘979). The use of substrates usable as the substrate include a glass substrate in Yamazaki et al (‘979) provides for a process of manufacturing a plurality of electronic devices from one large-sized substrate in order to reduce manufacturing cost of the electronic device, namely, to produce a low cost electronic device (Yamazaki et al (‘979), [0015]).
Response to Arguments
Applicant's arguments filed December 2, 2025 have been fully considered but they are not persuasive.
Regarding rejections of claims 1 and 18.
On page 5 of applicants remarks, applicant’s argues that Yamazaki et al fails to teach, suggest, or disclose all of the limitations of amended claim 1.
Examiner respectfully points out that Yamazaki et al disclose all of the limitations of applicant’s amended claims 1 and 18 as cited in the rejection above as best understood by the and 112(b) rejections above.
Regarding applicant’s amendments.
On page 5 of applicants remarks, applicant’s argues that support for applicant’ amendments can be found in FIG. 2A and [0021]-[0034].
Examiner respectfully points out that [0021]-[0030] are directed to unelected Species I, FIG. 1, and [0033]-[0034] are directed towards unelected Species 3-9 (FIG. 2B-2H).
Furthermore, FIG. 2A and [0021]-[0034] do not support applicant’s amendments.
Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/S.E.B./Examiner, Art Unit 2815