DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-13, 15-16 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ching et al. (US 2017/0207126 A1).
Regarding claim 10, Ching et al. teach in Fig. 34A (please also see Fig. 34B for structures under the ILD layer 1102 in Fig. 34A), a semiconductor structure (200D, [0017]), comprising: a first fin structure (a lower portion of 3212 below half the height 3116; [0136, 0145]) and a second fin structure (a lower portion of 3214 below half the height 3116; [0136, 0145]) disposed over a substrate (202; [0024]), the first fin structure (a lower portion of 3212 below half the height 3116) comprising an outer edge (the left edge of a lower portion of 3212 below half the height 3116) away from the second fin structure (a lower portion of 3214 below half the height 3116) and the second fin structure (a lower portion of 3214 below half the height 3116) comprising an outer edge (the right edge of a lower portion of 3214 below half the height 3116) away from the first fin structure (a lower portion of 3212 below half the height 3116); a first epitaxial layer (an upper portion of 3212 above half the height 3116; [0136, 0145]) disposed on the first fin structure (a lower portion of 3212 below half the height 3116); a first metal contact (1204B; [0079]); disposed on the first epitaxial layer (an upper portion of 3212 above half the height 3116); a second epitaxial layer (an upper portion of 3214 above half the height 3116; [0136, 0145]) disposed on the second fin structure (a lower portion of 3214 below half the height 3116); a second metal contact (1204B; [0079]) disposed on the second epitaxial layer (an upper portion of 3214 above half the height 3116); an inner spacer (3108; [0136]) disposed between the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116); and a dielectric material (1102/3002, 3002 is a dielectric material located inside 3108 as shown in Fig. 31B; [0068, 0128]) disposed over a top surface of the inner spacer (3108; see Figs. 32B and 33) and in contact with the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116), wherein the first epitaxial layer (an upper portion of 3212 above half the height 3116) comprises an outer side (left side) facing away from the second epitaxial layer (an upper portion of 3214 above half the height 3116) and an inner side (right side) facing toward the second epitaxial layer (an upper portion of 3214 above half the height 3116), wherein the second epitaxial layer (an upper portion of 3214 above half the height 3116) comprises an outer side (right side) facing away from the first epitaxial layer (an upper portion of 3212 above half the height 3116) and an inner side (left side) facing toward the first epitaxial layer (an upper portion of 3212 above half the height 3116), wherein the outer side of the first epitaxial layer (left side of an upper portion of 3212 above half the height 3116) comprises a first protrusion portion (the left portion of an upper portion of 3212 above half the height 3116; [0136, 0145]) extending beyond the outer edge of the first fin structure (the left edge of a lower portion of 3212 below half the height 3116), wherein the outer side of the second epitaxial layer (right side of an upper portion of 3214 above half the height 3116) comprises a second protrusion portion (the right portion of an upper portion of 3214 above half the height 3116; [0136, 0145]) extending beyond the outer edge of the second fin structure (the right edge of a lower portion of 3214 below half the height 3116), wherein the inner sides of the first epitaxial layer and the second epitaxial layer (right side of an upper portion of 3212 above half the height 3116 and left side of an upper portion of 3214 above half the height 3116) extend perpendicular to the substrate (202; see Fig. 34B), wherein the inner spacer (3108) extends continuously from the inner side of the first epitaxial layer (right side of an upper portion of 3212 above half the height 3116) to the inner side the second epitaxial layer (left side of an upper portion of 3214 above half the height 3116), wherein a portion of the dielectric material (1102/3002) extends between a sidewall of the first fin structure (a lower portion of 3212 below half the height 3116) and a sidewall of the second fin structure (a lower portion of 3214 below half the height 3116; see Figs. 32B and 33).
Regarding claim 11, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 10, further comprising: a first outer spacer (the left 3110; [0136]) disposed along a portion of the outer side of the first epitaxial layer (left side of an upper portion of 3212 above half the height 3116); and a second outer spacer (the right 3110; [0136]) disposed along a portion of the outer side of the second epitaxial layer (right side of an upper portion of 3214 above half the height 3116), wherein the first protrusion portion (the left portion of an upper portion of 3212 above half the height 3116) protrudes laterally beyond an outermost edge of the first outer spacer (the rightmost edge of the left 3110), wherein the second protrusion portion (the right portion of an upper portion of 3214 above half the height 3116) protrudes laterally beyond an outermost edge of the second outer spacer (the leftmost edge of the right 3110).
Regarding claim 12, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 11, further comprising: an isolation feature (402; [0032]) disposed over the substrate (202) and between the first fin structure (a lower portion of 3212 below half the height 3116) and the second fin structure (a lower portion of 3214 below half the height 3116).
Regarding claim 13, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 12, wherein the inner spacer (3108) extends continuously from the inner side of the first epitaxial layer (right side of an upper portion of 3212 above half the height 3116), to a top surface of the isolation feature (402), and then the inner side the second epitaxial layer (left side of an upper portion of 3214 above half the height 3116).
Regarding claim 15, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 13, wherein a top surface of the inner spacer (3108) is higher than a top surface of the first outer spacer (the left 3110) or a top surface of the second outer spacer (the right 3110).
Regarding claim 16, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 13, wherein the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116) are bounded by the inner spacer (3108) such that the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116) do not extend over the inner spacer (the portions of 3212 and 3214 in direct contact with 3108 do not extend over 3108).
Regarding claim 18, Ching et al. teach in Fig. 34A (please also see Fig. 34B for structures under the ILD layer 1102 in Fig. 34A), a semiconductor structure (200D, [0017]), comprising: a first fin structure (a lower portion of 3212 below half the height 3116; [0136, 0145]) and a second fin structure (a lower portion of 3214 below half the height 3116; [0136, 0145]) disposed over a substrate (202; [0024]); an isolation feature (402; [0032]) disposed over the substrate (202) and between the first fin structure (a lower portion of 3212 below half the height 3116) and the second fin structure (a lower portion of 3214 below half the height 3116); a first epitaxial layer (an upper portion of 3212 above half the height 3116; [0136, 0145]) disposed on the first fin structure (a lower portion of 3212 below half the height 3116), the first epitaxial layer (an upper portion of 3212 above half the height 3116) comprising an outer side (left side) facing away from the second fin structure (a lower portion of 3214 below half the height 3116) and an inner side (right side) facing toward the second fin structure (a lower portion of 3214 below half the height 3116); a second epitaxial layer (an upper portion of 3214 above half the height 3116; [0136, 0145]) disposed on the second fin structure (a lower portion of 3214 below half the height 3116), the second epitaxial layer (an upper portion of 3214 above half the height 3116) comprising an outer side (right side) facing away from the first epitaxial layer (an upper portion of 3212 above half the height 3116) and an inner side (left side) facing toward the first epitaxial layer (an upper portion of 3212 above half the height 3116); a first metal contact (a portion of 1204B formed of metal; [0079]) disposed on the first epitaxial layer (an upper portion of 3212 above half the height 3116) and separated from the second epitaxial layer (an upper portion of 3214 above half the height 3116, the portion of 1204B formed of metal is separated from 3214 by the silicide layer 1206B; see Fig. 34B, [0078-0079]); an inner spacer (3108; [0136]) extending continuously from the inner side of the first epitaxial layer (right side of an upper portion of 3212 above half the height 3116), to a top surface of the isolation feature (402), and then the inner side the second epitaxial layer (left side of an upper portion of 3214 above half the height 3116); and a dielectric material (1102/3002, 3002 is a dielectric material located inside 3108 as shown in Fig. 31B; [0068, 0128]) disposed over a top surface of the inner spacer (3108) and in contact with the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116), wherein the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116) are bounded by the inner spacer (3108) such that the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116) do not extend over the inner spacer (3108), wherein a portion of the dielectric material (1102/3002) extends between a sidewall of the first fin structure (a lower portion of 3212 below half the height 3116) and a sidewall of the second fin structure (a lower portion of 3214 below half the height 3116; see Figs. 32B and 33).
Regarding claim 19, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 18, further comprising: a first outer spacer (the left 3110) disposed along a portion of the outer side of the first epitaxial layer (left side of an upper portion of 3212 above half the height 3116); and a second outer spacer (the right 3110) disposed along a portion of the outer side of the second epitaxial layer (right side of an upper portion of 3214 above half the height 3116), wherein the outer side of the first epitaxial layer (left side of an upper portion of 3212 above half the height 3116) comprises a first protrusion portion (the left portion of an upper portion of 3212 above half the height 3116) extending laterally away from the second epitaxial layer (an upper portion of 3214 above half the height 3116) such that the first protrusion portion (the left portion of an upper portion of 3212 above half the height 3116) protrudes beyond an outermost edge of the first outer spacer (the rightmost edge of the left 3110), wherein the outer side of the second epitaxial layer (right side of an upper portion of 3214 above half the height 3116) comprises a second protrusion portion (the right portion of an upper portion of 3214 above half the height 3116) extending laterally away from the first epitaxial layer (an upper portion of 3212 above half the height 3116) such that the second protrusion portion (the right portion of an upper portion of 3214 above half the height 3116) protrudes beyond an outermost edge of the second outer spacer (the leftmost edge of the right 3110).
Regarding claim 20, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 19, wherein a top surface of the inner spacer (3108) is higher than a top surface of the first outer spacer (the left 3110) or a top surface of the second outer spacer (the right 3110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. as applied to claim 13 above, and further in view of Reznicek et al. (US 2019/0252260 A1).
Regarding claim 14, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 13, wherein the first outer spacer (the left 3110), the second outer spacer (the right 3110), and the inner spacer (3108).
Ching et al. do not teach the first outer spacer, the second outer spacer, and the inner spacer comprise fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicon based polymeric dielectrics, or combinations thereof.
In the same field of endeavor of semiconductor manufacturing, Reznicek et al. teach the spacer (30; Figs. 1A-1B; [0043]) comprise fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicon based polymeric dielectrics, or combinations thereof (porous silicon dioxide; [0043]).
Ching et al. teach all the claimed elements except that Ching et al. is using silicon nitride for the material of the spacer ([0040]) rather than porous silicon dioxide.
In the same field of endeavor of semiconductor manufacturing, Reznicek et al. teach porous silicon dioxide for the material of the spacer ([0043]).
One of ordinary skill in the art would have recognized that silicon nitride and porous silicon dioxide are known equivalents for providing the material of the spacer within the semiconductor art.
It would have been obvious to one of ordinary skill in the art at the time of invention was made to substitute one know element (silicon nitride) for another known equivalent element (porous silicon dioxide) resulting in the predictable result of providing the material of the spacer (KSR rationales B).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. as applied to claim 10 above.
Regarding claim 17, Ching et al. teach in Figs. 34A and 34B, the semiconductor structure of claim 10, wherein the first epitaxial layer (an upper portion of 3212 above half the height 3116) and the second epitaxial layer (an upper portion of 3214 above half the height 3116) comprise silicon germanium and a dopant (both 3212 and 3214 are source/drain features which can be SiGe and doped, [0145, 0065]).
Ching et al. do not teach a dopant is a p-type dopant.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to have the dopant of a p-type dopant since Ching et al. teach that the device can be used as a P-type metal-oxide-semiconductor (PMOS) ([0022]) and it was known in the art that PMOS needs the source/drain regions to be P-type.
Allowable Subject Matter
Claims 1-2, 5-9 and 21-22 are allowed.
Response to Arguments
Applicant's arguments with respect to claims 10 and 18 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Basker et al. (US 9659942 B1) teach a FINFET using the spacers to perform selective epitaxy process. .
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 5/5/2026
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