DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The objection to claim 11 and the 35 U.S.C. § 112 rejections to claims 1-18 are withdrawn due to the amendment that corrected these issues. However, claim 19-20 continues to have the 35 U.S.C. § 112 (b) rejection.
Applicant's arguments filed on 23 January 2026 have been fully considered but they are not persuasive. The applicant argues that Kong does not teach the added limitations of the claims, i.e., Kong does not teach build-up layers on the top surface of the IC package core and does not teach that the IC core via cap is disposed within an opening in the build-up layers. The examiner respectfully disagrees. Please see the 35 U.S.C. rejection below of independent claims 1, 11, and 19 for more details.
In summary, the application is not in a condition for an allowance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claim 19 and, by extension, dependent claim 20, is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purpose of compact prosecution, the examiner will cite art that teaches electrical conductors disposed in a plane that is non-coplanar with the core via cap.
Claim 19 and, by extension, dependent claim 20 recite the limitation "the conductor body" in amended limitations of the claims. There is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the examiner will treat “the conductor body” to be the “electrical conductor” defined in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable by Kong (US 2019/0131257 A1) and in further view of Shirvani (US 2018/0026680 A1).
Regarding claim 1, Kong teaches a tuning structure (Figs. 4-6; ¶ 0024 – ¶ 0036) to reduce a capacitive discontinuity (¶ 0015: impedance mismatch due to over-capacitive nature of a via) in an integrated circuit (IC) package (102; see Fig. 1; ¶ 0017), comprising:
an electrical conductor (410 & 412 & 414; see Figs. 4-6; ¶ 0026 - ¶ 0027) having a first end (414), a second end (412), and a conductor body (410) between the first end and the second end, the first end electrically coupled to a signal via (214 & 406; see ¶ 0026; also Figs. 4 & 5 & ¶ 0028 show 214 & 406 coupled to differential signal wires D+ and D-) and the second end electrically coupled to an IC package core via cap (210; see ¶ 0026; Fig. 4 shows 412 coupled to 210, with 210 being a capping core via 206; see also Figs. 2-3 & ¶ 0019 that shows 206 is a core via);
a first portion (Figs. 4-6: 412 and lower ends of 410 directly connected to 412 is a first portion) of the conductor body disposed in a first plane (plane of 210) that is coplanar with the IC package core via cap (Figs. 4-6 shows 412 and lower ends of 410 extending laterally, i.e., coplanar, to interconnect pad 210; also Fig. 5 & ¶ 0031 describes reference plane 216 wherein 412 & 410 and 210 are within the reference plane), and the first portion of the conductor body disposed along an outer perimeter (402, see ¶ 0024) of the IC package core via cap (as shown in Fig. 4, 410&412 are disposed along 402), the IC package core via cap and the first portion of the conductor body disposed within an opening (302, see Figs. 2 & 3 and ¶ [0023]: “a void may be formed between interconnect pad 210 and a reference plane 216…”; also see Figs. 4-6 where first portion 412 is in the same reference plane as 210) in a set of build-up layers (212 & 214, see Fig. 2; these are layers of conductive and insulative materials, see ¶ [0020]-[0021]: “package substrate 120 may include one or more interconnect layer 212 having several axial and transverse interconnects,” emphasis added) fabricated on a top surface (top surface of 202) of a core (202) of the IC package.
Kong further teaches the conductor body to be an inductor (¶ 0027) with a second portion (414 and upper ends of 410) of the conductor body disposed the same plane as the IC core via cap and the first portion of the conductor body (see Figs. 4 and 5).
However, Kong does not teach the second portion of the conductor body disposed in a second plane that is non-coplanar with the IC package core via cap.
Shirvani, in the same field of invention, teaches an inductor (520, see Fig. 24) with a first portion (522) of a conductor body (¶ 0219: 520 is made of first and second levels of metallization) and a second portion (524) disposed in a second plane (528) that is non-coplanar with the first portion of the conductor body (Fig. 24 shows 528 is not in the same plane 526 that 522 is disposed on). Hence, Kong in view of Shirvani teaches: the second portion of the conductor body disposed in a second plane that is non-coplanar with the IC package core via cap.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Shirvani into the device of Kong to have a second portion of a conductor body to be disposed in a second plane that is non-coplanar with an IC package core via cap in a tuning structure at least comprising of an electrical conductor having a first end, a second end, and the above-mentioned conductor body that is coupled between the first end and second end, with the first end coupled to a signal via and the second end coupled to the IC package core via, with a first portion of the conductor body being coplanar with the IC package core via and disposed along an outer perimeter of the IC package core via cap, and with the above-mentioned second portion of the conductor body. The ordinary artisan would have been motivated to modify Kong in the manner set forth above for designing the inductor as a multi-layered inductor at least the purpose of increasing the inductance per unit area and reducing the dimension of the inductor (Shirvani ¶ 0219).
Regarding claim 2, Kong in view of Shirvani teaches the tuning structure of claim 1, wherein the electrical conductor (410 & 412 & 414, see Kong Figs. 4-6) extends along the outer perimeter of the core via cap through an angle θ (Kong Fig. 5 & ¶ 0032: arc 514 is analogous to θ as it subtends an angle taken about axis 208) measured from a first line (diagonal dotted line) extending from a center point (208 ; Kong ¶ 0024-¶ 0025, ¶ 0032-¶ 0033) of the core via cap to the signal via (see Kong Fig. 4; labeled as 408 in Kong Fig. 5 & ¶ 0025), to a second line (vertical dotted line) extending from the center point of the core via cap to a contact location (508; see Kong ¶ 0030) where the second end is electrically coupled to the core via cap (Fig. 5 shows 508 is connected to 210).
Regarding claim 3, Kong in view of Shirvani teaches the tuning structure of claim 2, wherein a transmission path (Kong ¶ 0026) comprises a core via (206, see Kong Fig 4 and ¶ 0026; also see Kong Figs 2-3 & ¶ 0019: 206 is a core via), the core via cap (210, see Kong Figs. 4-6), the electrical conductor (410 & 412 & 414), and the signal via (214 & 406), and wherein the contact location (508, see Fig. 5) is set by an adjustment of angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region"), based on a TDR measurement (Kong Fig 8; ¶ 0042-¶ 0043]) of the transmission path.
Regarding claim 4, Kong in view of Shirvani teaches the tuning structure of claim 3, wherein the angle θ is adjusted (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region") to reduce an impedance change (804; Kong Fig. 8, ¶ 0043) produced by the TDR measurement (Kong ¶ 0042).
Regarding claim 5, Kong in view of Shirvani teaches the tuning structure of claim 2, wherein a transmission path (Kong ¶ 0026) comprises a core via (206; see Kong Fig 4; ¶ 0026; also Figs 2-3 & ¶ 0019 shows 206 is a core via), the core via cap (210, see Kong Figs. 4-6), the electrical conductor (410 & 412 & 414), and the signal via (214 & 406), and wherein the contact location (508, see Fig. 5) is moved by an adjustment of angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region"), based on an insertion loss measurement of the transmission path (Kong Fig 8; ¶ 0042-¶ 0043: Kong teaches using TDR measurement to compensate impedance mismatch. Insertion loss measurement is caused by component impedance mismatch as evidenced by Fluke Networks, Insertion Loss NPL, Page 5, Insertion Loss Deviation. Hence Kong teaches adjustment of angle θ based on insertion loss measurement; see previous Office Action mailed 13 January 2025 for NPL reference).
Regarding claim 6, Kong in view of Shirvani teaches the tuning structure of claim 5, wherein the angle θ is adjusted to reduce a ripple magnitude (804, see Kong Fig. 8; ¶ 0043: impedance change as seen on TDR plot) of the insertion loss measurement (as evidenced by Fluke Networks, Insertion Loss NPL, Page 5 Insertion Loss Deviation, a ripple is observed through measurement of insertion loss, which in turn is caused by impedance mismatch. Since Kong teaches measuring impedance mismatch through TDR, then Kong teaches adjustment of angle θ to reduce a ripple magnitude; see previous Office Action mailed 13 January 2025 for NPL reference ).
Regarding claim 7, Kong in view of Shirvani teaches the tuning structure of claim 2, wherein a transmission path (Kong ¶ 0026) comprises a core via (206; see Kong Fig 4; ¶ 0026; Figs 2-3 & ¶ 0019 shows 206 is a core via), the core via cap (210; Kong Figs. 4-6) , the electrical conductor (401 & 412 & 414), and the signal via (214 & 406), and wherein the contact location (508, see Fig. 5) is moved by an adjustment of angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region"), based on a return loss measurement (902; see Kong Fig. 9 and ¶ 0044-¶ 0045: solid line of eye diagram 902 is larger with adjusted lateral interconnects 410 than dotted line, which is without 410; Kong ¶ 0044 also teaches "Impedance mismatch is a key source of reflection noise (emphasis added) in a high-speed I/O channel, and thus, reduced impedance mismatch translates to an improvement in eye margin" ) of the transmission path (as evidenced by NPL: Chin, T.K. "What You Need to Know About Return Loss", Page 1, What is Return Loss: "Return loss is a mathematical term to measure how well a device’s termination matches with its target impedance, which also indicates the amount of reflected signal" (emphasis added). Hence Kong teaches adjustment of angle-θ based on a return loss; see previous Office Action mailed 13 January 2025 for NPL reference).
Regarding claim 8, Kong in view of Shirvani teaches the tuning structure of claim 7, wherein the angle θ is adjusted to reduce a return loss magnitude (Kong Fig. 9; ¶ 0045: the difference of solid and dotted 902 & 904) in the return loss measurement (Kong ¶ 0044 also teaches "Impedance mismatch is a key source of reflection noise in a high-speed I/O channel, and thus, reduced impedance mismatch (emphasis added) translates to an improvement in eye margin"; as evidenced by NPL: Chin, T.K. "What You Need to Know About Return Loss", Page 1, What is Return Loss: "Return loss is a mathematical term to measure how well a device’s termination matches with its target impedance, which also indicates the amount of reflected signal" (emphasis added). Hence Kong teaches adjustment of angle θ to reduce a return loss magnitude; see previous Office Action mailed 13 January 2025 for NPL reference).
Regarding claim 9, Kong in view of Shirvani teaches the tuning structure of claim 2, wherein the angle θ is between zero and 360° (Kong Fig. 5 & ¶ 0032: 514 may subtend an angle equal to or less than 360° ).
Regarding claim 10, Kong in view of Shirvani teaches the tuning structure of claim 2, wherein the angle θ is greater than 360° (Kong Fig. 6 & ¶ 0032; 514 may subtend an angle more than 360°).
Regarding claim 11, Kong teaches a method of tuning (Fig. 4 & ¶ 0027: using 410 to match an impedance of 214) an integrated circuit package (102; see Fig. 1 ¶ 0017) transmission path (112; ¶ 0027), comprising:
coupling a first end (414; see Figs 4-6; ¶ 0026) of an electrical conductor (410 & 412 & 414, see ¶0026- ¶ 0027) to a signal via (214 & 406; see ¶ 0026, ¶ 0028; Figs. 4 & 5 show 214 & 406 coupled to differential signal wires D+ and D-);
coupling a second end (412; see Figs. 4-6; ¶ 0026) of the electrical conductor to a core via cap (210; see ¶ 0026; Fig. 4 shows core via cap 210 is capping core via 206; see also Figs. 2-3 & ¶ 0019 that shows 206 is a core via) of the integrated circuit package (102), the electrical conductor having a conductor body (the entire length of 410 in between 412 and 414) between the first end and the second end;
disposing a first portion (Figs. 4-6: 412 and lower ends of 410 directly connected to 412 is a first portion) of the electrical conductor in a first plane (the plane of 210) that is coplanar with the core via cap (Figs. 4-6 & ¶ 0026 shows 412 and lower ends of 410 extending laterally, i.e., coplanar, from interconnect pad 210; also Fig. 5 & ¶ 0031 describes reference plane 216 wherein 412 & 410 and 210 are within the reference plane), and disposing the conductor body along an outer perimeter (402, see ¶ 0024) of the core via cap, the core via cap of the IC package and the first portion of the conductor body disposed within an opening (302, see Figs. 2 & 3 and ¶ [0023]: “void may be formed between interconnect pad 210 and a reference plane 216”; also see Fig. 4 where first portion 412 is in the same reference plane as 210) in a set of build-up layers (212 & 214, see Fig. 2; these are layers of conductive and insulative materials, see ¶ [0020]-[0021]: “package substrate 120 may include one or more interconnect layer 212 having several axial and transverse interconnects,” emphasis added) fabricated on a top surface (top surface of 202) of a core (202) of the IC package.
Kong further teaches the electrical conductor to be an inductor (¶ 0027) with a second portion (414 and upper ends of 410) of the electrical conductor body the same plane as the core via cap and the first portion of the electrical conductor (see Figs. 4 and 5).
However, Kong does not teach disposing the second portion of the electrical conductor in a second plane that is non-coplanar with the core via cap of the IC package.
Shirvani, in the same field of invention, teaches an inductor (520, see Fig. 24) with a first portion (522) of an electrical conductor (¶ 0219: 520 is made of first and second levels of metallization) and a second portion (524) of the electrical conductor disposed in a second plane (528) that is non-coplanar with the first portion of the electrical conductor (Fig. 24 shows 528 is not in the same plane 526 that 522 is disposed on). Hence, Kong in view of Shirvani teaches a method comprising: disposing the second portion of the electrical conductor in a second plane that is non-coplanar with the core via cap of the IC package.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Shirvani into the method of Kong to dispose a second portion of an electrical conductor in a second plane that is non-coplanar with an IC package core via cap in a method of tuning an integrated circuit package transmission path at least comprising of coupling a first end of an electrical conductor to a signal via; coupling a second end of the electrical conductor to a core via cap of an IC package, with the electrical conductor having a conductor body between the first end and the second end; disposing a first portion of the electrical conductor in a first plane that is coplanar with the core via cap and along an outer perimeter of the core via cap; and disposing the second portion of the conductor body as in the manner described above. The ordinary artisan would have been motivated to modify Kong in the manner set forth above for designing a multi-layered inductor at least the purpose of increasing the inductance per unit area and reducing the dimension of the inductor (Shirvani ¶ 0219).
Regarding claim 12, Kong in view of Shirvani teaches the method of claim 11, further comprising extending the electrical conductor (410 & 412 & 414, see Kong Figs. 4-6) along the outer perimeter of the core via cap through an angle θ (Kong Fig. 5 & ¶ 0032: arc 514 is analogous to θ as it subtends an angle taken about axis 208) measured from a first line (diagonal dotted line) extending from a center point (208, see Kong ¶ 0024- ¶ 0025 and ¶ 0032- ¶ 0033]) of the core via cap (210) to the signal via (214 & 406; see Kong Fig. 4; labelled as 408 in Kong Fig. 5 & ¶ 0025), to a second line (vertical dotted line) extending from the center point (208) of the core via cap (210) to a contact location (508; see Kong ¶ 0030) where the second end (412) is electrically coupled to the core via cap (210).
Regarding claim 13, Kong in view of Shirvani teaches the method of claim 12, further comprising moving the contact location (508; see Kong Fig. 5) by an adjustment of angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region"), based on a TDR measurement (Kong Fig 8; ¶ 0042- ¶ 0043) of a transmission path (¶ 0026), wherein the transmission path comprises a core via (206; see Kong Fig 4; ¶ 0026; Figs 2-3 & ¶ 0019 shows 206 is a core via), the core via cap (210; see Kong Figs. 4-6), the electrical conductor (410 & 412 & 414), and the signal via (214 & 406).
Regarding claim 14, Kong in view of Shirvani teaches the method of claim 13, further comprising adjusting the angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region") to reduce an impedance change (804; see Kong Fig. 8; ¶ 0043) produced by the TDR measurement (Kong ¶ 0043).
Regarding claim 15, Kong in view of Shirvani teaches the method of claim 12, further comprising moving the contact location (508; see Kong Fig. 5) by an adjustment of angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region"), based on an insertion loss measurement of a transmission path (Kong Fig 8; ¶ 0042-0043: Kong teaches using TDR measurement to compensate impedance mismatch. Insertion loss measurement is caused by component impedance mismatch as evidenced by Fluke Networks, Insertion Loss NPL, Page 5, Insertion Loss Deviation. Hence Kong teaches adjustment of angle θ based on insertion loss measurement; see previous Office Action mailed on 13 January 2025 for NPL reference), wherein the transmission path comprises a core via (206; see Kong Fig 4; ¶ 0026; Figs 2-3 & ¶ 0019 shows 206 is a core via), the core via cap (210, see Kong Figs. 4-6), the electrical conductor (410 & 412 & 414), and the signal via (214 & 406).
Regarding claim 16, Kong in view of Shirvani teaches the method of claim 15, further comprising adjusting the angle θ to reduce a ripple magnitude (804; see Kong Fig. 8; ¶ 0043: impedance change as seen on TDR plot) of the insertion loss measurement (as evidenced by Fluke Networks, Insertion Loss NPL, Page 5 Insertion Loss Deviation, a ripple is observed through measurement of insertion loss, which in turn is caused by impedance mismatch. Since Kong teaches measuring impedance mismatch through TDR, then Kong teaches adjusting the angle θ to reduce of ripple magnitude; see previous Office Action mailed 13 January 2025 for NPL reference).
Regarding claim 17, Kong in view of Shirvani teaches the method of claim 12, further comprising moving the contact location (508; see Kong Fig. 5) by an adjustment of angle θ (Kong ¶ 0032: "[The] arc length 514 may subtend an angle taken about vertical axis 208. The angle may be equal to, less than, or more than, 360°"; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region"), based on a return loss measurement (902 & 904; see Kong Fig. 9 and ¶ 0044-¶ 0045: solid line of eye diagram is larger with adjusted lateral interconnects 410 than dotted line, which is without 410; Kong ¶ 0044 also teaches "Impedance mismatch is a key source of reflection noise (emphasis added) in a high-speed I/O channel, and thus, reduced impedance mismatch translates to an improvement in eye margin" ) of a transmission path (Kong [0026]), wherein the transmission path comprises a core via (206, see Kong Fig 4 and ¶ 0026; Figs 2-3 & ¶ 0019 show 206 being a core via), the core via cap (210, see Figs. 4-6), the electrical conductor (401 & 412 & 414), and the signal via (214 & 406; as evidenced by NPL: Chin, T.K. "What You Need to Know About Return Loss", Page 1, What is Return Loss: "Return loss is a mathematical term to measure how well a device’s termination matches with its target impedance, which also indicates the amount of reflected signal" (emphasis added). Hence Kong teaches adjustment of angle θ to reduce a return loss magnitude; see previous Office Action mailed on 13 January 2025 for NPL reference).
Regarding claim 18, Kong in view of Shirvani teaches the method of claim 17, further comprising adjusting the angle θ to reduce a return loss magnitude (Kong Fig. 9; ¶ 0045: the difference of solid and dotted 902 & 904) in the return loss measurement (Kong ¶ 0044 also teaches "Impedance mismatch is a key source of reflection noise in a high-speed I/O channel, and thus, reduced impedance mismatch (emphasis added) translates to an improvement in eye margin"; as evidenced by NPL: Chin, T.K. "What You Need to Know About Return Loss", Page 1, What is Return Loss: "Return loss is a mathematical term to measure how well a device’s termination matches with its target impedance, which also indicates the amount of reflected signal" (emphasis added). Hence Kong teaches adjustment of angle θ based on a return loss; see previous Office Action mailed 13 January 2025 for NPL reference).
Regarding claim 19, Kong teaches a tuning structure (Figs. 4-6; [0024-0036]), comprising:
a first via (206; Figs. 2-3; ¶ 0019) embedded in a core of an integrated circuit (IC) package (102; Fig. 1; ¶ 0017) ;
a core via cap (210; Figs. 4; ¶ 0026]) attached to an end (top end of 206) of the first via;
a second via (214 & 406; ¶ 0026]; Figs. 4 & 5 & ¶ 0028 show 214 & 406 coupled to differential signal wires D+ and D-) electrically coupled to an IC die (110; Fig. 1 ¶ 0017);
an electrical conductor (410 & 412 & 414; Figs. 4-6; ¶ 0026-0027) that electrically couples the core via cap to the second via, a first portion (Figs. 4-6: 412 and lower ends of 410 directly connected to 412 is a first portion) of the electrical conductor extends around at least a portion (portion of 402 facing 410) of a perimeter (402, ¶ 0024) of the core via cap and electrically couples to the core via cap at a contact location (412, ¶ 0026; Figs. 4-6 & ¶ 0026 show 412 and lower ends of 410 extending laterally, i.e., coplanar, from interconnect pad 210; also Fig. 5 & ¶ 0031 describes reference plane 216 wherein 412 & 410 and 210 are within the reference plane), the core via cap and the first portion of the conductor body disposed within an opening (302, see Figs. 2 & 3 and ¶ [0023]: “void may be formed between interconnect pad 210 and a reference plane 216”; also see Fig. 4 where first portion 412 is in the same reference plane as 210) in a set of build-up layers (212 & 214, see Fig. 2; these are layers of conductive and insulative materials, see ¶ [0020]-[0021]: “package substrate 120 may include one or more interconnect layer 212 having several axial and transverse interconnects,” emphasis added) fabricated on a top surface (top surface of 202) of a core (202) of the IC package.
Kong further teaches the electrical conductor to be an inductor (¶ 0027) with a second portion (414 and upper ends of 410) of the electrical conductor disposed the same plane as the core via cap and the first portion of the electrical conductor (see Figs. 4 and 5).
However, Kong does not teach the second portion of the electrical conductor disposed in a plane that is substantially non-coplanar with the core via cap.
Shirvani, in the same field of invention, teaches an inductor (520, see Fig. 24) with a first portion (522) of an electrical conductor (¶ 0219: 520 is made of first and second levels of metallization) and a second portion (524) of the electrical conductor disposed in a plane (528) that is substantially non-coplanar with the first portion of the electrical conductor (Fig. 24 shows 528 is not in the same plane 526 that 522 is disposed on). Hence, Kong in view of Shirvani teaches: the second portion of the electrical conductor disposed in a plane that is substantially non-coplanar with the core via cap.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Shirvani into the device of Kong to have a second portion of an electrical conductor to be disposed in a plane that is substantially non-coplanar with a core via cap in a tuning structure at least comprising of a first via embedded in a core of an IC package; the above-mentioned core via cap attached to an end of a first via; a second via electrically coupled to an IC die; the above-mentioned electrical conductor having a first portion and the above-mentioned second portion, with the first portion extending around a portion of perimeter of the via cap and electrically couples the via cap at a contact location. The ordinary artisan would have been motivated to modify Kong in the manner set forth above for designing a multi-layered inductor at least the purpose of increasing the inductance per unit area and reducing the dimension of the inductor (Shirvani ¶ 0219).
Regarding claim 20, Kong in view of Shirvani teaches the tuning structure of claim 19, wherein a transmission path (Kong ¶ 0026) comprises the first via (206), the via cap (210), the second via (214 & 406), and the electrical conductor (410 & 412 & 414), and wherein the contact location is determined (Kong Fig. 5 & ¶ 0032: arc 514 is analogous to θ as it subtends an angle taken about axis 208 between the ends 412 & 414 of the electric conductor 410 & 412 & 414; also Kong ¶ 0027: 410 used to match an impedance of 214; "More particularly, lateral interconnect 410 may extend around a portion of interconnect pad 210, creating an inductive circuitry to generate inductance that compensates for the parasitic capacitance a vertical interconnect 206"; also Kong ¶ 0029: "The curved routing of arc segment 502 may increase inductance of signal line 112 in the vertical interconnect 206 region") based on a measurement (solid line in Kong Fig. 8) of a performance metric (TDR; see Kong Fig 8; ¶ 0042- 0043) associated with the transmission path.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899