DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 08/03/2026, in which: the title is amended; specification paragraphs [0034] and [0058] are amended; claim(s) 1, 4, 6, and 7 is/are amended; claim(s) 2-3 is/are cancelled; and the rejection of the claims are traversed. Claim(s) 1 and 4-10 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 08/03/2026, with respect to the objections to the title and specification are persuasive in view of the amendments made to each, by which the objections previously set forth have been overcome and are now withdrawn.
Applicant's arguments with respect to the rejection(s) of claim(s) 1 and 7 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that one would not be motivated to combine L1 and S1 in the manner proposed because the two references disclose different and incompatible structures (Applicant’s Remarks page 9-10), Examiner respectfully disagrees. Both L1’s auxiliary electrode 12 and S1’s auxiliary electrode 260 are auxiliary electrodes forming and undercut in an opening. The primary differences between the two are structure (12 is a single layer of material while 260 is a multi-layer), position with respect to a planarization layer (12 is under 14 while 260 is over 192), and the method of forming the electrode and undercut. What Applicant identifies as the differences between the structures are exactly the features of S1 which are to be combined with L1. Consider the structures of the display panels in both L1 FIG. 5 and S1 FIG. 8, which show intermediate structures at a stage prior to forming the anode electrode. In both figures, via holes expose underlying metallizations for connections to the anode and auxiliary electrode respectively. S1 discloses a superior method of forming the auxiliary electrode 260, by forming it in the same step and layer as anode electrode 210, and using the same materials, significantly simplifying the manufacturing method. At this stage, one would be motivated to form both electrodes simultaneously using the process disclosed by S1. The applicant should note that while L1 already has auxiliary electrode 12, the auxiliary electrode would not be formed at this stage in forming the device of the combined reference, since both the auxiliary electrode and undercut will be formed by the process disclosed by S1. By using the improved manufacturing method of S1, L1’s auxiliary electrode 12 would have the structure and position of S1’s auxiliary electrode 260, and as claimed. The only redesign of the architecture of L1 would be the removal of auxiliary electrode 12, as shown, and instead forming it and the anode in a single layer with the structure of S1’s auxiliary electrode 260, which would still perform the same function as 12, while being formed in a more-efficient process. Only a small part of L1 is redesigned, and insulating flat layer 14 remains in L1.
Regarding Applicant’s argument that the proposed combination of L1 and S1 would not result in the claimed recess structure of the cathode layer, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The combination of L1 and S1 combines only S1’s step of forming the auxiliary electrode and undercut. L1, being the primary reference, discloses the claimed recess structure of the cathode layer, which would be present in the references, as combined.
Furthermore, there is no teaching or suggestion in L1 or S1 that suggests the structure of cathode layer 18, as disclosed by L1, could not be formed when combining the auxiliary electrode 260 structure of S1. After all, the claimed structure can allegedly be formed in an undercut opening which appears to have similar geometry to that of S1, as shown in FIG. 8 of the instant application. Examiner sees no reason why the structure, as claimed, would not have been predictably formed by the combination of L1 and S1 when it can in the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20230189570 A1, hereinafter L1), and further in view of Shin et al. (US 20210193954 A1, hereinafter S1).
Regarding independent claim 1, L1 discloses in L1 FIG. 1 and 3-10 and associated text An OLED display panel, comprising: an array substrate (array substrate 11),
comprising: a substrate (base substrate 101); a buffer layer disposed on the substrate (buffer layer 104); an active layer disposed on the buffer layer (amorphous oxide semiconductor layer 105); a gate insulating layer disposed on the active layer (gate insulating layer 107); a gate layer disposed on the gate insulating layer (first metal conductive layer 108); an interlayer dielectric layer disposed on the gate layer (shield insulating layer 109); a metal layer disposed on the interlayer dielectric layer (layer comprising 110, 112, and 111), wherein the metal layer comprises a plurality of source-drain layers (source electrode 111 and drain electrode 112) and an auxiliary electrode layer (first auxiliary electrode 110) arranged at intervals in the same layer (110, 111, and 112 are spaced apart at intervals and on the same layer), and the plurality of source-drain layers are connected to the active layer (111 and 112 connect to 105 as shown); a passivation layer disposed on the auxiliary electrode and the plurality of source-drain layers (protective layer 113); a planarization layer disposed on the passivation layer (flat layer 14); a first via hole penetrating the planarization layer and the passivation layer from a side of the planarization layer away from the substrate (second via hole 141 penetrates 14 and 113), and the plurality of source-drain layers are exposed in the first via hole (141 exposing 111 is interpreted as exposing the plurality of source-drain layers); and a second via hole penetrating the planarization layer and the passivation layer from the side of the planarization layer away from the substrate (first opening 161 penetrates 14 and 113), and is spaced apart from the first via hole (141 and 161 are spaced apart), and the auxiliary electrode layer is exposed in the second via hole (110 is in 161 as shown);
an anode layer disposed on the array substrate (second auxiliary electrode 12 and anode electrode 15, which are together interpreted as an anode layer), wherein the anode layer comprises a first anode layer and a second anode layer arranged at intervals in the same layer (12 (second anode layer) and 15 (first anode layer) are spaced apart by an interval in 113), the first anode layer is disposed on the planarization layer and connected to the source-drain through the first via hole (15 is on 14 and connected to 111 through 141),
an undercut opening (undercut structure 13), wherein the second anode layer has the undercut opening (undercut 13 corresponds to “second anode layer” 12), and the auxiliary electrode is exposed in the undercut opening (auxiliary electrode 110 is exposed in undercut 13); and a through hole (first opening 161), wherein the undercut opening is connected to the through hole (undercut 13 connects to through hole 161); a light-emitting layer disposed on the anode layer and being partially disconnected in the undercut opening, covering a portion of the auxiliary electrode layer in the undercut opening (light-emitting layer 17 is on anode layer 15, partially disconnected in undercut 13, and covers a portion of auxiliary electrode 110); and a cathode layer disposed on the light-emitting layer, covering a portion of the auxiliary electrode layer in the undercut opening (cathode electrode 18 exhibits the aforementioned structure); wherein the cathode layer is continuously disposed on the light-emitting layer, and a continuous portion of the cathode layer disposed in the undercut opening is disposed on a portion of the light-emitting layer disposed in the undercut opening and comprising a recess formed in the continuous portion, facing the light-emitting layer, and accommodating the portion of the light-emitting layer disposed in the undercut opening (cathode 18 exhibits the aforementioned structure as shown in L1 FIG. 10 and the annotated figure below). L1 does not explicitly disclose the second anode layer is disposed on the planarization layer and covers sidewalls of the second via hole, wherein along a vertical direction that the second anode layer comprises: a first electrode layer disposed on the planarization layer; a reflective layer disposed on the first electrode layer; a third electrode layer disposed on the reflective layer; the undercut opening penetrates the first electrode layer; or a through hole penetrating the reflective layer and the third electrode layer, a projection of the through hole on the substrate falls into a projection of the undercut opening on the substrate.
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However, in the same field of endeavor, S1 discloses in S1 FIG. 3-4 and associated text the second anode layer is disposed on the planarization layer and covers sidewalls of the second via hole (auxiliary electrode 260, corresponding to the second anode layer, is on overcoat layer 192, corresponding to the planarization layer, and covers sidewalls of second via hole VIA2), along a vertical direction that the second anode layer comprises: a first electrode layer disposed on the planarization layer (260 comprises conductive layer 261 on 192); a reflective layer disposed on the first electrode layer (reflective layer 262); a third electrode layer disposed on the reflective layer (conductive layer 263); the undercut opening penetrates the first electrode layer (as shown in S1 FIG. 4 and the annotated figure below); and a through hole penetrating the reflective layer and the third electrode layer (as shown in S1 FIG. 4 and the annotated figure below), a projection of the through hole on the substrate falls into a projection of the undercut opening on the substrate (as shown in S1 FIG. 4 and the annotated figure below).
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L1 teaches a base OLED display panel which the claimed invention can be seen as an improvement in that the anode layer comprises the same materials and is formed in the same process across different regions whereas the portions of the anode layer 12 and 15 disclosed by L1 are formed in separate stages. S1 teaches a known technique of forming both portions of the anode layer 210 and 260 at once, using the same materials for each of their layers to produce an OLED display panel that is comparable to the base process/product.
S1’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base OLED panel of L1 and the results would have been predictable and resulted in the OLED panel of L1 wherein portions of the anode layer 12 and 15 are replaced by the analogous anode layer structures of 260 and 210 respectively which results in an improved OLED panel.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding dependent claim 4, L1, as modified by S1, further discloses in S1 FIG. 13 and associated text The OLED display panel of claim 1, wherein the reflective layer and the third electrode layer comprise a plurality of protrusion portions protruding inward from the sidewalls of the second via hole (protrusions PR).
Regarding dependent claim 5, L1, as modified by S1, further discloses in S1 FIG. 3-4 and associated text The OLED display panel of claim 4, wherein the cathode layer is continuously disposed on the plurality of protruding portions (cathode electrode 230 exhibits the aforementioned structure in FIG. 3-4, though only one protruding portion PR is shown, S1 [0009] states: “the cathode electrode may be continuously formed on the at least one protrusion” (emphasis added)).
Regarding dependent claim 6, L1, as modified by S1, further discloses in S1 FIG. 3 and associated text The OLED display panel of claim 1, wherein the metal layer further comprises a pad layer spaced apart from the plurality of source-drain layers and the auxiliary electrode layer (metal layer 180 includes pad connection electrode 185), and an area along a vertical direction of the pad layer is defined as a bonding area (vertical surfaces of pad 185 are bonded to various structures as shown in S1 FIG. 3 and the annotated figure below).
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Regarding independent claim 7, L1 discloses in L1 FIG. 3-10 and associated text A fabrication method of an OLED display panel, comprising: providing an array substrate (array substrate 11), wherein the array substrate comprises
comprising: a substrate (base substrate 101); a buffer layer disposed on the substrate (buffer layer 104); an active layer disposed on the buffer layer (amorphous oxide semiconductor layer 105); a gate insulating layer disposed on the active layer (gate insulating layer 107); a gate layer disposed on the gate insulating layer (first metal conductive layer 108); an interlayer dielectric layer disposed on the gate layer (shield insulating layer 109); a metal layer disposed on the interlayer dielectric layer (layer comprising 110, 112, and 111), wherein the metal layer comprises a plurality of source-drain layers (source electrode 111 and drain electrode 112) and an auxiliary electrode layer (first auxiliary electrode 110) arranged at intervals in the same layer (110, 111, and 112 are spaced apart at intervals and on the same layer), and the plurality of source-drain layers are connected to the active layer (111 and 112 connect to 105 as shown); a passivation layer disposed on the auxiliary electrode and the plurality of source-drain layers (protective layer 113); a planarization layer disposed on the passivation layer (flat layer 14); a first via hole penetrating the planarization layer and the passivation layer from a side of the planarization layer away from the substrate (second via hole 141 penetrates 14 and 113), and the plurality of source-drain layers are exposed in the first via hole (141 exposing 111 is interpreted as exposing the plurality of source-drain layers); and a second via hole penetrating the planarization layer and the passivation layer from the side of the planarization layer away from the substrate (first opening 161 penetrates 14 and 113), and is spaced apart from the first via hole (141 and 161 are spaced apart), and the auxiliary electrode layer is exposed in the second via hole (110 is in 161 as shown);
and fabricating an anode layer on the array substrate (second auxiliary electrode 12, which is interpreted as an anode electrode, and anode electrode 15), wherein the anode layer comprises a first anode layer and a second anode layer arranged at intervals in the same layer (12 (second anode layer) and 15 (first anode layer) are spaced apart by an interval in 113), the first anode layer being fabricated on the planarization layer and connected to the source-drain through the first via hole (15 is on 14 and connected to 111 through 141), wherein the step of fabricating the anode layer specifically comprises: fabricating a through hole (first opening 161); fabricating an undercut opening (undercut structure 13), wherein the undercut opening is connected to the through hole (undercut 13 connects to through hole 161), and the auxiliary electrode is exposed in the undercut opening (auxiliary electrode 110 is exposed in undercut 13); fabricating a light-emitting layer on the anode layer and being partially disconnected in the undercut opening, and the light-emitting layer covering a portion of the auxiliary electrode layer in the undercut opening (light-emitting layer 17 is on anode layer 15, partially disconnected in undercut 13, and covers a portion of auxiliary electrode 110); fabricating a cathode layer on the light-emitting layer and covering a portion of the auxiliary electrode layer in the undercut opening (cathode electrode 18 exhibits the aforementioned structure); wherein the cathode layer is continuously disposed on the light-emitting layer, and a continuous portion of the cathode layer disposed in the undercut opening is disposed on a portion of the light-emitting layer disposed in the undercut opening and comprising a recess formed in the continuous portion, facing the light-emitting layer, and accommodating the portion of the light-emitting layer disposed in the undercut opening (cathode 18 exhibits the aforementioned structure as shown in L1 FIG. 10 and the annotated figure below). L1 does not explicitly disclose the second anode layer being fabricated on the planarization layer and covering sidewalls of the second via hole wherein the step of fabricating the anode layer specifically comprises: fabricating a first electrode layer on the array substrate; fabricating a reflective layer on the first electrode layer, fabricating a third electrode layer on the reflective layer; the undercut opening is on the first electrode layer, wherein a projection of the through hole on the array substrate falls into a projection of the undercut opening on the array substrate; or the through hole penetrates the first electrode layer and the third electrode layer from a side of the third electrode layer away from the array substrate and extends to a side of the auxiliary electrode away from the array substrate.
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However, in the same field of endeavor, S1 discloses in S1 FIG. 3-4 and associated text wherein the step of fabricating the anode layer (anode electrode 210 and auxiliary electrode 260, corresponding to the anode layer claimed and interpreted above in L1) specifically comprises: fabricating a first electrode layer on the array substrate (conductive layer 261 and lowest layer of anode 210); fabricating a reflective layer on the first electrode layer (reflective layer 262 and middle layer of 210, which is reflective (S1 [0090])), fabricating a third electrode layer on the reflective layer (conductive layer 263 and uppermost layer of anode 210); the through hole penetrates the first electrode layer and the third electrode layer from a side of the third electrode layer away from the array substrate and extends to a side of the auxiliary electrode away from the array substrate (as shown in S1 FIG. 4 and the annotated figure below); and the undercut opening is on the first electrode layer, wherein a projection of the through hole on the array substrate falls into a projection of the undercut opening on the array substrate (as shown in S1 FIG. 4 and the annotated figure below).
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L1 teaches a base fabrication method of an OLED display panel which the claimed invention can be seen as an improvement in that the anode layer comprises the same materials and is formed in the same process across different regions whereas the portions of the anode layer 12 and 15 disclosed by L1 are formed in separate stages. S1 teaches a known technique of forming both portions of the anode layer 210 and 260 at once, using the same materials for each of their layers to produce an OLED display panel that is comparable to the base process/product.
S1’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base fabrication method of an OLED panel of L1 and the results would have been predictable and resulted in the OLED panel of L1 wherein portions of the anode layer 12 and 15 are replaced by the analogous anode layer structures of 260 and 210 respectively which results in an improved fabrication method of an OLED panel.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Regarding dependent claim 10, L1, as modified by S1, further discloses in L1 FIG. 8-10 and S1 FIG. 4 associated text The fabrication method of claim 7, wherein the step of fabricating the light-emitting layer and the cathode layer comprise: controlling a vapor deposition angle of a vapor deposition source at a first set angle and forming the light-emitting layer on the anode layer by a vapor deposition (light-emitting layer 17 is formed by vapor deposition at first set angle a1 (L1 [0132])), wherein the light-emitting layer is disconnected in the undercut opening (light-emitting layer 17 exhibits the claimed structure in L1 FIG. 8), and there is a gap formed between the light-emitting layer on the auxiliary electrode layer and the light-emitting layer on the anode layer (S1’s electron transport layer 240, which is replaced by L1’s light-emitting layer 17 when combined, exhibits the aforementioned structure in S1 FIG. 4 and the annotated figure below); and adjusting the vapor deposition angle of the vapor deposition source to a second set angle, forming the cathode layer on the light-emitting layer by the vapor deposition and covering a portion of the auxiliary electrode layer in the undercut opening, wherein the cathode layer and the exposed auxiliary electrode layers are in contact with each other (cathode electrode 18 is formed by vapor deposition at second set angle a2 (L1 [0141]) and the resulting cathode layer exhibits the aforementioned structure in L1 FIG. 10).
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Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over L1, and further in view of S1 and Ahn et al. (US 7279765 B2, hereinafter A1).
Regarding dependent claim 8, L1, as modified by S1, discloses The fabrication method of claim 7, wherein the anode layer may comprise indium zinc oxide (S1 [0089]), a material of the reflective layer is one or more of molybdenum, titanium, silver alloy, aluminum alloy or molybdenum titanium alloys (the reflective layer may be an aluminum or silver alloy (S1 [0089])), and a material of the third electrode is indium tin oxide film (anode electrode 210 and 260 may be comprised of a triple layer including ITO/Ag/ITO (S1 [0090], [0098])). The references as combined do not explicitly disclose a material of the first electrode layer is an indium zinc oxide film.
However, in the same field of endeavor, A1 discloses in A1 FIG. 3 and associated text a material of the first electrode layer is an indium zinc oxide film (pixel electrode 20, corresponding to the first electrode layer claimed and interpreted in S1 above, is an IZO film (A1 (10)-(11))).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of fabricating an OLED display panel of L1, as modified by S1, with the use of IZO as the material of the first electrode layer of A1 to provide an OLED display panel with a first electrode layer exhibiting the desirable etching characteristics such as selectivity compared to ITO films (A1 (15)) and high bonding strength to organic insulating films (A1 (11)) on which the first electrode layer would be disposed such as L1’s flat layer 14 (flat layer 14 is organic, specifically a polyimide (L1 [0124]), therefore an interface between it and an IZO first layer would have high bond strength).
Regarding dependent claim 9, L1, as modified by S1 and A1, discloses in S1 FIG. 10 and L1 FIG. and corresponding text the fabrication method of claim 8, wherein the anode layer is etched by a wet etching process to form the through hole (S1’s electrode hole H, corresponding to the through hole claimed and interpreted in L1 above, is formed by wet etching (S1 [0125])), and etching the first electrode to form the undercut opening (S1’s undercut 13 is formed by ). The references as combined do not explicitly disclose the first electrode is etched by an oxalic acid.
However, in the same field of endeavor, A1 discloses in A1 Table 2 and associated text the first electrode is etched by an oxalic acid (a pixel electrode (20) is etched by C2H2O-4 (aka oxalic acid) (A1 claim 1)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of fabricating an OLED display panel of L1, as previously modified by S1 and A1, including the IZO/aluminum or silver alloy/ITO composition of the anode layers with the etching of IZO using oxalic acid of A1 to provide a method of fabricating an OLED display panel wherein etching the undercut can be performed within a shorter period of time using an oxalic acid which is selective to IZO (A1 (15)), mitigating damage to the ITO layer during the process.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20140167005 A1, pertaining to an OLED display using ITO/Ag/IZO in a multilayered electrode.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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