DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 and 22-28 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 11437304 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the reference claims requires substantially all of the limitations of the present claims.
The reference claims do not explicitly recite “a patterned metallic baseplate”, however the baseplate has metallic traces (“patterns”) formed on the insulated layers of the baseplate, similarly as Applicant’s, and thus may be construed as “patterned”. Further, dependent claim 7 recites wherein the metallic baseplate is patterned. Further, a physical baseplate has a specific size, shape, surface area, etc. once produced, which may be construed as a form or pattern, and would therefore have been obvious to one of ordinary skill in the art.
Pattern (Merriam-Webster’s Dictionary) - a form or model proposed for imitation.
Present Application
Reference US 11437304 B2
1. A semiconductor package, comprising:
a patterned metallic baseplate comprising a first surface and a second surface opposing the first surface;
a first laminate insulative layer comprising a first surface coupled to the second surface of the patterned metallic baseplate, the first laminate insulative layer having a second surface opposing the first surface of the first laminate insulative layer;
a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the second surface of the first laminate insulative layer at a first surface of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface opposing the first surface of the metallic trace;
one or more semiconductor devices comprising a first surface and a second surface opposing the first surface, wherein the first surface of the one or more semiconductor devices are coupled to the second surface of each one of the first plurality of metallic traces;
a second plurality of metallic traces comprising a first surface and a second surface, wherein the first surface of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface of the one or more semiconductor devices; and
a second laminate insulative layer comprising a first surface coupled to the second surfaces of the metallic traces of the second plurality of metallic traces.
1. A semiconductor package, comprising:
a metallic baseplate comprising a first surface and a second surface opposing the first surface;
an electrically insulative layer comprising a first surface coupled to the second surface of the metallic baseplate, the electrically insulative layer having a second surface opposing the first surface of the electrically insulative layer;
a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the second surface of the electrically insulative layer at a first surface of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface opposing the first surface of the metallic trace;
one or more semiconductor devices comprising a first surface and a second surface opposing the first surface, wherein the first surface of the one or more semiconductor devices are coupled to the second surface of each one of the first plurality of metallic traces;
a second plurality of metallic traces comprising a first surface and a second surface, wherein the first surface of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface of the one or more semiconductor devices;
a second insulative layer comprising a first surface coupled to the second surfaces of the metallic traces of the upper plurality of metallic traces; and
a mold compound encapsulating the one or more semiconductor devices;
wherein the the semiconductor package is configured to electrically couple to an external device through external connectors directly coupled to the first plurality of metallic traces and not to the second plurality of metallic traces.
7. The package of claim 1, wherein the metallic base plate is patterned.
2. The package of claim 1, further comprising a top metallic plate coupled to a second surface of the second laminate insulative layer, wherein the second surface of the second laminate insulative layer is opposite the first surface of the second laminate insulative layer.
2. The package of claim 1, further comprising a top metallic plate coupled to a second surface of the second insulative layer, wherein the second surface of the second insulative layer is opposite the first surface of the second insulative layer.
3. The package of claim 1, wherein the semiconductor devices include one of an IGBT, diode, MOSFET, a SiC device and a GaN device.
3. The package of claim 1, wherein the semiconductor devices include one of an IGBT, diode, MOSFET, a SiC device and a GaN device.
4. The package of claim 1, wherein the package does not comprise one of wire bonds or clips.
6. The package of claim 1, wherein the package does not comprise one of wire bonds and clips.
5. The package of claim 2, wherein the top metallic plate is patterned.
8. The package of claim 2, wherein the top metallic plate is patterned.
22. (New) A semiconductor package, comprising:
a patterned metallic baseplate comprising a first surface and a second surface opposing the first surface;
an electrically insulative layer comprising a first surface coupled to the second surface of the patterned metallic baseplate, the electrically insulative layer having a second surface opposing the first surface of the electrically insulative layer;
a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the second surface of the electrically insulative layer at a first surface of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface opposing the first surface of the metallic trace;
one or more semiconductor devices
comprising a first surface and a second surface opposing the first surface, wherein the first surface of the one or more semiconductor devices are coupled to the second surface of each one of the first plurality of metallic traces;
a second plurality of metallic traces comprising a first surface and a second surface, wherein the first surface of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface of the one or more semiconductor devices;
a second insulative layer comprising a first surface coupled to the second surfaces of the metallic traces of the upper plurality of metallic traces; and
a mold compound encapsulating the one or more semiconductor devices;
wherein the semiconductor package is configured to electrically couple to an external device through external connectors directly coupled to the first plurality of metallic traces and not to the second plurality of metallic traces.
1. A semiconductor package, comprising:
a metallic baseplate comprising a first surface and a second surface opposing the first surface;
an electrically insulative layer comprising a first surface coupled to the second surface of the metallic baseplate, the electrically insulative layer having a second surface opposing the first surface of the electrically insulative layer;
a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the second surface of the electrically insulative layer at a first surface of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface opposing the first surface of the metallic trace;
one or more semiconductor devices comprising a first surface and a second surface opposing the first surface, wherein the first surface of the one or more semiconductor devices are coupled to the second surface of each one of the first plurality of metallic traces;
a second plurality of metallic traces comprising a first surface and a second surface, wherein the first surface of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface of the one or more semiconductor devices;
a second insulative layer comprising a first surface coupled to the second surfaces of the metallic traces of the upper plurality of metallic traces; and
a mold compound encapsulating the one or more semiconductor devices;
wherein the the semiconductor package is configured to electrically couple to an external device through external connectors directly coupled to the first plurality of metallic traces and not to the second plurality of metallic traces.
7. The package of claim 1, wherein the metallic base plate is patterned.
23. (New) The package of claim 22, further comprising a top metallic plate coupled to a second surface of the second insulative layer, wherein the second surface of the second insulative layer is opposite the first surface of the second insulative layer.
2. The package of claim 1, further comprising a top metallic plate coupled to a second surface of the second insulative layer, wherein the second surface of the second insulative layer is opposite the first surface of the second insulative layer.
24. (New) The package of claim 22, wherein the semiconductor devices include one of an IGBT, diode, MOSFET, a SiC device and a GaN device.
3. The package of claim 1, wherein the semiconductor devices include one of an IGBT, diode, MOSFET, a SiC device and a GaN device.
25. (New) The package of claim 22, wherein the electrically insulative layer is one of a ceramic insulated layer and a laminate insulated layer.
4. The package of claim 1, wherein the electrically insulative layer is one of a ceramic insulated layer and a laminate insulated layer.
26. (New) The package of claim 22, wherein the second insulative layer is one of a ceramic insulated layer and a laminate insulated layer.
5. The package of claim 1, wherein the second insulative layer is one of a ceramic insulated layer and a laminate insulated layer.
27. (New) The package of claim 22, wherein the package does not comprise one of wire bonds and clips.
6. The package of claim 1, wherein the package does not comprise one of wire bonds and clips.
28. (New) The package of claim 23, wherein the top metallic plate is patterned.
8. The package of claim 2, wherein the top metallic plate is patterned.
Claim Objections
Claims 3 and 24 objected to because of the following informalities:
Claims 3 and 24 each recite acronyms (IGBT, MOSFET) without spelling them out first (not required for chemical formulas SiC and GaN).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 22-28 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rizza (US 9986631 B2).
Examiner notes that the earliest support for the claimed limitations is in parent application no. 15440967 with a filing date of 02/23/2017. There is no support for the specific arrangement of semiconductor devices and first and second plurality of metallic traces in application no. 15206574. Thus, the earliest effective filing date for the present application is 02/23/2017.
As to claim 1, Rizza discloses: A semiconductor package (Fig. 2), comprising:
a patterned metallic baseplate 23, 47 (see col. 3, lines 41-44; col. 4, lines 50-64; the baseplate has metallic traces (“patterns”) formed on the insulated layer of the baseplate, similarly as Applicant’s, and thus may be construed as “patterned”. Further, the baseplate is patterned or formed as a plate shaped layer of a certain size, shape, surface area, etc.; Pattern - a form or model proposed for imitation; Merriam-Webster’s Dictionary) comprising a first surface (bottom/lower surface) and a second surface (top/upper surface) opposing the first surface;
a first laminate insulative layer 46 (col. 4, lines 50-64) comprising a first surface (bottom/lower surface) coupled (at least indirectly) to the second surface of the patterned metallic baseplate, the first laminate insulative layer having a second surface (top/upper surface) opposing the first surface of the first laminate insulative layer;
a first plurality of metallic traces 30 (alternatively – 30, 48, and 61; col. 3, lines 55-65 and col. 4, lines 32-64), each metallic trace of the first plurality of metallic traces coupled (through 48) to the second surface of the first laminate insulative layer 46 at a first surface (bottom/lower surface) of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface (top/upper surface) opposing the first surface of the metallic trace;
one or more semiconductor devices 33, 35 (col. 4, lines 14-20) comprising a first surface (bottom/lower surface) and a second surface (top/upper surface) opposing the first surface, wherein the first surface (bottom/lower surface) of the one or more semiconductor devices 33, 35 are coupled to the second surface (top/upper surface) of each one of the first plurality of metallic traces 30;
a second plurality of metallic traces 34 (alternatively - 34, 36, 32, 37, and 50; col. 3, lines 55-65 and col. 4, lines 32-64;) comprising a first surface and a second surface, wherein the first surface (bottom/lower surface) of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface (top/upper surface) of the one or more semiconductor devices 33, 35; and
a second laminate insulative layer 49 (col. 4, lines 50-64) comprising a first surface (bottom/lower surface) coupled to the second surfaces (top/upper surface) of the metallic traces of the second plurality of metallic traces.
As to claim 22, Rizza discloses: A semiconductor package (Fig. 2), comprising:
a patterned metallic baseplate 23, 47 (see col. 3, lines 41-44; col. 4, lines 50-64; the baseplate has metallic traces (“patterns”) formed on the insulated layer of the baseplate, similarly as Applicant’s, and thus may be construed as “patterned”. Further, the baseplate is patterned or formed as a plate shaped layer of a certain size, shape, surface area, etc.; Pattern - a form or model proposed for imitation; Merriam-Webster’s Dictionary) comprising a first surface (bottom/lower surface) and a second surface (top/upper surface) opposing the first surface;
an electrically insulative layer 46 (col. 4, lines 50-64) comprising a first surface (bottom/lower surface) coupled (at least indirectly) to the second surface of the patterned metallic baseplate, the electrically insulative layer having a second surface (top/upper surface) opposing the first surface of the electrically insulative layer;
a first plurality of metallic traces (30, 48, and 61 combined; col. 3, lines 55-65 and col. 4, lines 32-64), each metallic trace of the first plurality of metallic traces coupled (through 48) to the second surface of the electrically insulative layer 46 at a first surface (bottom/lower surface) of the metallic trace, each metallic trace of the first plurality of metallic traces having a second surface (top/upper surface) opposing the first surface of the metallic trace;
one or more semiconductor devices 33, 35 (col. 4, lines 14-20) comprising a first surface (bottom/lower surface) and a second surface (top/upper surface) opposing the first surface, wherein the first surface (bottom/lower surface) of the one or more semiconductor devices 33, 35 are coupled to the second surface (top/upper surface) of each one of the first plurality of metallic traces (30 on top of 48);
a second plurality of metallic traces (34, 36, 32, 37, and 50 combined; col. 3, lines 55-65 and col. 4, lines 32-64) comprising a first surface and a second surface, wherein the first surface (bottom/lower surface) of at least one metallic trace of the second plurality of metallic traces is coupled to the second surface (top/upper surface) of the one or more semiconductor devices 33, 35; and
a second insulative layer 49 (col. 4, lines 50-64) comprising a first surface (bottom/lower surface) coupled to the second surfaces (top/upper surface) of the metallic traces of the second plurality of metallic traces; and
a mold compound 52 (col. 4, lines 24-36) encapsulating the one or more semiconductor devices;
wherein the semiconductor package is configured to electrically couple to an external device through external connectors 38 directly coupled to the first plurality of metallic traces 30, 48, 61 and not to the second plurality of metallic traces.
As to claims 2 and 23, Rizza discloses: further comprising a top metallic plate 51 (col. 4, lines 50-64) coupled to a second surface (top/upper surface) of the second laminate insulative layer 49, wherein the second surface (top/upper surface) of the second laminate insulative layer 49 is opposite the first surface (bottom/lower surface) of the second laminate insulative layer 49.
As to claims 3 and 24, Rizza discloses: wherein the semiconductor devices include one of an IGBT 33 (col. 4, lines 14-20), diode 35, MOSFET, a SiC device and a GaN device.
As to claims 4 and 27, Rizza discloses: wherein the package does not comprise one of wire bonds or clips (neither are mentioned – 38 are terminal pins, which do not explicitly correspond to wire bonds).
As to claims 5 and 28, Rizza discloses: wherein the top metallic plate is patterned (the top metallic plate has metallic traces (“patterns”) formed on the insulated layer of the top metallic plate, similarly as Applicant’s, and thus may be construed as “patterned”. Further, the top plate is patterned or formed as a plate shaped layer of a certain size, shape, surface area, etc.). Pattern - a form or model proposed for imitation (Merriam-Webster’s Dictionary).
As to claim 6 (alternatively), Rizza discloses:
wherein the second plurality of metallic traces 34, 36, 32, 37, and 50 comprises multiple thicknesses (see Fig. 2, multiple recesses and gaps).
As to claim 7, Rizza discloses: wherein the first plurality of metallic traces is directly coupled (consistent with applicant’s interpretation of 144, 150, 132 in Fig. 31 and p. 7-8 of the Remarks) to the second plurality of metallic traces (by portions 36).
As to claim 25, Rizza discloses:
wherein the electrically insulative layer 46 is one of a ceramic insulated layer (ceramic; col. 4, lines 50-64) and a laminate insulated layer.
As to claim 26, Rizza discloses:
wherein the second insulative layer 49 is one of a ceramic insulated layer (ceramic; col. 4, lines 50-64) and a laminate insulated layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rizza (US 9986631 B2) as applied to claim 1 above, and further in view of Koyama (US 7501696 B2).
As to claim 6 (alternatively), Rizza does not explicitly disclose: wherein the second plurality of metallic traces comprises multiple thicknesses.
However, Koyama discloses:
wherein the plurality of metallic traces 55, 58 (Fig. 2B-2E) comprises multiple thicknesses (see 55 above 52, 58 above the single chip of chip stack 57, and 58 above both chips in chip stack 57);
in order to provide metallic trace connections to connection pads 52, through holes 53, and single and doubly stacked semiconductor chips (col. 4, lines 11-64).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Rizza as suggested by Koyama, e.g., providing:
wherein the second plurality of metallic traces comprises multiple thicknesses;
in order to provide metallic trace connections to connection pads, through holes, and single and doubly stacked semiconductor chips.
Additionally, all claimed elements were known in the prior art and one skilled in the art could have combined/modified the elements as claimed by known methods with no change in their respective functions, and the combination/modification would have yielded predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. See KSR International Co. v. Teleflex Inc., 550 U.S.___, 82 USPQ2d 1385 (2007).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rizza (US 9986631 B2) as applied to claim 1 above, and further in view of Ch’ng (US 7375288 B1).
As to claim 8, Rizza does not explicitly disclose: wherein one of the first plurality of metallic traces, the second plurality of metallic traces, or the first plurality of metallic traces and the second plurality of metallic traces are formed from a metal foil.
However, Ch’ng discloses:
wherein metallic traces are formed from a metal foil (col. 4, lines 10-23);
in order to provide conventional printed circuit board construction and provide any number of traces/conductive paths of copper foil (col. 4, lines 10-23).
It would have been obvious to one of ordinary skill in the related art(s) before the effective filing date of the claimed invention to modify the device of Rizza as suggested by Ch’ng, e.g., providing:
wherein one of the first plurality of metallic traces, the second plurality of metallic traces, or the first plurality of metallic traces and the second plurality of metallic traces are formed from a metal foil;
in order to provide conventional printed circuit board construction and provide any number of traces/conductive paths of copper foil.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Additionally, all claimed elements were known in the prior art and one skilled in the art could have combined/modified the elements as claimed by known methods with no change in their respective functions, and the combination/modification would have yielded predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. See KSR International Co. v. Teleflex Inc., 550 U.S.___, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 21, the allowability resides in the overall structure and functionality of the apparatus as recited in the claim, including all of the limitations of their base claims and intervening claims, and at least in part, because they recite the following limitations:
21. (New) The package of claim 1, wherein a plurality of thicker portions are directly coupled between the first plurality of traces and the second plurality of traces and one of the plurality of thicker portions is coupled between the semiconductor devices.
None of the prior art, either alone or in combination, can be reasonably construed as adequately teaching the above claimed elements, in combination with the remaining claim limitations.
Further, Examiner has not identified any double patenting issues.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 1/12/2026 have been fully considered but they are not persuasive.
Claim Limitation Not Taught/Special Definition of “Patterned”
Applicant has suggested that the term pattern has been improperly interpreted because “patterned” in reference to the “patterned metallic baseplate” has a special definition in light of the specification (Remarks, p. 8-11).
In response, the cited par. (par. 0115 in the printed publication) refers to Fig. 31, and reads in entirety:
“[0115] Referring now to FIG. 31, a cross-section view of a wirebond-less (bond wire-less) interconnection semiconductor package is illustrated. The package may include a metallic baseplate 120. The baseplate includes a first surface 122 opposing a second surface 124. The metallic baseplate 120 may be, by non-limiting example, copper, tungsten, nickel, gold, palladium, or any other metal or combination of metals, including any disclosed in this document. The metallic baseplate may be patterned in various implementations, increasing thermal dissipation and/or permitting for electrical signal routing/power transfer. In various implementations, the patterning may be carried using any method disclosed herein. The metallic baseplate 120 may also be configured to couple to a heatsink in various implementations.”
PNG
media_image1.png
464
974
media_image1.png
Greyscale
Fig. 31 illustrates a metallic baseplate 120 with no discernable features. “The metallic baseplate may be patterned… increasing thermal dissipation and/or permitting for electrical signal routing/power transfer.”
The passage does not identify what patterning is but identifies that it may increase thermal dissipation and/or permit signal routing/power transfer. It is not required to do both. A metallic baseplate itself dissipates heat. The specific size, shape, and/or surface area of the baseplate affects the amount of heat dissipation (e.g., a larger surface area plate vs a smaller surface area plate), and thus the inherent size, shape, and/or surface area of the baseplate may be interpreted as patterning.
“[0126] The structure of FIG. 33 may include a metallic baseplate 166. The metallic baseplate may be patterned to form metallic traces similar to metallic traces 164. The metallic baseplate may be, by non-limiting example, copper, tungsten, nickel, gold, palladium, or any other metal or combination of metals disclosed herein. In other implementations, as illustrated by FIG. 34, the multiple thickness substrate structure may not include the metallic baseplate.”
PNG
media_image2.png
286
1006
media_image2.png
Greyscale
Examiner notes that the baseplate is referenced as 166 (a flat plate). 162 is an insulative layer and the pattern of traces 164 is formed on top of the insulative layer 162 and on top of the baseplate 166. This appears to indicate that the combination of traces and baseplate form a patterned baseplate (equivalent to the device of Rizza), and the pattern is not a feature of the baseplate itself.
Thus, the specification does not sufficiently redefine the term to identify that “patterned” refers to any particular feature, and the rejections are maintained.
112 Rejection Withdrawn
Regarding claim 7, Applicant has pointed out that the thick portions 150 (Fig. 31) are considered to be a part of the second plurality of metal traces 144, despite being shown as a separate layer/element, and that thus the second metallic traces 144, 150 are directly coupled to the first metallic traces 132 (Remarks, p. 7).
Examiner accepts this interpretation, has withdrawn the 112 rejection, and interprets the device of Rizza similarly – namely where combinations of conductive layers are considered to constitute the respective first and second metallic traces and provide direct coupling.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R CRUM whose telephone number is (571)270-7665. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached at (571) 272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACOB R CRUM/ Primary Examiner, Art Unit 2835