DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 27 October 2025 has been entered.
Response to Amendment
The Office acknowledges receipt on 27 October 2025 of Applicants’ amendment in which claim 1 is amended. The Office withdraws the section 112(b) rejection identified in the Office Communication dated 11 September 2025 in view of the amendment.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 7-10, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (US20220208992A1) in view of Hsu (US20160314839A1).
Regarding claim 1, Chou teaches in Fig. 12 a charge-trapping semiconductor device comprising:
a lower wide-bandgap semiconductor channel layer (104) of a first conductivity type (n/p-type) {[0021]; e.g., GaN is a wide bandgap semiconductor};
a barrier layer (106) disposed on the lower wide-bandgap semiconductor channel layer (104) {[0017]; Chou’s barrier layer (106) is made of same material as in the instant application and is disposed between semiconductor layers of the same material as in the instant application – thus it has the same properties (e.g., barrier) as with the instant application};
an upper wide-bandgap semiconductor channel layer (108) of a second conductivity type (p/n-type), opposite to the first conductivity type (n/p-type), and disposed on the barrier layer (106) {[0023]; e.g., GaN is a wide bandgap semiconductor}; and
a control gate (118) disposed over the upper wide-bandgap semiconductor channel layer (108) {[0034]},
wherein the charge-trapping semiconductor device further comprises an insulating layer (111 and/or 112) sandwiched between the control gate (118) and the upper wide-bandgap semiconductor channel layer (108) {¶0024}.
Chou does not expressly teach wherein a charge-trapping interface is formed at an interface between the upper wide-bandgap semiconductor channel layer and the insulating layer.
In an analogous art, Hsu teaches in Fig. 2C and paragraph [0030] a charge-trapping interface (103, 104, and/or 105) is formed at an interface between a semiconductor channel layer (106 between 110a, 110b and potentially 110a, 110b) and an insulating layer (102). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chou’s device based on the teachings of Hsu – such that Hsu’s charge-trapping interface is formed at an interface between Chou’s upper wide-bandgap semiconductor channel layer and Chou’s insulating layer – for injecting charge from a channel region into the charge-trapping layer based on voltage differentials between a gate and the channel region {Hsu ¶0009} to provide the functionality of a memory device {Hsu ¶0007}.
Regarding claim 2, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chou further teaches
wherein the upper wide-bandgap semiconductor channel layer (108) is of n-type or p-type conductivity {[0023]};
wherein the lower wide-bandgap semiconductor channel layer (104) is of p-type or n-type conductivity {[0021]}.
Regarding claim 5, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chen further teaches wherein the insulating layer (111 and/or 112) is made of oxide materials selected from SiO, AlO, GaO, ZrO, HfO, or HfZrO, or nitride dielectric materials selected from SiN, SiON, AlON, or GaON {[0024]; SiN/SiON/SiO}.
Regarding claim 7, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chou further teaches
wherein the barrier layer (106) is a semiconductor material (AlN/AlGaN) with a wider bandgap than that of the upper (108) or lower (106) wide-bandgap semiconductor channel layer (106, 108 are GaN) {[0022]; AlN has a bandgap of about 6.2 eV, GaN has a bandgap of about 3.4 eV, AlGaN between 3.4 eV and 6.2 eV},
wherein the semiconductor material (AlN/AlGaN) comprises AlN, AlGaN, or other semiconductor materials forming a heterojunction structure with the upper or lower wide-bandgap semiconductor channel layer (106/108) (heterojunction is implicit because AlN/AlGaN and GaN are different materials).
Regarding claim 8, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chou further teaches
wherein the upper wide-bandgap semiconductor channel layer (108) is selected from p-type GaN, p-type SiC, p-type AlN, p-type Ga2O3, p-type diamond {[0023]; e.g., p-type GaN};
wherein the lower wide-bandgap semiconductor channel layer (104) is selected from n-type GaN, n-type SiC, n-type AlN, n-type Ga2O3, n-type diamond {[0021]; e.g., n-type GaN}.
Regarding claim 9, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chou further teaches further comprising
a buffer layer (102) and a substrate (100) such that the buffer layer (102) is sandwiched between the lower wide-bandgap semiconductor channel layer (104) and the substrate (100) {[0019]},
wherein the substrate (100) is selected from silicon, sapphire, diamond, SiC, AlN, or GaN {[0017-0018]; e.g., Si/SiC/AlN/sapphire}; and
the buffer layer (102) is selected from AlN, GaN, InN, or any alloys thereof {[0022]; e.g., AlN/GaN}.
Regarding claim 10, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, but Chou does not teach a complementary logic circuit comprising the charge-trapping semiconductor device of claim 1.
Hsu teaches in Fig. 2C and paragraphs [0007] and [0009] injecting charge from a channel region (layer containing 110a and 110b) into a charge-trapping layer (103, 104, and/or 105) based on voltage differentials between a gate (101) and the channel region (layer containing 110a and 110b) to provide the functionality of a memory device. Hsu further teaches in paragraph [0051] the memory device may be implemented in CMOS. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chou’s device as modified by Hsu based on the further teachings of Hsu – such that a complementary logic circuit comprises the device of claim 1 – because [t]he selection of a known [component] … based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 22, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chou further teaches wherein the upper wide-bandgap semiconductor channel layer (108) is selected from n-type GaN, n-type SiC, n-type AlN, n-type Ga2O3, or n-type diamond {[0041]; e.g., n-type GaN}, wherein the lower wide-bandgap semiconductor channel layer (104) is selected from p-type GaN, p-type SiC, p-type AlN, p-type Ga2O3, or p-type diamond {[0021]; e.g., p-type GaN}.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Hsu as applied to claim 1 above, and further in view of Chiang et al. (US20160071969A1).
Regarding claim 3, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, and Chou further teaches further comprising:
two further source contacts (124, 126) disposed on two other opposing sides of the control gate (118) and being in contact with the barrier layer (106) {[0035]}.
Chou does not teach a source contact and a drain contact disposed on two opposing sides of the control gate and being in contact with the upper wide-bandgap semiconductor channel layer.
In an analogous art, Chiang teaches in Fig. 1 and paragraph [0019-0021] a source contact (115 or 113, 115) and a drain contact (119 or 113, 119) are disposed on two opposing sides of a control gate (123) and in contact with an upper wide-bandgap semiconductor channel layer (113/111; InGaN/AlGaN). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chou’s device as modified by Hsu based on the teachings of Chiang – such that a source contact and a drain contact disposed on two opposing sides of the control gate and being in contact with the upper wide-bandgap semiconductor channel layer – so the ohmic performance of the semiconductor device … is … improved. Chiang [0021].
Claim(s) 6 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou in view of Hsu as applied to claim 1 above, and further in view of Min et al. (US20090097320A1).
Regarding claim 6, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, but Chou does not teach wherein the charge-trapping interface is formed by a charge trapping layer that is sandwiched between the insulating layer and the upper wide-bandgap semiconductor channel layer.
Hsu teaches in Fig. 2C and paragraph [0030] a charge-trapping interface (103, 104, and/or 105) is formed by a charge trapping layer (103, 104, and/or 105) that is sandwiched between an insulating layer (102) and a semiconductor channel layer (106 between 110a, 110b and potentially 110a, 110b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chou’s device as modified by Hsu based on the further teachings of Hsu – such that the charge-trapping interface is formed by a charge trapping layer that is sandwiched between Chou’s insulating layer and Chou’s upper wide-bandgap semiconductor channel layer – for injecting charge from a channel region into the charge-trapping layer based on voltage differentials between a gate and the channel region {Hsu [0009]} to provide the functionality of a memory device {Hsu [0007]}.
Chou as modified by Hsu does not teach wherein the charge trapping layer is selected from a heavily doped semiconductor layer, or a metal layer.
In an analogous art, Min teaches in Fig. 3 and paragraph [0036] the charge trapping layer (18/22/26) is selected from a heavily doped semiconductor layer or a metal layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chou’s device as modified by Hsu based on the teachings of Min – such that the charge trapping layer is selected from a heavily doped semiconductor layer, or a metal layer – because such are programmed and erased primarily with electrons, rather than with holes [which] can damage the … materials through which the holes pass. Min [0036]. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 21, Chou as modified by Hsu teaches the charge-trapping semiconductor device of claim 1, but Chou does not teach wherein the charge-trapping interface is a modified semiconductor surface of the upper wide-bandgap semiconductor channel layer that is in direct contact with the insulating layer.
Min teaches in Fig. 3 and paragraph [0036] the charge-trapping interface is a semiconductor channel layer (18) that is in direct contact with an insulating layer (20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chou’s device as modified by Hsu based on the further teachings of Min – such that Hsu’s charge-trapping interface is (i.e., becomes) a modified semiconductor surface (as taught by Min) of Hsu’s semiconductor channel layer – because such are programmed and erased primarily with electrons, rather than with holes [which] can damage the … materials through which the holes pass. Min ¶0036. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. A consequence of this modification is that Hsu’ semiconductor channel layer becomes in direct contact with Hsu’s insulating layer, due to the substitution of Min’s modified semiconductor, as a charge trapping interface, for Hsu’s charge trapping interface. A further consequence of this modification is that the fully-modified charge-trapping interface is a modified semiconductor surface of Chou’s upper wide-bandgap semiconductor channel layer.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US20140252369A1) teaches a nitride-based semiconductor device including a substrate; a GaN-containing layer on the substrate; a nitride-containing layer on the GaN layer; a channel blocking layer on the nitride-containing layer, the channel blocking layer including a nitride-based semiconductor; a gate insulation layer on the channel blocking layer; and a gate electrode on the gate insulation layer.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891