Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Currently claims “1-5, 7-9, 11, 19-23, 25-26, 30, 32, 40 and 42-43” are under examination, and claims “6,12-18, 27-29 and 33-39” have been withdrawn from further consideration.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7, 9, 11, 19-23, 25-26, 30-32, 40 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (Pub. No. US 2017/0194344 A1, herein Wu) in view of Bojarczuk, JR et al. (Pub. No. US 2005/0269634 A1, herein Bojarczuk), and further in view of Kim et al. (Pub. No. US 2005/0156256 A1, herein Kim).
Regarding claim 1, Wu discloses a semiconductor device structure, comprising: a semiconductor substrate 106 (Wu: Fig. 2 and paragraphs [0012]); a first device formed 112b/112c in a first region 104 of the semiconductor substrate, the first device 112b/112c comprising a first gate structure on the semiconductor substrate, wherein the first gate structure comprises: a first gate dielectric layer 206-116 on the semiconductor substrate; and a first gate layer 114 on the first gate dielectric layer (Wu: Fig. 2 and paragraphs [0019]-[0021]); and a second device 118a formed in a second region 102 of the semiconductor substrate, the second device comprising a second gate structure on the semiconductor substrate, wherein the second gate structure comprises: a second gate dielectric layer 124-204-206-119 on the semiconductor substrate; and a second gate layer 122 on the second gate dielectric layer, wherein the first gate dielectric layer of the first device and the second gate dielectric layer of the second device have different dielectric material compositions ((Wu: Fig. 2 and paragraphs [0013]-[0021]).
Wu does not specifically show that the first gate dielectric layer consists of only a single dielectric material layer.
However, in the same field of endeavor, Bojarczuk teaches a semiconductor device, comprising: a first gate structure 25 having a first gate dielectric layer 20 on a semiconductor substrate 12, wherein the first gate dielectric layer is a single dielectric material layer, and a second gate structure 15 having gate dielectric layers 20 and 22 to stabilize the second device regions threshold voltage and flatband voltage without shifting the first device regions threshold voltage and flatband voltage (Bojarczuk: Fig. 8 and paragraphs [0027], [0036]-[0040]).
Therefore, given the teachings of Bojarczuk, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Wu in view of Bojarczuk by employing the first gate dielectric layer made of only a single dielectric material layer.
The previous combination does not specifically state wherein the second gate dielectric layer comprises a hafnium oxide (HfOx) layer and a lanthanum oxide (LaOx) layer stacked in sequence over the substrate.
However, in the same field of endeavor, Kim teaches a semiconductor device, wherein the second gate dielectric layer comprises a hafnium oxide (HfOx) layer and a lanthanum oxide (LaOx) layer stacked in sequence over the substrate because lanthanum oxide has a crystallization temperature of about 900 ºC, it functions as a leakage current barrier layer, thereby contributing to the excellent thermal stability and low leakage levels of the stacked layers (Kim: Figs. 5, 8, 14 and paragraphs [0025], [0047], [0048]).
Therefore, given the teachings of Kim, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Kim by employing the HfOx–LaOx stack layer.
Regarding claim 2, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein the first gate dielectric layer 206-116 has a first dielectric constant, the second gate dielectric layer 124-204-206-119 has a second dielectric constant, and the first dielectric constant is different from the second dielectric constant (Wu: Fig. 2 and paragraph [0021]).
Regarding claim 3, Wu in view of Bojarczuk teaches the semiconductor device structure as claimed in claim 1, wherein the first device and the second device are high-voltage metal oxide semiconductor (MOS) devices (Wu: Fig. 2 and paragraphs [0015], [0019]-[0020]).
Regarding claim 4, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein a first dielectric constant of the first gate dielectric layer and a second dielectric constant of the second gate dielectric layer are equal to or greater than 20 (Wu: Fig. 2 and paragraph [0021]; For example, the dielectric constant of hafnium oxide typically ranges between 20 and 25. The exact value can vary depending on deposition method, film thickness, crystal structure and measurement frequency.).
Regarding claim 5, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 4, wherein the second dielectric constant of the second gate dielectric layer is greater than the first dielectric constant of the first gate dielectric layer (Wu: Fig. 2 and paragraphs [0015], [0019]-[0021]).
Regarding claim 7, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein the first gate dielectric layer has a first thickness, the second gate dielectric layer has a second thickness, and the first thickness is different from the second thickness (Wu: Fig. 2 and paragraphs [0015], [0019]-[0021]).
Regarding claims 8 and 24, Wu, in paragraph [0019] says “because of the different operating voltages the devices may have gate electrodes overlying different gate dielectric thicknesses (e.g., the high voltage device 112a has one or more underlying oxide(s) with a collective greater thickness than the core device 112b and the I/O device 112c)” but does not specifically state the range of 1 to 50 Angstrom for the thicknesses of the gate dielectric layers. However, the claimed range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. Thinner gate dielectric layers allow stronger electric field coupling between the gate and the channel and lowers the threshold voltage, but increase quantum tunneling and gate leakage current. Thus, thinner gate dielectric layers provide better control of the current flow, higher performance but more leakage, whereas thicker gate dielectric layers provide less leakage, worse control and slower switching, and optimal design balances these trade-offs using advanced materials and engineering. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed thickness range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 9, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein the second gate dielectric layer comprises multiple dielectric material layers (Wu: Fig. 2 and paragraphs [0015], [0019]-[0021]).
Regarding claim 11, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 10, wherein the first gate dielectric layer and the second gate dielectric layer have a different number of the dielectric material layers (Wu: Fig. 2 and paragraphs [0019]-[0021]).
Regarding claim 19, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein the first gate dielectric layer and the second gate dielectric layer each includes hafnium oxide (HfOx), lanthanum oxide (LaOx), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or a combination thereof (Wu: Fig. 2 and paragraph [0021]).
Regarding claim 20, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, further comprising: a third device 118b formed in a third region of the semiconductor substrate (The term “region” is a broad term and it is considered to be any section of the substrate that is not the first or second regions.), the third device comprising a third gate structure on the semiconductor substrate, wherein the third gate structure comprises: a third gate dielectric layer 204-206-116 on the semiconductor substrate; and a third gate layer 120 on the third gate dielectric layer, wherein the third gate dielectric layer and the first gate dielectric layer have different dielectric material compositions, and the third gate dielectric layer and the second gate dielectric layer have different dielectric material compositions (Wu: Fig. 2 and paragraphs [0013]-[0021]).
Regarding claim 21, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 20, wherein the first gate dielectric layer has a first dielectric constant, the second gate dielectric layer has a second dielectric constant, and the third gate dielectric layer has a third dielectric constant, wherein the first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other (Wu: Fig. 2 and paragraphs [0013]-[0021]).
Regarding claim 22, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 20, wherein each of the first dielectric constant, the second dielectric constant, and the third dielectric constant is equal to or greater than 20 (Wu: Fig. 2 and paragraphs [0013]-[0021]).
Regarding claim 23, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 20, wherein the first gate dielectric layer has a first thickness, the second gate dielectric layer has a second thickness, and the third gate dielectric layer has a third thickness, wherein the first thickness, the second thickness and the third thickness are different from each other (Wu: Fig. 2 and paragraphs [0013]-[0021]).
Regarding claim 25, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 20, wherein at least one of the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer comprises multiple dielectric material layers (Wu: Fig. 2 and paragraphs [0013]-[0021]).
Regarding claim 26, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 25, wherein the third gate dielectric layer and the second gate dielectric layer have a different number of the dielectric material layers (Wu: Fig. 2 and paragraphs [0013]-[0021]).
Regarding claim 30, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 20, wherein the third gate dielectric layer includes hafnium oxide (HfOx), lanthanum oxide (LaOx), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or a combination thereof (Wu: Fig. 2 and paragraph [0021]).
Regarding claim 31, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 20, wherein the third device is a high-voltage metal oxide semiconductor (MOS) device (Wu: Fig. 2 and paragraphs [0015], [0019]-[0020]).
Regarding claim 32, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein the first device further comprises a first source region 126 and a first drain region 126 at opposite sides of the first gate structure, and the second device further comprises a second source region and a second drain region at opposite sides of the second gate structure (Wu: Fig. 2 and paragraphs [0013], [0018]. [0032]).
Regarding claim 40, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 1, wherein the first gate dielectric layer is in direct contact with the substrate, and the first gate dielectric layer has a dielectric constant equal to or greater than 20 (Wu: Fig. 2 and paragraphs [0015], [0019]-[0021], and Bojarczuk: Fig. 8 and paragraphs [0046]-[0048]).
Regarding claim 42, Wu in view of Bojarczuk and further in view of Kim teaches the semiconductor device structure as claimed in claim 41, wherein the dielectric material layers of the second gate dielectric layer comprise different materials (Wu: Fig. 2 and paragraphs [0015], [0019]-[0021], Bojarczuk: Fig. 8 and paragraphs [0046]-[0048], and Kim: Figs. 5, 8, 14 and paragraphs [0025], [0047], [0048]).
The applicant is further referred to paragraphs [0003], [0025] and [0035] of Lin et al. (Pub. No. US 2014/0151710 A1).
Allowable Subject Matter
Claim 43 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claim 43, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the third gate dielectric layer comprises a hafnium oxide (HfOx) layer, a first lanthanum oxide (LaOx) layer, and a second lanthanum oxide (LaOx) layer stacked in sequence over the substrate.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-9, 11, 19-23, 25-26, 30, 32, 40 and 42 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
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January 24, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813