Attorney’s Docket Number: 20353.0266US01
Filing Date: 08/02/2022
Claimed Priority Date: 09/22/2021 (JP 2021-153878)
Inventors: Kageyama et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 06/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 06/11/2026 in reply to the previous Office action mailed on 03/11/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-5 and 7-21, with claims 9-12 and 15-20 remaining withdrawn from consideration.
Claim Rejections
Initially, and with respect to claim 21, note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe,
even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935).
Note that the applicants have the burden of proof in such cases, as the above case law makes clear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yanagida (US 2021/0098374) in view of Kurata (WO 2020100947A1 - published 05/22/2020), Fuji (US 2021/0280551), Harada (US 2019/0287890), and Nishimura II (WO 2021065907 A1 – published 04/08/2021). All citations from Kurata are taken from the equivalent U.S. document US 2021/0407937.
All citations from Nishimura II are taken from the equivalent U.S. document US 2022/0352105.
Regarding claim 1, Yanagida (see, e.g., figs. 4-5) shows most aspects of the instant invention, including a semiconductor device comprising:
a resin layer 20a having a resin main surface 20e;
a mounting wiring layer 14 arranged on the resin main surface and having a mounting wiring main surface (top of 14) facing the same side as the resin main surface 20e and a mounting wiring back surface (bottom of 14) facing a side that is opposite to the side of the resin main surface 20e;
a bonding portion (Ni and Solder layer closest to 42 in 44 – see, e.g., par.0065/ll.6-9) which is provided on the mounting wiring main surface;
a semiconductor element 24 including an element wiring layer 132, which has an element wiring main surface facing the side that is opposite to the side of the resin main surface and an element electrode (Ni and Cu layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9) which is provided on the element wiring main surface, and which is mounted on and connected to the bonding portion; and
a sealing resin 20b which seals the mounting wiring layer and the semiconductor element;
wherein the bonding portion (Ni and Solder layer closest to 42 in 44 – see, e.g., par.0065/ll.6-9) includes:
a plating layer (Ni layer closest to 42 in 44 – see, e.g., par.0065/ll.6-9) (see, e.g., par.0080/ll.8-12) formed on the mounting wiring main surface (top of 14) of the mounting wiring layer 14 and a solder layer (solder layer in 44 – see, e.g., par.0065/ll.6-9) formed between the plating layer and the element electrode (Ni and Cu layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9) of the semiconductor element 24 (see, e.g., par.0065/ll.6-9);
wherein a side surface of the plating layer is a flat surface (see, e.g., figs. 4-5);
wherein a side surface of the solder layer is a flat surface (see, e.g., figs. 4-5);
wherein the element electrode (Ni and Cu layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9) includes:
a conductive layer (Cu layer in 44 – see, e.g., par.0065/ll.6-9) which is connected to the element wiring layer 132; and
a Ni layer (Ni layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9) which is connected to the solder layer (solder layer in 44 – see, e.g., par.0065/ll.6-9), wherein a side surface of the Ni layer is a flat surface (see, e.g., figs. 4-5);
wherein:
the element wiring layer 132 contains Cu (see, e.g., par.0163);
the mounting wiring layer 14 contains Cu (see, e.g., par.0167); and
the Ni layer (Ni layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9) contains Ni
Although Yanagida teaches that roughening a surface can improve the adhesion characteristics of the roughened surface (see, e.g., par.0070/ll.7), Yanagida fails to specify that the mounting wiring main surface (top of 14) and element wiring main surface 132 are rough surfaces having a larger surface roughness than the mounting wiring back surface (bottom of 14) and that a side surface of the conductive layer is a rough surface having a larger surface roughness than the mounting wiring back surface.
Kurata, in the same field of endeavor, teaches that surface roughening is feasible for a diverse range of conductive surfaces, including various wiring surfaces and side surfaces of conductive layers of element electrodes, and that such roughening raises the adhesive force of sealing resin directly contacting the exposed roughened surfaces, preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Fuji, also in the same field of endeavor, also teaches that roughening may be possible for a diverse range of conductive structures in contact with a sealing resin (see, e.g., Fuji: par.0208). Fuji teaches that such roughened areas contribute to an anchoring effect so that the sealing resin is more firmly bonded to the conductive surfaces, thereby increasing the bonding strength between the respective conductive structures and the sealing resin and mitigating rupturing or peeling of the conductive structures (see, e.g., Fuji: par.0208). Furthermore, Harada, in the same field of endeavor, particularly teaches that roughening surfaces of conductive structures exposed to contact a sealing resin (such as a mounting wiring main or side surface), such that the roughened surfaces have a larger surface roughness than a mounting wiring back surface, improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Accordingly, Kurata, Fuji, and particularly Harada teach that for elements exposed to contact a sealing resin (i.e., portions of Yanagida’s mounting wiring main/side surfaces, the element wiring main surface, and a side surface of the conductive layer), adhesion between such surfaces and a sealing resin may be improved by roughening such surfaces to have a larger surface roughness than a mounting wiring back surface (see, e.g., Harada: pars.0071/ll.5-12 and 0100), whereby such roughening contributes to an anchoring effect so that the sealing resin is more firmly bonded to such surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Yanagida’s mounting wiring back surface and Yanagida’s mounting wiring main/side surfaces, element wiring main surface, and a side surface of the conductive layer, as already taught by Yanagida to have portions exposed to contact Yanagida’s sealing resin, so as to improve the adhesion characteristics of Yanagida’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji.
Furthermore, Yanagida teaches the use of a Ni layer between Yanagida’s solder layer and Yanagida’s copper-containing conductive layer (see, e.g., par.0065/ll.6-9). Yanagida, however, fails to specify that such a Ni layer is a barrier layer. Nishimura II, in the same field of endeavor and in a similar device to Yanagida, teaches a device containing a similar Ni layer between a Cu-containing conductive layer and a solder layer (see, e.g., Nishimura II: par.0169 and fig. 5). Nishimura II teaches that the placement of such a Ni layer allows the Ni layer to act as a barrier layer inhibiting the undesirable formation of Kirkendall voids between the solder layer and the Cu-containing conductive layer (see, e.g., Nishimura II: pars.0154, 0169, 0202/ll.5-9, and 0258/ll.5-9).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Yanagida’s Ni layer constitute a barrier layer containing Ni, as taught by Nishimura II, so as to inhibit the undesirable formation of Kirkendall voids between Yanagida’s Cu-containing conductive layer and Yanagida’s solder layer.
Regarding claim 2, Yanagida (see, e.g., fig. 4) shows that the mounting wiring layer 14 has a mounting wiring side surface (side of 14) connected to the mounting wiring main surface (top of 14) and mounting wiring back surface (bottom of 14), wherein the mounting wiring side surface is a rough surface having a larger surface roughness than the mounting wiring back surface. See the comments stated above in paragraphs 7-12, with respect to claim 1, which are considered to be repeated here.
Regarding claim 3, Yanagida (see, e.g., fig. 5) shows that the mounting wiring main surface (top of 14) includes:
a flat first covered portion covered by the bonding portion (Ni and Solder layer closest to 42 in 44 – see, e.g., par.0065/ll.6-9); and
a first exposed portion which is a rough surface having a larger surface roughness than the mounting wiring back surface exposed from the bonding portion
See the comments stated above in paragraphs 7-12, with respect to claim 1, which are considered to be repeated here.
Regarding claim 4, see the comments stated above in paragraph 14, with respect to claim 3, which are considered to be repeated here.
Regarding claim 5, Yanagida (see, e.g., fig. 5) that the element wiring main surface includes:
a flat second covered portion covered by the element electrode (Ni and Cu layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9); and
a second exposed portion which is a rough surface having a larger surface roughness than the mounting wiring back surface exposed from the element electrode (Ni and Cu layer farthest from 42 in 44 – see, e.g., par.0065/ll.6-9)
See the comments stated above in paragraphs 7-12, with respect to claim 1, which are considered to be repeated here.
Regarding claim 7, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the mounting wiring main surface 211 is 0.3 µm or more.
Regarding claim 8, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the element wiring main surface 132 is 0.3 µm or more.
Regarding claim 13, Yanagida (see, e.g., figs. 4 and 9b) shows that the resin layer 20a has:
a resin back surface 20d2 facing the opposite side of the resin main surface 20e; and
a through-hole that penetrates the resin layer from the resin main surface to the resin back surface; and
wherein the semiconductor device further comprises:
a terminal portion 12 provided in the through-hole and connected to the mounting wiring layer 14
Regarding claim 14, Yanagida (see, e.g., fig. 4) shows that the terminal portion 12 has a back surface exposed from the resin back surface 20d2, wherein the semiconductor device further comprises an external conductive film 18 in contact with the back surface of the terminal portion.
Regarding claim 21, Harada (see, e.g., Harada: par.0071/ll.5-8) teaches that roughening to within a specific mathematical range is preferred for surfaces of conductive materials exposed to resin, wherein such roughening improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Furthermore, Kurata (see, e.g. Kurata: pars.0006, 0008, 0127-0128, 0088-0090, 0116-0118, and 0191) teaches that the roughnesses of multiple separate conductive surfaces contacting a sealing resin may be physically adjusted to a variety of roughness values in order to optimize bonding and peel-off resistance. Fuji further corroborates such findings, teaching that an average surface roughness within a specific mathematical range is preferred for surfaces contacting a sealing resin, and that such roughening contributes to a desired anchoring effect promoting bonding, increased adhesion, and decreased rupturing and peeling (see, e.g., Fuji: par.0077/ll.5-8 and 0208)..
It is well established that where the claimed range is close to or overlaps with a range disclosed in the prior art, a prima facie case of obviousness exists. See Titanium Metals Corp. v. Banner; see also In re Peterson. Additionally, where a general range is disclosed in the prior art, discovering an optimum value within that range through routine experimentation is ordinarily within the skill in the art. See In re Aller.
Here, Harada’s, Kurata’s, and Fuji’s express teaching that surface roughnesses may take on values within a specified range together with their disclosure that such surface roughnesses may vary, would have suggested to one of ordinary skill in the art that the roughnesses of surfaces exposed to a sealing resin, that is, a surface of an element wiring main surface and a surface of a mounting wiring main surface, could be adjusted to values within the claimed range (i.e., “equal roughness”) as a matter of routine optimization of a result-effective variable. Adjusting roughness to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, alongside Harada’s, Kurata’s and/or Fuji’s express teachings of improved adhesion, bonding, and peel-off/rupturing resistance, would have been well within the ordinary skill in the art. Such modification would have involved no more than routine experimentation to determine an appropriate degree or location of surface roughness to achieve the predictable result of improved adhesion. No evidence of criticality or unexpected results for the claimed roughness equivalence is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Additionally, Kurata (see, e.g., pars.0174 and 0215) teaches that the roughening of conductive surfaces contacting a sealing resin may be achieved through the use of a roughening solution, wherein Harada (see, e.g., par.0089) further teaches that the roughening of conductive surfaces contacting a sealing resin may be achieved through use of a roughening solution that interacts specifically with Cu. Nevertheless, and furthermore, the language, term, or phrase “wherein the rough surface of the element wiring main surface and the rough surface of the mounting wiring main surface are formed… by being simultaneously roughened by a same roughening solution, which reacts with Cu more than Ni”, is directed towards the process of making rough surfaces. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “wherein the rough surface of the element wiring main surface and the rough surface of the mounting wiring main surface are formed… by being simultaneously roughened by a same roughening solution, which reacts with Cu more than Ni” only requires a rough surface of the element wiring main surface and a rough surface of the mounting wiring main surface, which does not distinguish the invention from Yanagida/Kurata/Fuji/Harada/Nishimura II, who teaches the structure as claimed.
Accordingly, it is noted that Yanagida/Kurata/Fuji/Harada/Nishimura II shows all structural aspects of the semiconductor device according to the claimed invention, and that the method steps of forming the roughened surfaces through simultaneous roughening by a same roughening solution, which reacts with Cu more than Ni, do not affect the structure of the final device.
Claims 1-4, 7-8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura II (WO 2021065907 A1 – published 04/08/2021) in view of Kurata, Fuji, and Harada. All citations from Nishimura II are taken from the equivalent U.S. document US 2022/0352105.
Regarding claim 1, Nishimura II (see, e.g., figs. 4 and 11) shows most aspects of the instant invention, including a semiconductor device comprising:
a resin layer 10 (see, e.g., par.0157/ll.1-3) having a resin main surface 101;
a mounting wiring layer 21 arranged on the resin main surface and having a mounting wiring main surface 211 facing the same side as the resin main surface and a mounting wiring back surface 212 facing a side that is opposite to the side of the resin main surface;
a bonding portion 40/45 which is provided on the mounting wiring main surface;
a semiconductor element 50 including an element wiring layer 551 which has an element wiring main surface facing the side that is opposite to the side of the resin main surface and an element electrode 552/553 which is provided on the element wiring main surface and which is mounted on and connected to the bonding portion; and
a sealing resin 60 which seals the mounting wiring layer and the semiconductor element;
wherein:
the bonding portion 40/45 includes a plating layer 41 formed on the mounting wiring main surface 211 of the mounting wiring layer 21 and a solder layer 42/45 formed between the plating layer and the element electrode 552/553 of the semiconductor element 50;
a side surface of the plating layer is a flat surface;
a side surface of the solder layer is a flat surface;
the element electrode includes a conductive layer 552 which is connected to the element wiring layer 551 and a barrier layer 553 which is connected to the solder layer;
a side surface of the barrier layer is a flat surface;
the element wiring layer 551 contains Cu (see, e.g., par.0153/ll.8-10);
the mounting wiring layer contains Cu (see, e.g., par.0258/ll.1-4); and
the barrier layer contains Ni (see, e.g., par.0154/ll.4-6)
Although Nishimura II teaches that surfaces of Nishimura’s device, including the mounting wiring main surface, are rough surfaces (see, e.g., par.0259/ll.8-10), and that portions of Nishimura II’s mounting wiring main surface, element wiring main surface, and a side surface of the conductive layer directly contact Nishimura II’s sealing resin (see, e.g., figs. 4 and 11), Nishimura II fails to specify that the mounting wiring main surface and element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface and that a side surface of the conductive layer is a rough surface having a larger surface roughness than the mounting wiring back surface.
Kurata, in the same field of endeavor, teaches that surface roughening is feasible for a diverse range of conductive surfaces, including various wiring surfaces and side surfaces of conductive layers of element electrodes, and that such roughening raises the adhesive force of sealing resin directly contacting the exposed roughened surfaces, preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Fuji, also in the same field of endeavor, also teaches that roughening may be possible for a diverse range of conductive structures in contact with a sealing resin (see, e.g., Fuji: par.0208). Fuji teaches that such roughened areas contribute to an anchoring effect so that the sealing resin is more firmly bonded to the conductive surfaces, thereby increasing the bonding strength between the respective conductive structures and the sealing resin and mitigating rupturing or peeling of the conductive structures (see, e.g., Fuji: par.0208). Furthermore, Harada, in the same field of endeavor, particularly teaches that roughening surfaces of conductive structures exposed to contact a sealing resin (such as a mounting wiring main or side surface), such that the roughened surfaces have a larger surface roughness than a mounting wiring back surface, improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Accordingly, Kurata, Fuji, and particularly Harada teach that for elements exposed to contact a sealing resin (i.e., portions of Nishimura II’s mounting wiring main surface, element wiring main surface, and a side surface of the conductive layer), adhesion between such surfaces and a sealing resin may be improved by roughening such surfaces to have a larger surface roughness than a mounting wiring back surface (see, e.g., Harada: pars.0071/ll.5-12 and 0100), whereby such roughening contributes to an anchoring effect so that the sealing resin is more firmly bonded to such surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Nishimura II’s mounting wiring back surface and Nishimura II’s mounting wiring main surface, element wiring main surface, and a side surface of the conductive layer, as already taught by Nishimura II to have portions exposed to contact Nishimura II’s sealing resin, so as to improve the adhesion characteristics of Nishimura II’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji.
Regarding claim 2, Nishimura II (see, e.g., figs. 4 and 11) shows that the mounting wiring layer 21 has a mounting wiring side surface (side of 21) connected to the mounting wiring main surface 211 and the mounting wiring back surface 212. However, although Nishimura II shows that the mounting wiring side surface directly contacts Nishimura II’s sealing resin, Nishimura II fails to explicitly specify that the mounting wiring side surface is a rough surface having a larger surface roughness than the mounting wiring back surface.
Kurata, in the same field of endeavor, teaches that surface roughening is feasible for a diverse range of conductive surfaces, including various wiring surfaces, and that such roughening raises the adhesive force of sealing resin directly contacting the exposed roughened surfaces, preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Fuji, also in the same field of endeavor, also teaches that roughening may be possible for a diverse range of conductive structures in contact with a sealing resin (see, e.g., Fuji: par.0208). Fuji teaches that such roughened areas contribute to an anchoring effect so that the sealing resin is more firmly bonded to the conductive surfaces, thereby increasing the bonding strength between the respective conductive structures and the sealing resin and mitigating rupturing or peeling of the conductive structures (see, e.g., Fuji: par.0208). Furthermore, Harada, in the same field of endeavor, particularly teaches that roughening surfaces of conductive structures exposed to contact a sealing resin (such as a mounting wiring side surface), such that the roughened surfaces have a larger surface roughness than a mounting wiring back surface, improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Accordingly, Kurata, Fuji, and particularly Harada teach that for elements exposed to contact a sealing resin (i.e., portions of Nishimura II’s mounting wiring side surface), adhesion between such surfaces and a sealing resin may be improved by roughening such surfaces to have a larger surface roughness than a mounting wiring back surface (see, e.g., Harada: pars.0071/ll.5-12 and 0100), whereby such roughening contributes to an anchoring effect so that the sealing resin is more firmly bonded to such surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Nishimura II’s mounting wiring back surface and Nishimura II’s mounting wiring side surface, as already taught by Nishimura II to be exposed to contact Nishimura II’s sealing resin, so as to improve the adhesion characteristics of Nishimura II’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji. See also the comments stated above in paragraphs 27-30, with respect to claim 1, which are considered to be repeated here.
Regarding claim 3, Nishimura II (see, e.g., figs. 4 and 11) Regarding claim 3, Nishimura II (see, e.g., figs. 4 and 11) shows that the mounting wiring main surface 211 includes a flat first covered portion covered by the bonding portion 40/45 and a first exposed portion which is a rough surface having a larger surface roughness than the mounting wiring back surface exposed from the bonding portion. See the comments stated above in paragraphs 27-30, with respect to claim 1, which are considered to be repeated here.
Regarding claim 4, see the comments stated above in paragraph 34, with respect to claim 3, which are considered to be repeated here.
Regarding claim 7, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the mounting wiring main surface 211 is 0.3 µm or more.
Regarding claim 8, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the element wiring main surface 132 is 0.3 µm or more.
Regarding claim 13, Nishimura II (see, e.g., figs. 4 and 11) shows that the resin layer 10 has:
a resin back surface 102 facing the opposite side of the resin main surface 101; and
a through-hole 105 that penetrates the resin layer from the resin main surface to the resin back surface; and
wherein the semiconductor device further comprises:
a terminal portion 22 provided in the through-hole and connected to the mounting wiring layer 21
Regarding claim 14, Nishimura II (see, e.g., fig. 11) shows that the terminal portion 22 has a back surface 222 exposed from the resin back surface 102, wherein the semiconductor device further comprises an external conductive film 71 in contact with the back surface of the terminal portion (see, e.g., par.0272/ll.3).
Regarding claim 21, Harada (see, e.g., Harada: par.0071/ll.5-8) teaches that roughening to within a specific mathematical range is preferred for surfaces of conductive materials exposed to resin, wherein such roughening improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Furthermore, Kurata (see, e.g. Kurata: pars.0006, 0008, 0127-0128, 0088-0090, 0116-0118, and 0191) teaches that the roughnesses of multiple separate conductive surfaces contacting a sealing resin may be physically adjusted to a variety of roughness values in order to optimize bonding and peel-off resistance. Fuji further corroborates such findings, teaching that an average surface roughness within a specific mathematical range is preferred for surfaces contacting a sealing resin, and that such roughening contributes to a desired anchoring effect promoting bonding, increased adhesion, and decreased rupturing and peeling (see, e.g., Fuji: par.0077/ll.5-8 and 0208). Additionally, Kurata (see, e.g., pars.0174 and 0215) teaches that the roughening of conductive surfaces contacting a sealing resin may be achieved through the use of a roughening solution, wherein Harada (see, e.g., par.0089) further teaches that the roughening of conductive surfaces contacting a sealing resin may be achieved through use of a roughening solution that specifically interacts with Cu.
It is well established that where the claimed range is close to or overlaps with a range disclosed in the prior art, a prima facie case of obviousness exists. See Titanium Metals Corp. v. Banner; see also In re Peterson. Additionally, where a general range is disclosed in the prior art, discovering an optimum value within that range through routine experimentation is ordinarily within the skill in the art. See In re Aller.
Here, Harada’s, Kurata’s, and Fuji’s express teaching that surface roughnesses may take on values within a specified range together with their disclosure that such surface roughnesses may vary, would have suggested to one of ordinary skill in the art that the roughnesses of surfaces exposed to a sealing resin, that is, a surface of an element wiring main surface and a surface of a mounting wiring main surface, could be adjusted to values within the claimed range (i.e., “equal roughness”) as a matter of routine optimization of a result-effective variable. Adjusting roughness to achieve predictable results, such as improved scaling, reduced material usage, or modified electrical/mechanical performance, alongside Harada’s, Kurata’s and/or Fuji’s express teachings of improved adhesion, bonding, and peel-off/rupturing resistance, would have been well within the ordinary skill in the art. Such modification would have involved no more than routine experimentation to determine an appropriate degree or location of surface roughness to achieve the predictable result of improved adhesion. No evidence of criticality or unexpected results for the claimed roughness equivalence is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Additionally, Kurata (see, e.g., pars.0174 and 0215) teaches that the roughening of conductive surfaces contacting a sealing resin may be achieved through the use of a roughening solution, wherein Harada (see, e.g., par.0089) further teaches that the roughening of conductive surfaces contacting a sealing resin may be achieved through use of a roughening solution that interacts specifically with Cu. Nevertheless, and furthermore, the language, term, or phrase “wherein the rough surface of the element wiring main surface and the rough surface of the mounting wiring main surface are formed… by being simultaneously roughened by a same roughening solution, which reacts with Cu more than Ni”, is directed towards the process of making rough surfaces. It is well settled that “product by process” limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language “wherein the rough surface of the element wiring main surface and the rough surface of the mounting wiring main surface are formed… by being simultaneously roughened by a same roughening solution, which reacts with Cu more than Ni” only requires a rough surface of the element wiring main surface and a rough surface of the mounting wiring main surface, which does not distinguish the invention from Nishimura II/Kurata/Fuji/Harada, who teaches the structure as claimed.
Accordingly, it is noted that Nishimura II/Kurata/Fuji/Harada shows all structural aspects of the semiconductor device according to the claimed invention, and that the method steps of forming the roughened surfaces through simultaneous roughening by a same roughening solution, which reacts with Cu more than Ni, do not affect the structure of the final device.
Response to Arguments
With respect to the drawings, Applicant’s amendments to the drawings and the specification as filed on 10/31/2025 have overcome the objections to the drawings put forth in the previous Office action mailed on 08/08/2025. Accordingly, the objections to the drawings put forth in the previous Office action are hereby withdrawn.
With respect to the claims, Applicant argues:
In the outstanding Office Action, it is alleged that wiring layer 14 and second conductive part 132, as described by Yanagida, are each formed of Ti or TaN together with a Cu stack, as described in paragraphs [0063] and [0067] thereof. Applicant submits that, at [0063], Yanagida states that "The second conductive portion 132 is configured by a titanium (Ti) layer and a copper (Cu) layer which are stacked on each other. In the second conductive portion 132, the Cu layer is in contact with the first conductive portion 131," and therefore the outermost surface of second conductive portion 132 is the Ti layer. It is also alleged that seed layer 42 described by Yanagida is formed of Ti or TaN. Taken together, Applicant submits that Yanagida does not teach the material combination for the mounting wiring main surface, the element wiring main surface, and the barrier layer, as in amended Claim 1.
The Examiner responds:
Applicant argues that because Yanagida specifies that Yanagida’s element wiring layer may comprise a titanium layer over a copper layer that Yanagida does not teach the copper-containing element wiring layer required by amended claim 1. This is not found persuasive. The features upon which applicant relies (i.e., concerning “outermost” surfaces of element wiring layers) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Claim 1 at present only requires that “the element wiring layer contains Cu”. As admitted by Applicant and as demonstrated by Yanagida (see, e.g., par.0063), Yanagida’s element wiring layer contains Cu. Therefore, Yanagida’s element wiring layer adheres to amended claim 1.
Applicant’s arguments regarding the barrier layer in Yanagida are found moot in view of the new grounds of rejection that were necessitated by Applicant’s amendments to the claims, specifically, Applicant’s amendments to the materials of the barrier layer.
In the Response to Arguments on page 18 of the Office Action, it is alleged that internal electrode 2, as described by Harada, teaches the presently claimed mounting wiring main surface and that second conductive part 132, as also described by Harada, teaches the presently claimed element wiring main surface. Applicant submits that Harada describes the internal electrode 2 as being formed of Cu and the second conductive part 132 is formed of Ni, Pd, or Au, as described in paragraphs [0063], [0066], and [0069] and shown in FIG. 6 thereof. Such description fails to teach that the element wiring layer of the semiconductor element contains Cu, that the mounting wiring layer contains Cu, and that the barrier layer of the element electrode contains Ni, as in amended Claim 1. On page 7 of the Office Action, it is alleged that main surface wiring 21 as taught by Nishimura I at paragraphs [0054] - [0058] teaches the presently claimed mounting wiring main surface. Main surface wiring 21, as described by Nishimura I, is formed of Ni, and there is no further disclosure provided by Nishimura that would teach or suggest that the element wiring layer of the semiconductor element contains Cu, that the mounting wiring layer contains Cu, and that the barrier layer of the element electrode contains Ni, as in amended Claim 1. Neither Kurata nor Fuji compensate for the deficiencies of the references discussed above, relative to amended Claim 1, particularly since neither Kurata nor Fuji teaches any component that is even suggestive of the presently claimed mounting wiring main surface, element wiring main surface, and barrier layer, as in amended Claim 1. Accordingly, none of the references cited in rejections a) and b), either singularly or in combination, teaches or suggests that "the element wiring layer contains Cu and the mounting wiring layer contains Cu" and "the barrier layer contains Ni," as in amended Claim 1.
The Examiner responds:
These arguments are not persuasive because they are based on a mischaracterization of the rejection. The rejection does not rely on Nishimura I, Kurata, Fuji, Harada for the limitations directed to the materials of the mounting wiring layer, the element wiring layer, or the barrier layer. Yanagida, the primary reference, already teaches these features for the mounting wiring layer and the element wiring layer and Yanagida in view of Nishimura II already teaches these features for the barrier layer. Specifically, Yanagida and Yanagida/Nishimura II (see, e.g., Yanagida: pars.0065/ll.6-9, 0163, 0167) disclose an element wiring layer containing Cu, a mounting wiring layer containing Cu, and a barrier layer containing Ni (see paragraphs 11-12 above). Accordingly, the materials of any respective features in Nishimura I, Harada, Kurata, and Fuji have no bearing on the features of the instant rejection since they are already taught or suggested by Yanagida or Yanagida/Nishimura II alone.
Nishimura I is no longer relied upon. Furthermore, Harada, Kurata, and Fuji are relied upon solely to teach that roughening may be applied to a diverse range of conductive structures, and that such roughening increases the adhesive force between a contacting resin and the conductive structures, thereby increasing bonding strength and mitigating rupture or peeling of the conductive structures (see, e.g., Harada: pars.0071/ll.5-12 and 100; Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238; and Fuji: par.0208). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Yanagida’s recited sealing-resin-contacting conductive features as recited in the rejections above, as already taught by Yanagida to have portions exposed to contact Yanagida’s sealing resin, so as to improve the adhesion characteristics of Yanagida’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji. It would have been an obvious design choice to apply the known roughening technique taught by Harada to conductive surfaces contacting a sealing resin in Yanagida in order to improve adhesion and reliability of the overall device. This modification would merely involve applying a known surface treatment to a similar interface for the same predictable result of enhanced adhesion.
Accordingly, Applicant’s arguments do not overcome the prima facie case of obviousness, and the rejection under 35 U.S.C. § 103 is therefore maintained.
With respect to the claims, Applicant additionally argues:
On pages 11 - 12 of the Office Action, it is alleged that metal layer 551, as taught by Nishimura II, teaches the element wiring layer of Claim 1. Applicant disagrees. Metal layer 551, as described in paragraph [0153] of Nishimura II, does not and cannot be configured such that "surface facing the side is opposite to the side of the resin main surface," as in amended Claim 1. Further, although protection film 54 is described in paragraph [0152] as having a surface in contact with a sealing resin, protection film 54 is described as being made of polyimide resin and thus does not teach the material of the presently claimed element wiring main surface. Thus, Nishimura II does not compensate for the deficiencies of Yanagida, relative to amended Claim 1, because Nishimura II does not teach the material combination for the mounting wiring main surface, the element wiring main surface, and the barrier layer, as recited in amended Claim 1.
The Examiner responds:
Applicant argues that Nishimura II’s element wiring layer 551 does not and cannot be configured such as to include an element wiring main surface facing the side that is opposite to the side of the resin main surface. This is not found persuasive. Under the “Rejection Under 35 U.S.C. 112 rejection” section on page 8 of the “Applicant Arguments/Remarks Made in an Amendment” document filed on 06/11/2026, Applicant has showcased an orientation that Applicant believes to read upon an “element wiring main surface facing the side that is opposite to the side of the resin main surface”. In such a description, Applicant references the instant Application’s figure 3 and describes that a surface 541 of element wiring layer 54 faces a resin layer 10 in a direction in which the side opposite to a resin main surface 101 is directed. Nishimura II shows a remarkably identical disposition. See, for example, figures 4-5 of Nishimura II, in which a side of element wiring layer 551 (e.g., side of 551 closest to 10), that is, the element wiring main surface, is established in a nearly identical position to Applicant’s figure 3, wherein Nishimura II’s element wiring main surface further faces a resin layer 10 in a direction in which a side opposite to the resin layer’s resin main surface 101 is directed, akin to the instant application. Applicant cites Nishimura II’s paragraph 0153 as evidence that Nishimura II cannot have the element wiring main surface described in the claim. However, paragraph 0153 makes no mention of any alternative element wiring layer or resin layer disposition that teaches away from Nishimura II’s figures. It is unclear to the Examiner why such a disposition would be permissible to read on the elected claims of the instant application yet would be unacceptable for Nishimura II. Accordingly, as can be seen in Nishimura II’s drawings, Nishimura II teaches an element wiring layer having an element wiring main surface the side that is opposite to the side of the resin main surface as is claimed in the instant application.
Applicant’s arguments regarding Nishimura II’s alleged “protection layer 54” appear to be irrelevant to the current claims set, as alleged “protection layer 54” has never been referenced by the Examiner in either the previous or instant rejections.
Applicant’s amendments to the claims are sufficient to overcome the 35 U.S.C. 112 rejections put forth in the previous Office action mailed on 03/11/2026. Accordingly, the 35 U.S.C. 112 rejections put forth in the previous Office action are hereby withdrawn.
All other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
