Listed by the USPTO as HANUMASAGAR, SHAMITA S
Tech Center 2800 • Art Units: 2814
This examiner grants 77% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18091583 | TECHNOLOGIES FOR DIE RECYCLING FOR HIGH YIELD PACKAGING | Non-Final OA | Intel Corporation |
| 18084438 | LOW ALUMINUM CONCENTRATION ALUMINUM GALLIUM NITRIDE INTERLAYER FOR GROUP III-NITRIDE (III-N) DEVICES | Final Rejection | Intel Corporation |
| 17357895 | NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL WITH EPI PROTECTION | Final Rejection | Intel Corporation |
| 17353263 | INTEGRATED CIRCUIT STRUCTURES HAVING PLUGGED METAL GATES | Non-Final OA | Intel Corporation |
| 17353275 | INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE SELF-ALIGNED CONDUCTIVE PASS-THROUGH CONTACT | Final Rejection | Intel Corporation |
| 17346990 | INTEGRATED CIRCUIT STRUCTURES HAVING METAL GATES WITH REDUCED ASPECT RATIO CUTS | Non-Final OA | Intel Corporation |
| 17347015 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING BACKSIDE REMOVAL APPROACH | Non-Final OA | Intel Corporation |
| 18069224 | TEST PAD ON DEVICE LEAD FOR TEST CONTACTOR | Final Rejection | Texas Instruments Incorporated |
| 18216887 | DOUBLE-SIDED INTEGRATED CIRCUIT WITH STABILIZING CAGE | Non-Final OA | International Business Machines Corporation |
| 18308891 | SEMICONDUCTOR PACKAGE INCLUDING BUMP INTERCONNECTION STRUCTURE | Final Rejection | SK hynix Inc. |
| 18343290 | SEMICONDUCTOR DEVICE | Non-Final OA | ROHM CO., LTD. |
| 17816826 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Final Rejection | ROHM CO., LTD. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy76.7% of resolved applications examined by Shamita S Hanumasagar were allowed (30 resolved cases), compared with 74.2% across Art Unit 2814 over the last five years.
This examiner's interview lift is -6.8 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Shamita S Hanumasagar took 1,240 days on average from filing to allowance.
Shamita S Hanumasagar examines applications in Art Unit 2814 in Tech Center 2800 (Semiconductors, Circuits & Optics).
