Attorney’s Docket Number: 20353.0266US01
Filing Date: 08/02/2022
Claimed Priority Date: 09/22/2021 (JP 2021-153878)
Inventors: Kageyama et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 10/31/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection mailed on 08/08/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 10/31/2025 has been entered.
Amendment Status
The RCE submission filed on 10/31/2025 as an amendment in reply to the Office action mailed on 08/08/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-5 and 7-20, with claims 9-12 and 15-20 remaining withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-5, 7-8, and 13-14 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites the limitation “facing the side of the resin layer”. No distinct singular “side” of the resin layer has been previously sufficiently recited in the claim. As such, there is insufficient antecedent basis for this limitation in the claim. Furthermore, in the case that “the side” of the resin layer is intended to be a previously recited element in the claim (e.g., a “side” corresponding to the resin main surface or a “side” that is opposite to the side of the resin main surface), this limitation in the claim is indefinite as it is unclear which of the various previously recited “side”-comprising surfaces the specific limitation “the side of the resin layer” is intended to refer.
Claims 2-5, 7-8, and 13-14 depend from claim 1 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yanagida (US 2021/0098374) in view of Kurata (WO 2020100947A1 - published 05/22/2020), Fuji (US 2021/0280551), Harada (US 2019/0287890), and Nishimura I (US 2020/0411425). All citations from Kurata are taken from the equivalent U.S. document US 2021/0407937.
Regarding claim 1, Yanagida (see, e.g., figs. 4-5) shows most aspects of the instant invention, including a semiconductor device comprising:
a resin layer 20a having a resin main surface 20e;
a mounting wiring layer 14 arranged on the resin main surface and having a mounting wiring main surface (top of 14) facing the same side as the resin main surface 20e and a mounting wiring back surface (bottom of 14) facing a side 20d2 that is opposite to the side of the resin main surface 20e;
a semiconductor element 24 including an element wiring layer 132, which has an element wiring main surface facing a side of the resin layer 20a, and an element electrode 44, 42 which is provided on the element wiring main surface; and
a sealing resin 20b which seals the mounting wiring layer and the semiconductor element; and
wherein the element electrode includes:
a conductive layer 44 which is connected to the element wiring layer 132; and
a barrier layer 42 which is connected to the conductive layer, wherein a side surface of the barrier layer 42 is a flat surface
Although Yanagida teaches that roughening a surface can improve the adhesion characteristics of the roughened surface (see, e.g., par.0070/ll.7), Yanagida fails to specify that the mounting wiring main surface (top of 14) and element wiring main surface 132 are rough surfaces having a larger surface roughness than the mounting wiring back surface (bottom of 14) and that a side surface of the conductive layer is a rough surface having a larger surface roughness than the mounting wiring back surface. Furthermore, although Yanagida teaches that the mounting wiring layer 20, semiconductor element 24, and element electrode 44, 42 are connected, Yanagida fails to specify that this is done through a bonding portion which is provided on the mounting wiring main surface, wherein the element electrode is mounted on and connected to the bonding portion, and that such a bonding portion further includes (1) a plating layer formed on the mounting wiring main surface of the mounting wiring layer and (2) a solder layer formed between the plating layer and the element electrode of the semiconductor element, wherein a side surface of each of the plating and solder layers is a flat surface, and wherein the barrier layer is connected to the solder layer.
Kurata, in the same field of endeavor, teaches that surface roughening is feasible for a diverse range of conductive surfaces, including various wiring surfaces and side surfaces of conductive layers of element electrodes, and that such roughening raises the adhesive force of sealing resin directly contacting the exposed roughened surfaces, preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Fuji, also in the same field of endeavor, also teaches that roughening may be possible for a diverse range of conductive structures in contact with a sealing resin (see, e.g., Fuji: par.0208). Fuji teaches that such roughened areas contribute to an anchoring effect so that the sealing resin is more firmly bonded to the conductive surfaces, thereby increasing the bonding strength between the respective conductive structures and the sealing resin and mitigating rupturing or peeling of the conductive structures (see, e.g., Fuji: par.0208). Furthermore, Harada, in the same field of endeavor, particularly teaches that roughening surfaces of conductive structures exposed to contact a sealing resin (such as a mounting wiring main or side surface), such that the roughened surfaces have a larger surface roughness than a mounting wiring back surface, improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Accordingly, Kurata, Fuji, and particularly Harada teach that for elements exposed to contact a sealing resin (i.e., portions of Yanagida’s mounting wiring main/side surfaces, the element wiring main surface, and a side surface of the conductive layer), adhesion between such surfaces and a sealing resin may be improved by roughening such surfaces to have a larger surface roughness than a mounting wiring back surface (see, e.g., Harada: pars.0071/ll.5-12 and 0100), whereby such roughening contributes to an anchoring effect so that the sealing resin is more firmly bonded to such surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures.
Furthermore, like Yanagida and in the same field of endeavor, Nishimura I teaches a semiconductor element 50 having an element electrode 55 comprising a barrier layer 58, wherein the semiconductor element is connected to a mounting wiring layer 21 having a mounting wiring main surface 211 arranged on a resin layer 10 (see, e.g., Nishimura I: figs. 1 and 3). Nishimura I teaches uses a bonding portion 40 to provide this connection, wherein this bonding portion is provided on Nishimura I’s mounting wiring main surface such that the element electrode is mounted on and connected to the bonding portion and the bonding portion is further connected to Nishimura I’s semiconductor element 50. Nishimura I further shows that the bonding portion includes a plating layer 41 formed on the mounting wiring main surface of the mounting wiring layer and a solder layer 44 formed between the plating layer and the barrier layer 58 / element electrode 55 of Nishimura I’s semiconductor element 50, wherein a side surface of the plating layer is a flat surface and a side surface of the solder layer is a flat surface, and wherein the barrier layer is connected to the solder layer. Nishimura I teaches that such a bonding portion can both electrically and physically connect a mounting wiring layer to a semiconductor element and an element electrode, and can further assist in mounting a semiconductor element on a resin layer (see, e.g., Nishimura I: fig. 1 and pars.0061/ll.1-5 and 0070/ll.14-17).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Yanagida’s mounting wiring back surface and Yanagida’s mounting wiring main/side surfaces, element wiring main surface, and a side surface of the conductive layer, as already taught by Yanagida to have portions exposed to contact Yanagida’s sealing resin, so as to improve the adhesion characteristics of Yanagida’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the bonding portion of Nishimura I, shown such that the bonding portion is provided on a mounting wiring main surface and the element electrode is mounted on and connected to the bonding portion, and that the bonding portion includes (1) a plating layer formed on the mounting wiring main surface of the mounting wiring layer and (2) a solder layer formed between the plating layer and an element electrode of the semiconductor element, wherein a side surface of the plating layer is a flat surface and a side surface of the solder layer is a flat surface and wherein a barrier layer of the element electrode is connected to a solder layer of the bonding portion, as taught by Nishimura I, in the device of Yanagida, so as to facilitate an electrical and physical connection between Yanagida’s mounting wiring layer and semiconductor element and element electrode, and to beneficially assist in mounting Yanagida’s semiconductor element on Yanagida’s resin layer.
With regards to other language recited in claim 1, see the comments stated above in paragraph 6.
Regarding claim 2, Yanagida (see, e.g., fig. 4) shows that the mounting wiring layer 14 has a mounting wiring side surface (side of 14) connected to the mounting wiring main surface (top of 14) and mounting wiring back surface (bottom of 14), wherein the mounting wiring side surface is a rough surface having a larger surface roughness than the mounting wiring back surface. See the comments stated above in paragraphs 9-15, with respect to claim 1, which are considered to be repeated here.
Regarding claim 3, Nishimura I (see, e.g., figs. 1 and 3) shows that the mounting wiring main surface 211 includes a flat first covered portion covered by the bonding portion 40 and a first exposed portion exposed from the bonding portion. Yanagida (see, e.g., fig. 5) further shows that the mounting wiring main surface (top of 14) includes:
a covered flat first covered portion covered by the bonding portion (see the comments stated above in paragraphs 9-15, which are considered to be repeated here); and
a first exposed portion which is a rough surface having a larger surface roughness than the mounting wiring back surface exposed from the bonding portion
See the comments stated above in paragraphs 9-15, with respect to claim 1, which are considered to be repeated here.
Regarding claim 4, see the comments stated above in paragraph 17, with respect to claim 3, which are considered to be repeated here.
Regarding claim 5, Yanagida (see, e.g., fig. 5) that the element wiring main surface includes:
a flat second covered portion covered by the element electrode 44, 42; and
a second exposed portion which is a rough surface having a larger surface roughness than the mounting wiring back surface exposed from the element electrode 44, 42
See the comments stated above in paragraphs 9-15, with respect to claim 1, which are considered to be repeated here.
Regarding claim 7, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the mounting wiring main surface 211 is 0.3 µm or more.
Regarding claim 8, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the element wiring main surface 132 is 0.3 µm or more.
Regarding claim 13, Yanagida (see, e.g., figs. 4 and 9b) shows that the resin layer 20a has:
a resin back surface 20d2 facing the opposite side of the resin main surface 20e; and
a through-hole that penetrates the resin layer from the resin main surface to the resin back surface; and
wherein the semiconductor device further comprises:
a terminal portion 12 provided in the through-hole and connected to the mounting wiring layer 14
Regarding claim 14, Yanagida (see, e.g., fig. 4) shows that the terminal portion 12 has a back surface exposed from the resin back surface 20d2, wherein the semiconductor device further comprises an external conductive film 18 in contact with the back surface of the terminal portion.
Claims 1-4, 7-8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura II (WO 2021065907 A1 – published 04/08/2021) in view of Kurata, Fuji, and Harada. All citations from Nishimura II are taken from the equivalent U.S. document US 2022/0352105.
Regarding claim 1, Nishimura II (see, e.g., figs. 4 and 11) shows most aspects of the instant invention, including a semiconductor device comprising:
a resin layer 10 (see, e.g., par.0157/ll.1-3) having a resin main surface 101;
a mounting wiring layer 21 arranged on the resin main surface and having a mounting wiring main surface 211 facing the same side as the resin main surface and a mounting wiring back surface 212 facing a side that is opposite to the side of the resin main surface;
a bonding portion 40/45 which is provided on the mounting wiring main surface;
a semiconductor element 50 including an element wiring layer 551 which has an element wiring main surface facing a side of the resin layer and an element electrode 552/553 which is provided on the element wiring main surface and which is mounted on and connected to the bonding portion; and
a sealing resin 60 which seals the mounting wiring layer and the semiconductor element;
wherein:
the bonding portion 40/45 includes a plating layer 41 formed on the mounting wiring main surface 211 of the mounting wiring layer 21 and a solder layer 42/45 formed between the plating layer and the element electrode 552/553 of the semiconductor element 50;
a side surface of the plating layer is a flat surface;
a side surface of the solder layer is a flat surface;
the element electrode includes a conductive layer 552 which is connected to the element wiring layer 551 and a barrier layer 553 which is connected to the solder layer; and
a side surface of the barrier layer is a flat surface
Although Nishimura II teaches that surfaces of Nishimura’s device, including the mounting wiring main surface, are rough surfaces (see, e.g., par.0259/ll.8-10), and that portions of Nishimura II’s mounting wiring main surface, element wiring main surface, and a side surface of the conductive layer directly contact Nishimura II’s sealing resin (see, e.g., figs. 4 and 11), Nishimura II fails to specify that the mounting wiring main surface and element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface and that a side surface of the conductive layer is a rough surface having a larger surface roughness than the mounting wiring back surface.
Kurata, in the same field of endeavor, teaches that surface roughening is feasible for a diverse range of conductive surfaces, including various wiring surfaces and side surfaces of conductive layers of element electrodes, and that such roughening raises the adhesive force of sealing resin directly contacting the exposed roughened surfaces, preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Fuji, also in the same field of endeavor, also teaches that roughening may be possible for a diverse range of conductive structures in contact with a sealing resin (see, e.g., Fuji: par.0208). Fuji teaches that such roughened areas contribute to an anchoring effect so that the sealing resin is more firmly bonded to the conductive surfaces, thereby increasing the bonding strength between the respective conductive structures and the sealing resin and mitigating rupturing or peeling of the conductive structures (see, e.g., Fuji: par.0208). Furthermore, Harada, in the same field of endeavor, particularly teaches that roughening surfaces of conductive structures exposed to contact a sealing resin (such as a mounting wiring main or side surface), such that the roughened surfaces have a larger surface roughness than a mounting wiring back surface, improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Accordingly, Kurata, Fuji, and particularly Harada teach that for elements exposed to contact a sealing resin (i.e., portions of Nishimura II’s mounting wiring main surface, element wiring main surface, and a side surface of the conductive layer), adhesion between such surfaces and a sealing resin may be improved by roughening such surfaces to have a larger surface roughness than a mounting wiring back surface (see, e.g., Harada: pars.0071/ll.5-12 and 0100), whereby such roughening contributes to an anchoring effect so that the sealing resin is more firmly bonded to such surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Nishimura II’s mounting wiring back surface and Nishimura II’s mounting wiring main surface, element wiring main surface, and a side surface of the conductive layer, as already taught by Nishimura II to have portions exposed to contact Nishimura II’s sealing resin, so as to improve the adhesion characteristics of Nishimura II’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji.
With regards to other language recited in claim 1, see the comments stated above in paragraph 6.
Regarding claim 2, Nishimura II (see, e.g., figs. 4 and 11) shows that the mounting wiring layer 21 has a mounting wiring side surface (side of 21) connected to the mounting wiring main surface 211 and the mounting wiring back surface 212. However, although Nishimura II shows that the mounting wiring side surface directly contacts Nishimura II’s sealing resin, Nishimura II fails to explicitly specify that the mounting wiring side surface is a rough surface having a larger surface roughness than the mounting wiring back surface.
Kurata, in the same field of endeavor, teaches that surface roughening is feasible for a diverse range of conductive surfaces, including various wiring surfaces, and that such roughening raises the adhesive force of sealing resin directly contacting the exposed roughened surfaces, preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Fuji, also in the same field of endeavor, also teaches that roughening may be possible for a diverse range of conductive structures in contact with a sealing resin (see, e.g., Fuji: par.0208). Fuji teaches that such roughened areas contribute to an anchoring effect so that the sealing resin is more firmly bonded to the conductive surfaces, thereby increasing the bonding strength between the respective conductive structures and the sealing resin and mitigating rupturing or peeling of the conductive structures (see, e.g., Fuji: par.0208). Furthermore, Harada, in the same field of endeavor, particularly teaches that roughening surfaces of conductive structures exposed to contact a sealing resin (such as a mounting wiring side surface), such that the roughened surfaces have a larger surface roughness than a mounting wiring back surface, improves the adhesion between the (roughened) surfaces and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). Accordingly, Kurata, Fuji, and particularly Harada teach that for elements exposed to contact a sealing resin (i.e., portions of Nishimura II’s mounting wiring side surface), adhesion between such surfaces and a sealing resin may be improved by roughening such surfaces to have a larger surface roughness than a mounting wiring back surface (see, e.g., Harada: pars.0071/ll.5-12 and 0100), whereby such roughening contributes to an anchoring effect so that the sealing resin is more firmly bonded to such surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the roughnesses taught by Harada, supported by Kurata and Fuji, for Nishimura II’s mounting wiring back surface and Nishimura II’s mounting wiring side surface, as already taught by Nishimura II to be exposed to contact Nishimura II’s sealing resin, so as to improve the adhesion characteristics of Nishimura II’s device, such as by contributing to an anchoring effect so that the sealing resin is more firmly bonded to such conductive structure surfaces, thereby increasing the bonding strength between the respective structures and the sealing resin and ensuring mitigation of rupturing or peeling of the conductive structures, as taught by Fuji. See also the comments stated above in paragraphs 25-29, with respect to claim 1, which are considered to be repeated here.
Regarding claim 3, Nishimura II (see, e.g., figs. 4 and 11) Regarding claim 3, Nishimura II (see, e.g., figs. 4 and 11) shows that the mounting wiring main surface 211 includes a flat first covered portion covered by the bonding portion 40/45 and a first exposed portion which is a rough surface having a larger surface roughness than the mounting wiring back surface exposed from the bonding portion. See the comments stated above in paragraphs 25-29, with respect to claim 1, which are considered to be repeated here.
Regarding claim 4, see the comments stated above in paragraph 33, with respect to claim 3, which are considered to be repeated here.
Regarding claim 7, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the mounting wiring main surface 211 is 0.3 µm or more.
Regarding claim 8, Harada (see, e.g., par.0071/ll.5-8) shows that a surface roughness of the element wiring main surface 132 is 0.3 µm or more.
Regarding claim 13, Nishimura II (see, e.g., figs. 4 and 11) shows that the resin layer 10 has:
a resin back surface 102 facing the opposite side of the resin main surface 101; and
a through-hole 105 that penetrates the resin layer from the resin main surface to the resin back surface; and
wherein the semiconductor device further comprises:
a terminal portion 22 provided in the through-hole and connected to the mounting wiring layer 21
Regarding claim 14, Nishimura II (see, e.g., fig. 11) shows that the terminal portion 22 has a back surface 222 exposed from the resin back surface 102, wherein the semiconductor device further comprises an external conductive film 71 in contact with the back surface of the terminal portion (see, e.g., par.0272/ll.3).
Response to Arguments
With respect to the drawings, Applicant’s amendments to the drawings and the specification as filed on 10/31/2025 have overcome the objections to the drawings put forth in the previous Office action mailed on 08/08/2025. Accordingly, the objections to the drawings put forth in the previous Office action are hereby withdrawn.
With respect to the claims, Applicant argues:
Harada only teaches roughening internal electrode 2 in contact with a sealing resin and does not teach or suggest roughening the second conductive portion 132 or conductive bonding material 44 described by Yanagida. Therefore, only by hindsight would any other element described by Yanagida be roughened. Accordingly, the Examiner’s proposed combination relies on improper hindsight and fails to teach the claimed configurations recited in claim 1 requiring that “the element wiring main surface of the element wiring layer is a rough surface having a greater surface roughness than the mounting wiring back surface” and “the side surface is a rough surface having a larger surface roughness than the mounting wiring back surface”.
Applicant argues that Harada only teaches roughening element 2 and therefore provides no teaching or suggestion that the element wiring layer 132 or a side surface of the conductive layer 44 of Yanagida would be roughened such that “the element wiring main surface of the element wiring layer is a rough surface having a greater surface roughness than the mounting wiring back surface” and “the side surface is a rough surface having a larger surface roughness than the mounting wiring back surface”. This is not found persuasive. The fact that Harada illustrates roughening in the context of a particular structure does not negate the broader teaching that surface roughening at conductor-sealing resin interfaces improves adhesion. It is well established that disclosure of a preferred embedment does not limit the scope of technical teaching where the reference conveys a general principle applicable to similar structures. In fact, Harada itself explicitly states that “the semiconductor device according to the present disclosure and the method for manufacturing the semiconductor device are not limited to those described in the above embodiments. Various design changes can be made to the specific structures of the elements of the semiconductor device according to the present disclosure, and to the details of the steps of the method for manufacturing the semiconductor device” (see, e.g., Harada: par.0146). Similarly, Yanagida itself also explicitly states that “the embodiments described… are presented to illustrate apparatuses or methods for embodying the technical concept of the present disclosure and are not intended to specify the materials, features, structures, arrangements, and the like of the components. The embodiments may be variously modified without departing from the scope of the accompanying claims” and “while certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Further, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures” (see, e.g., Yanagida: pars.0028 and 0114). Accordingly, the rationale is consistent with the principle that where the prior art recognizes a problem and provides a solution, it would have been within the level of ordinary skill in the art to employ that solution in similar contexts absent evidence that such application would be technically infeasible or yield unpredictable results, to which Applicant has provided no evidence.
Harada explicitly teaches that roughening a conductive surface in contact with a sealing resin such that the roughened surfaces are rough surfaces with larger surface roughness than a mounting wiring back surface enhances adhesion between the (roughened) surface and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100). The benefit described by Harada is not limited to the specific structure of element 2, but rather reflects a general adhesion-improvement technique applicable to surfaces that interface with sealing resin. A person of ordinary skill in the art would have recognized that the same adhesion improvement would be achieved by roughening other conductive surfaces that contact a sealing resin within a device structure, including the exposed surfaces of the element wiring main surface and conductive layer side surface described by Yanagida. This understanding and general teaching are further corroborated by Kurata and Fuji, which likewise disclose that the use of surface roughening to improve adhesion between conductive structures and sealing resin in known in the art. Kurata teaches that the roughening may be applied to a diverse range of conductive structures, including wiring surfaces and side surface of conductive layers of element electrodes, and that such roughening increases the adhesive force between the resin and the conductive structures, thereby preventing peel-off of the resin (see, e.g., Kurata: pars.0006, 0008, 0191, 0222, 0235, 0238). Similarly, Fuji teaches that roughening conductive structures in contact with sealing resin produces an anchoring effect, whereby the sealing resin bonds more firmly to the roughened conductive structures, thereby increasing bonding strength and mitigating rupture or peeling of the conductive structures (see, e.g., Fuji: par.0208).
These teachings demonstrate that improving adhesion between conductive structures and sealing resin by roughening exposed conductive structures was a known and widely applied technique in the art, and a person of ordinary skill in the art would have understood that applying the same adhesion-enhancing technique could be applied to other conductive structures within Yanagida’s device that contact sealing resin, including the element wiring layer / element wiring main surface and a side surface of the conductive layer. Therefore, even if Harada might not explicitly identify the element wiring layer / element wiring layer main surface and a side surface of the conductive layer as being roughened, it would have been an obvious design choice to apply the known roughening technique taught by Harada to conductive surfaces contacting a sealing resin in Yanagida (i.e., the element wiring main surface and a side surface of the conductive layer) in order to improve adhesion and reliability of the overall device. This modification would merely involve applying a known surface treatment to a similar interface for the same predictable result of enhanced adhesion.
Moreover, by explicitly teaching that roughening a surface in contact with sealing resin such that the roughened surfaces are rough surfaces with larger surface roughness than a mounting wiring back surface enhances adhesion between the surface and the sealing resin (see, e.g., Harada: pars.0071/ll.5-12 and 0100), Harada identifies surface roughness as a parameter that affects adhesion performance at the interface between conductive structures and sealing resin. In other words, surface roughness is a result-effective variable influencing bonding strength with sealing resin.
When the prior art recognizes that a variable affects a desired result, it would have been routine for a person of ordinary skill in the art to optimize that variable to achieve improved performance. Thus, a person of ordinary skill in the art would therefore have been motivated to adjust the surface roughness of conductive structures that interface with sealing resin, such as the element wiring layer / element wiring main surface and a side surface of the conductive layer. Such modification would have involved no more than routine experimentation to determine an appropriate degree or location of surface roughness to achieve the predictable result of improved adhesion. Accordingly, even if Harada does not explicitly disclose roughening the specific conductive structures identified by Applicant, the recognition that surface roughness improves adhesion with sealing resin would have rendered it obvious for a person of ordinary skill in the art to optimize the roughness of other conductive structures with the same resin interface in the device of Yanagida. Subsequently, Yanagida in view of the described teachings teaches the structures as claimed.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814