DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/07/2026 has been entered. Claims 1-20 remain pending in the application.
Drawings
Replacement drawings for Fig.2 and 6 were received on 08/07/2026. These drawings are acceptable and overcome the objections made in the Non-final office action filed on 05/07/2026.
Specification
Replacement specification was received on 08/07/2026 and overcomes the objections made in the Non-final office action filed on 05/07/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/01/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 11 recites the limitation” “wherein at least the first plated through-hole comprises a void within the at least first plated through-hole that is filled with the substantially uniform dielectric material.”. In the Applicant Arguments/Remarks made in 08/07/2026, the applicant states, on page 10, that this limitation is supported by at least paragraphs [0008], [0023] and [0026] of the originally filed specification.
Paragraph [0023] of the originally filed specification (corresponding to paragraph [0051] of the corrected specification filed on 08/07/2026) states: “Thus, between the original layer of dielectric material 404 and the second layer of dielectric material 404 laminated at workflow 702, the overall layers filling the voids between the plated through holes”. Therefore, there is no mention of the dielectric material filling the voids within any plated through holes.
When referring to the deficiencies of the methodology of Figs 1-2, paragraph [0008] of the originally filed specification (corresponding to paragraph [0036] of the corrected specification filed on 08/07/2026) states: “The relatively large pitch also results in the plated through holes being so large that they must include voids within their center”. This deficiency is claimed to be eliminated by the methodology proposed by the current application in Fig.3-7, as stated in paragraph [0026] of the originally filed specification (corresponding to paragraph [0054] of the corrected specification filed on 08/07/2026): “the solution corresponding to workflow step 706 can eliminate the voids within the plated through holes, which were previously discussed in the context of Fig.1-2”. Thus, the current application claims that the voids are no longer present if the methodology proposed and claimed in claim 11 is applied. Furthermore, there is no mention that the voids within the plated through holes, and in particular the first plated through hole which is located below the component, are filled with dielectric material. Therefore, the newly added limitation of claim 11 constitutes new matter and there lacks a reasonable conveyance of possession of the subject matter claimed in claim 1.
For the purpose of examination and given paragraph [0023] of the originally filed specification (corresponding to paragraph [0051] of the corrected specification filed on 08/07/2026), the above limitation of claim 11 will be interpreted as: wherein voids between the second and third pluralities of plated through holes are filled with substantially uniform dielectric material.
Claims 12-19 are also rejected as dependent on claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 12, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Das et al., (United States Patent Application Publication Number, US 2017/0162550 A1), hereinafter referenced as Das, in view of Lee et al., (United States Patent Number, US 10,881,004 B1) hereinafter referenced as Lee.
Regarding claim 11, Das teaches a semiconductor substrate comprising: a first layer having (Fig.1, element #110) a first plated through-hole (Fig.1, plated through-hole located below the component element #170, on its right side, paragraph [0051], rows 13-21) and a first plurality of plated through-holes offset from the first plated through-hole (Fig.1, the leftmost and right most plated through-holes of layer #110); a component on the first layer over the first plated through-hole (Fig.1, element #170), wherein a first surface of the component is electrically connected to the first plated through-hole (Fig.1, bottom surface of element #170 is electrically connected to the plated through-hole located below the component, on its right side); a first dielectric layer on the first layer that encapsulates the component (Fig.1, element #120, paragraph [0067], rows 5-9) and comprises a second plurality of plated through-holes aligned with and directly connected to the first plurality of plated through-holes (Fig.1, the left-most and right-most plated through-holes of element #120 are aligned and directly connected to the plated through holes of first layer, element #110); and a second dielectric layer on the first dielectric layer (Fig.1, element #130) that comprises a second plated through-hole electrically connected to a second surface of the component (Fig.1, plated through-hole located above component element #170, on its right side, see also Fig.4, element #170 can have both top and bottom electrical connections with top and bottom plated through-holes), and a third plurality of plated through-holes aligned with and directly connected to the second plurality of plated through holes (Fig.1, the left-most and right-most plated through-holes of element #130 are aligned and directly connected to the plated through holes of first dielectric layer, element #120); wherein the component, a top surface of the first plated through-hole, and a bottom surface of the second plated through-hole are embedded within the first and second dielectric layers (see Fig.1, note that the pads are considered as being part of the through-holes).
Das does not teach wherein the first and second dielectric layers are formed of a substantially uniform dielectric material. Lee teaches wherein the first and second dielectric layers are formed of a substantially uniform dielectric material (Fig.3, first dielectric layer, element #111A, column 4, row 35, and second dielectric layer, element #111B, column 4, rows 43-44, may be made of pre-preg, column 7, rows 14-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose wherein the first and second dielectric layers are formed of a substantially uniform dielectric material. Making the layers from the same uniform material simplifies the design and allows the use of the same process for forming the layers.
Das further teaches the second plurality of plated through-holes extends through the first dielectric layer to extend the first plurality of plated through-holes through the first dielectric layer and the third plurality of plated through-holes extends through the second dielectric layer to extend the second plurality of plated through-holes forming a plurality of plated through-hole structures (Fig.1, the leftmost and rightmost plated through-holes of layers #110, #120 and #130 form through-hole structures), and a thickness of the first dielectric layer is less than a pitch of a plated through-hole pattern of the plurality of plated through-hole structures (Fig.1, the pitch between the through-hole structures is larger than the pitch between elements #181, #182, #183 and #184, which can be 150um, when the first dielectric layer thickness is 150um, paragraph [0093], rows 9-18), wherein voids between the second and third pluralities of plated through holes are filled with dielectric (Fig.1, elements #120 and #130 fill the space between the plated through holes and the component). Since Lee teaches the dielectric layers are formed of the same materials. The combination of Das and Lee teaches wherein voids between the second and third pluralities of plated through holes are filled with substantially uniform dielectric material.
Regarding claim 12, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. Das does not teach the semiconductor substrate of claim 11, wherein the dielectric material is pre-preg. Lee teaches the semiconductor substrate of claim 11, wherein the dielectric material is pre-preg (Fig.3, first dielectric layer, element #111A, column 4, row 35, and second dielectric layer, element #111B, column 4, rows 43-44, may be made of pre-preg, column 7, rows 14-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose wherein the dielectric material is pre-preg. Pre-preg is a common material used in electronics, which is easily shaped into desired shapes and ensures strength, durability and dimensional stability of the layers made of it.
Regarding claim 15, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. Das further teaches the semiconductor substrate of claim 11, wherein thickness of the first dielectric layer is approximately 50-100 microns (paragraph [0072], rows 1-6).
Regarding claim 16, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. The limitation “the first surface of the component of the semiconductor substrate is positioned prior to covering the second surface of the component with the second dielectric layer such that a cavity drill is not used to form a space in which the component is disposed” is being treated as a product by process limitation and as such only the structure is required to meet the limitation (MPEP 2113).
Regarding claim 17, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. Das teaches the semiconductor substrate of claim 11, further comprising contacts formed of a conductive material at the second surface of the component of the semiconductor substrate (Fig.3, elements #172, #304, and #305).
Regarding claim 18, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. Das teaches the semiconductor substrate of claim 11, wherein: the semiconductor substrate is formed of at least three layers of dielectric material (Fig.1, elements #110, #120 and #130), and the plated through-hole structure extends through the at least three layers using an aligned plated through-hole in each of the at least three layers (Fig.1, the rightmost and leftmost plated through-hole structures extend through the three layers and the plated through holes in each of the layers are aligned).
Das does not teach wherein: the at least three layers are made of the uniform dielectric material. Lee teaches the at least three layers are made of the uniform dielectric material (Fig.3, element #141A, #111A and #11B are formed of pre-preg, column 10, row 37 and column 7, row 21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose the at least three layers are made of the uniform dielectric material. Making the substrate layers from the same uniform material simplifies the design and allows the use of the same process for forming the layers.
Regarding claim 19, the combination of Das and Lee teaches the semiconductor substrate of claims 11 and 18 as set forth in the obviousness rejection. Das does not teach the semiconductor substrate of claim 18, wherein the at least three layers of the dielectric material are formed of pre-preg. Lee teaches the semiconductor substrate of claim 18, wherein the at least three layers of the dielectric material are formed of pre-preg (Fig.3, element #141A, #111A and #11B are formed of pre-preg, column 10, row 37 and column 7, row 21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lee and disclose wherein the at least three layers of the dielectric material are formed of pre-preg. Pre-preg is a common material used in electronics, which is easily shaped into desired shapes and ensures strength, durability and dimensional stability of the layers made of it.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Das, in view of Lee and in view of Kwon et al., (United States Patent Application Publication Number, US 2009/0145645 A1) hereinafter referenced as Kwon.
Regarding claim 13, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. Das teaches wherein the pitch is about five times the pitch between adjacent plated through holes of the first layer (Fig.3, the pitch is 5 times the pitch between elements #300). The combination of Das and Lee does not teach wherein the pitch is less than approximately 350 microns. Kwon teaches the pitch between adjacent plated through holes of the first layer is 60um (paragraph [0031], rows 1-4). Therefore, the combination of Das, Lee and Kwon teaches the pitch is 300um which is less than 350um. Therefore, the claimed pitch range overlaps the range disclosed by prior art and a prima facie case of obviousness exits (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teaching of Das and Kwon and disclose a pitch is less than approximately 350 microns. The pitch value may match the pitch value of pads corresponding to devices connected to the plated through-hole pattern. Therefore, these devices can be connected directly to the substrate comprising the plated through-hole pattern without the need of an interposer or redistribution layer.
Regarding claim 14, the combination of Das and Lee teaches the semiconductor substrate of claim 11 as set forth in the obviousness rejection. Das teaches wherein the pitch is about five times the pitch between adjacent plated through holes of the first layer (Fig.3). The combination of Das and Lee does not teach wherein the pitch is less approximately 250 microns. Kwon teaches the pitch between adjacent plated through holes of the first layer is less than 60um (paragraph [0031], rows 1-6). Therefore, the combination of Das, Lee and Kwon teaches the pitch is less than 300um. Therefore, the claimed pitch range overlaps the range disclosed by prior art and a prima facie case of obviousness exits (MPEP 2144.05). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to combine the teaching of Das and Kwon and disclose a pitch is approximately 250 microns. The pitch value may match the pitch value of pads corresponding to devices connected to the plated through-hole pattern. Therefore, these devices can be connected directly to the substrate comprising the plated through-hole pattern without the need of an interposer or redistribution layer. The plated through-hole structures can be used to make direct connections with semiconductor devices and therefore, they need to have pitch values similar to the pads/connectors pitch values of these devices, in order simplify and produce reliable electrical connections.
Allowable Subject Matter
Claims 1 and 20 are allowed. Claims 2-10 are also allowed as being dependent of claim 1
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the cited prior art does not teach or fairly suggests, along with other claimed features: “a fourth plated through-hole that directly connects to the second plated through-hole.” Inui et al., (United states Patent Number, US 8,745,860 B2), teaches all the limitations of claim 1, except the fourth plated through hole does not directly connects to the second plated through hole (Fig.5C, fourth through hole, element #89b does not directly connect the second through hole, element #58b).
Regarding claim 20, the cited prior art does not teach or fairly suggests, along with other claimed features: “fourth plated through-hole that is aligned with and directly connects to the second plated through-hole.” Inui et al., (United states Patent Number, US 8,745,860 B2), teaches all the limitations of claim 1, except the fourth plated through hole does not directly connects to the second plated through hole (Fig.5C, fourth through hole, element #89b, does not directly connect second through hole, element #58b).
Response to Arguments
Applicant’s arguments filed on 08/07/2026 have been fully considered but they
are not persuasive. As noted in the above 112(a) rejection of claim 11, the arguments related to new matter.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00AM -5:00 PM EST.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
