DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment & Claims’ Status
The Amendment filed on 5/9/2025 has been entered. Claims 1-2, 4-5, 7-12, 14-15, 17-18, 20-24, 26-30, and 32-36 are currently pending, with Claims 14-15, 17-18, 20-24, 26-30, and 32-36 being examined due to Claims 1-2, 4-5, and 7-12 having been previously withdrawn without traverse. Claims 1, 7, 10, 14, 20, 22, 24, 26, and 28-29 have been amended. Claims 3, 6, 13, 16, 19, 25, and 31 have been cancelled. Claims 32-36 have been newly added. The 35 U.S.C. 112(b) rejection of Claim 24 has been withdrawn due to the amendment to Claim 24 addressing the issues mentioned in the previous Office Action (filed 2/20/2025).
Claim Objections
Claims 14-15, 17-18, 20-24, 34-36 are objected to because of the following informalities:
Re Claims 14 and 20, in lines 2-3 “a plurality of semiconductor die” should be “a plurality of semiconductor dies” for grammatical correctness.
Re Claim 18, “the semiconductor die” in line 3 should be “the semiconductor wafer” (a singular semiconductor die was not previously established) for proper antecedent basis.
Re Claim 22, “the second surface of the semiconductor die” in lines 2-3 and “the first surface of the semiconductor die” in lines 3-4 should be “the second surface of the semiconductor wafer” and “the second surface of the semiconductor wafer” (a singular semiconductor die was not previously established), respectively, for proper antecedent basis.
Re Claim 24, “the semiconductor die” in line 3 should be “the semiconductor wafer” (a singular semiconductor die was not previously established) for proper antecedent basis.
Re Claim 34, “a first surface of the semiconductor die” in lines 2-3 should be “the first surface of the semiconductor ” (a singular semiconductor die was not previously established), “a second surface of the semiconductor die” in lines 3-4 should be “the second surface of the semiconductor ”, and “the first surface of the semiconductor die” in lines 4-5 should be “the first surface of the semiconductor ” for proper antecedent basis.
In Re Claims 15, 17-18, 34 and Claims 20-24, 35-36, they are objected to due to their dependence from Claims 14 and 20, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-15 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Winslow (US 2003/0178655 A1, of record) in view of Padmanathan et al (US 2014/0327107 A1, hereafter Padmanathan) and Noma et al (US 2019/0067164 A1, hereafter Noma).
Re Claim 14, Winslow discloses a semiconductor device (FIG. 7A; [0064]), comprising:
a semiconductor wafer (122; [0045]) including a plurality of semiconductor die ([0066]);
a first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]);
a first integrated passive device (IPD) (316; [0063]); and
an active device (295; [0064]) formed in a second surface of the semiconductor wafer (122, top surface as seen in FIG. 7A; [0064]) opposite the first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]).
Winslow does not explicitly disclose:
a semiconductor wafer (122) having a low resistivity of about 10 ohm-cm;
a first insulating layer formed over a first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A);
a second insulating layer formed over the first insulating layer;
a first integrated passive device (IPD) (316) formed over the second insulating layer.
However, Padmanathan teaches a semiconductor device (FIG. 3A; [0035]-[0037]) comprising wherein the semiconductor wafer (120; [0035]) has a low resistivity of about 10 ohm-cm ([0035]).
Additionally, Noma teaches a semiconductor device (FIG. 2S, with reference to FIG. 2H; [0036]-[0051]) comprising:
a first insulating layer (202a; [0031]) formed over a first surface of the semiconductor wafer (201, top surface as seen in FIG. 2S; [0031]);
a second insulating layer (202b; [0032]) formed over the first insulating layer (202a; [0032]);
a first integrated passive device (IPD) (208; [0037]) formed over the second insulating layer (202b; [0037]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Winslow with the limitations taught by Padmanathan to substitute the material of the semiconductor wafer (Winslow: 122) with a specifically low resistivity semiconductor base material to reduce costs in the manufacturing process as taught by Padmanathan ([0035]).
It would also have been obvious to modify the limitations taught by Winslow and Padmanathan with the limitations taught by Noma to substitute in a stacked insulating structure in the formation of the first integrated passive device (Winslow: 316) to create a vertically layered IPD structure with multiple metallization layers for higher density as taught by Noma ([0014]-[0015], [0022]) and as a functionally equivalent means of predictably forming insulation for an inductor with opposite wafer side access as taught by Noma ([0037]).
Re Claim 15, Winslow, Padmanathan, and Noma teach the semiconductor device according to Claim 14, while Winslow further teaches wherein the first IPD (316) includes a capacitor, resistor, or inductor ([0063]).
Re Claim 34, Winslow, Padmanathan, and Noma teach the semiconductor device according to Claim 14, while Winslow further teaches including a bond wire (740; [0065]) disposed over a first surface of the semiconductor die (700, top surface as seen in FIG. 7B; [0065]) and a bump (750; [0065], with solder used) disposed over a second surface of the semiconductor die (700, bottom surface as seen in FIG. 7B; [0065]) opposite the first surface of the semiconductor die (700, top surface as seen in FIG. 7B; [0065]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow, Padmanathan, and Noma, as applied to Claim 14, further in view of Tang et al (US 2023/0065844 A1, hereafter Tang).
Re Claim 17, Winslow, Padmanathan, and Noma teach the semiconductor device according to Claim 14, but they do not explicitly disclose the device comprises an interconnect structure formed over the first IPD (Winslow: 316).
However, Tang teaches a semiconductor device (FIG. 9; [0032]-[0039]) comprising an interconnect structure (114, 115; [0032]) formed over the first IPD (IN1; [0032]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 14 with the limitations taught by Tang to use a plurality of vertically stacked metallization/dielectric layers above the first IPD (Winslow: 316) tangential to the use of vertically stacked IPD metallization/dielectric layers (as taught in Claim 20) to allow for distinct metallization layers and the bond pad (Winslow: 315) to be exposed on the upper surface of the device for further connections as taught by Tang ([0032], [0039]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow, Padmanathan, Noma, and Tang, as applied to Claim 17, further in view of Liou et al (US 8,471,376 B1, hereafter Liou).
Re Claim 18, Winslow, Padmanathan, Noma, and Tang teach the semiconductor device according to Claim 17, but they do not explicitly disclose the device comprises:
an interconnect substrate, wherein the semiconductor die (Winslow: 122) is disposed over the interconnect substrate; and
a bond wire formed between the interconnect structure (Tang: 114, 115) and the interconnect substrate.
However, Liou teaches a semiconductor device (FIG. 5; column 6, line 26 to column 7, line 15) comprising:
an interconnect substrate (102; column 6, lines 28-29), wherein the semiconductor die (512; column 6, lines 28-29) is disposed over the interconnect substrate (102; column 6, lines 28-29); and
a bond wire (516; column 6, lines column 6, lines 46-51) formed between the interconnect structure (534, top section of 512) and the interconnect substrate (102; column 6, lines column 6, lines 46-51, of note, the interconnect structure is not required by the claim limitations to be electrically connected to the interconnect substrate).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 17 with the limitations taught by Liou to utilize an interconnect substrate (Liou: 102) along with bond wires (Liou: 516)/interconnects (Liou: 328) to provide external connection terminals for both the semiconductor die (Winslow: 122) and subsequently formed semiconductor dies (Liou: 532) as taught by Liou (column 6, lines 28-29).
Claims 20-22 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Winslow in view of Noma.
Re Claim 20, Winslow discloses a semiconductor device (FIG. 7A; [0064]), comprising:
a semiconductor wafer (122; [0045]) including a plurality of semiconductor die ([0066]);
a first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]);
a first integrated passive device (IPD) (316; [0063]); and
an active device (295; [0064]) formed in a second surface of the semiconductor wafer (122, top surface as seen in FIG. 7A; [0064]) opposite the first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]).
Winslow does not explicitly disclose:
a first insulating layer formed over a first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A);
a second insulating layer formed over the first insulating layer;
a first integrated passive device (IPD) (316) formed over the second insulating layer.
Noma teaches a semiconductor device (FIG. 2S, with reference to FIG. 2H; [0036]-[0051]) comprising:
a first insulating layer (202a; [0031]) formed over a first surface of the semiconductor wafer (201, top surface as seen in FIG. 2S; [0031]);
a second insulating layer (202b; [0032]) formed over the first insulating layer (202a; [0032]);
a first integrated passive device (IPD) (208; [0037]) formed over the second insulating layer (202b; [0037]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Winslow with the limitations taught by Noma to substitute in a stacked insulating structure in the formation of the first integrated passive device (Winslow: 316) to create a vertically layered IPD structure with multiple metallization layers for higher density as taught by Noma ([0014]-[0015], [0022]) and as a functionally equivalent means of predictably forming insulation for an inductor with opposite wafer side access as taught by Noma ([0037]).
Re Claim 21, Winslow and Noma teach the semiconductor device according to Claim 20, while Winslow further teaches wherein the first IPD (316) includes a capacitor, resistor, or inductor ([0063]).
Re Claim 22, Winslow and Noma teach the semiconductor device according to Claim 20, while Winslow further teaches the device comprises a second IPD (350; [0064]) formed over the second surface of the semiconductor die (122, top surface as seen in FIG. 7A; [0064]) opposite the first surface of the semiconductor die (122, bottom surface as seen in FIG. 7A; [0064]).
Re Claim 36, Winslow and Noma teach the semiconductor device according to Claim 20, while Winslow further teaches wherein the semiconductor wafer (122) includes a semiconductor die (700; [0065], see FIG. 7B) with a bond wire (740; [0065]) disposed over a first surface of the semiconductor die (700, top surface as seen in FIG. 7B; [0065]) and a bump (750; [0065], with solder used) disposed over a second surface of the semiconductor die (700, bottom surface as seen in FIG. 7B; [0065]) opposite the first surface of the semiconductor die (700, top surface as seen in FIG. 7B; [0065]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow and Noma, as applied to Claim 20, further in view of Tang.
Re Claim 23, Winslow and Noma teach the semiconductor device according to Claim 20, but they do not explicitly disclose the device comprises an interconnect structure formed over the first IPD (Winslow: 316).
However, Tang teaches a semiconductor device (FIG. 9; [0032]-[0039]) comprising an interconnect structure (114, 115; [0032]) formed over the first IPD (IN1; [0032]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 20 with the limitations taught by Tang to use a plurality of vertically stacked metallization/dielectric layers above the first IPD (Winslow: 316) tangential to the use of vertically stacked IPD metallization/dielectric layers (as taught in Claim 20) to allow for distinct metallization layers and the bond pad (Winslow: 315) to be exposed on the upper surface of the device for further connections as taught by Tang ([0032], [0039]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow, Noma, and Tang, as applied to Claim 23, further in view of Liou.
Re Claim 24, Winslow, Noma, and Tang teach the semiconductor device according to Claim 23, but they do not explicitly disclose the device comprises:
an interconnect substrate, wherein the semiconductor die (Winslow: 122) is disposed over the interconnect substrate; and
a bond wire formed between the interconnect structure (Tang: 114, 115) and the interconnect substrate.
However, Liou teaches a semiconductor device (FIG. 5; column 6, line 26 to column 7, line 15) comprising:
an interconnect substrate (102; column 6, lines 28-29), wherein the semiconductor die (512; column 6, lines 28-29) is disposed over the interconnect substrate (102; column 6, lines 28-29); and
a bond wire (516; column 6, lines column 6, lines 46-51) formed between the interconnect structure (534, top section of 512) and the interconnect substrate (102; column 6, lines column 6, lines 46-51, of note, the interconnect structure is not required by the claim limitations to be electrically connected to the interconnect substrate).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 23 with the limitations taught by Liou to utilize an interconnect substrate (Liou: 102) along with bond wires (Liou: 516)/interconnects (Liou: 328) to provide external connection terminals for both the semiconductor die (Winslow: 122) and subsequently formed semiconductor dies (Liou: 532) as taught by Liou (column 6, lines 28-29).
Claims 26-29 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Winslow in view of Noma and Tang.
Re Claim 26, Winslow discloses a semiconductor device (FIG. 7A; [0064]), comprising:
a semiconductor wafer (122; [0045]);
a first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]);
a first integrated passive device (IPD) (316; [0063]); and
an active device (295; [0064]) formed in a second surface of the semiconductor wafer (122, top surface as seen in FIG. 7A; [0064]) opposite the first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]).
Winslow does not explicitly disclose:
a first insulating layer formed over a first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A);
a second insulating layer formed over the first insulating layer;
a first integrated passive device (IPD) (316) formed over the second insulating layer;
an interconnect structure formed over the first IPD (316).
However, Noma teaches a semiconductor device (FIG. 2S, with reference to FIG. 2H; [0036]-[0051]) comprising:
a first insulating layer (202a; [0031]) formed over a first surface of the semiconductor wafer (201, top surface as seen in FIG. 2S; [0031]);
a second insulating layer (202b; [0032]) formed over the first insulating layer (202a; [0032]);
a first integrated passive device (IPD) (208; [0037]) formed over the second insulating layer (202b; [0037]).
Additionally, Tang teaches a semiconductor device (FIG. 9; [0032]-[0039]) comprising an interconnect structure (114, 115; [0032]) formed over the first IPD (IN1; [0032]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Winslow with the limitations taught by Noma to substitute in a stacked insulating structure in the formation of the first integrated passive device (Winslow: 316) to create a vertically layered IPD structure with multiple metallization layers for higher density as taught by Noma ([0014]-[0015], [0022]) and as a functionally equivalent means of predictably forming insulation for an inductor with opposite wafer side access as taught by Noma ([0037]).
It would have also been obvious to modify the limitations taught by Winslow and Noma with the limitations taught by Tang to use a plurality of vertically stacked metallization/dielectric layers above the first IPD (Winslow: 316) tangential to the use of vertically stacked IPD metallization/dielectric layers (as taught in Claim 20) to allow for distinct metallization layers and the bond pad (Winslow: 315) to be exposed on the upper surface of the device for further connections as taught by Tang ([0032], [0039]).
Re Claim 27, Winslow, Noma, and Tang teach the semiconductor device according to Claim 26, while Winslow further teaches wherein the first IPD (316) includes a capacitor, resistor, or inductor ([0063]).
Re Claim 28, Winslow, Noma, and Tang teach the semiconductor device according to Claim 26, while Winslow further teaches the device comprises a second IPD (350; [0064]) formed over the second surface of the semiconductor wafer (122, top surface as seen in FIG. 7A; [0064]) opposite the first surface of the semiconductor wafer (122, bottom surface as seen in FIG. 7A; [0064]).
Re Claim 29, Winslow, Noma, and Tang teach the semiconductor device according to Claim 26, while Tang further teaches including a third insulating layer (117; [0032]) formed over the interconnect structure (114, 115; [0032]).
No further modification made, see obviousness statement in Claim 26.
Re Claim 33, Winslow and Noma teach the semiconductor device according to Claim 26, while Winslow further teaches wherein the semiconductor wafer (122) includes a semiconductor die (700; [0065], see FIG. 7B) with a bond wire (740; [0065]) disposed over a first surface of the semiconductor die (700, top surface as seen in FIG. 7B; [0065]) and a bump (750; [0065], with solder used) disposed over a second surface of the semiconductor die (700, bottom surface as seen in FIG. 7B; [0065]) opposite the first surface of the semiconductor die (700, top surface as seen in FIG. 7B; [0065]).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow, Noma, and Tang, as applied to Claim 26, further in view of Liou.
Re Claim 30, Winslow, Noma, and Tang teach the semiconductor device according to Claim 26, but they do not explicitly disclose the device comprises:
an interconnect substrate, wherein a semiconductor die from the semiconductor wafer (Winslow: 122) is disposed over the interconnect substrate; and
a bond wire formed between the interconnect structure (Tang: 114, 115) and the interconnect substrate.
However, Liou teaches a semiconductor device (FIG. 5; column 6, line 26 to column 7, line 15) comprising:
an interconnect substrate (102; column 6, lines 28-29), wherein a semiconductor die (512; column 6, lines 28-29) from the semiconductor wafer (512; column 6, lines 28-29) is disposed over the interconnect substrate (102; column 6, lines 28-29); and
a bond wire (516; column 6, lines column 6, lines 46-51) formed between the interconnect structure (534, top section of 512) and the interconnect substrate (102; column 6, lines column 6, lines 46-51, of note, the interconnect structure is not required by the claim limitations to be electrically connected to the interconnect substrate).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 26 with the limitations taught by Liou to utilize an interconnect substrate (Liou: 102) along with bond wires (Liou: 516)/interconnects (Liou: 328) to provide external connection terminals for both the semiconductor die (Winslow: 122) and subsequently formed semiconductor dies (Liou: 532) as taught by Liou (column 6, lines 28-29).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow, Noma, and Tang, as applied to Claim 26, further in view of Padmanathan.
Re Claim 32, Winslow, Noma, and Tang teach the semiconductor device according to Claim 26, but they do not explicitly disclose wherein the semiconductor wafer (Winslow: 122) has a low resistivity of about 10 ohm-cm.
However, Padmanathan teaches a semiconductor device (FIG. 3A; [0035]-[0037]) comprising wherein the semiconductor wafer (120; [0035]) has a low resistivity of about 10 ohm-cm ([0035]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 26 with the limitations taught by Padmanathan to substitute the material of the semiconductor wafer (Winslow: 122) with a specifically low resistivity semiconductor base material to reduce costs in the manufacturing process as taught by Padmanathan ([0035]).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Winslow and Noma, as applied to Claim 20, further in view of Padmanathan.
Re Claim 35, Winslow and Noma teach the semiconductor device according to Claim 20, but they do not explicitly disclose wherein the semiconductor wafer (Winslow: 122) has a low resistivity of about 10 ohm-cm.
However, Padmanathan teaches a semiconductor device (FIG. 3A; [0035]-[0037]) comprising wherein the semiconductor wafer (120; [0035]) has a low resistivity of about 10 ohm-cm ([0035]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device according to Claim 20 with the limitations taught by Padmanathan to substitute the material of the semiconductor wafer (Winslow: 122) with a specifically low resistivity semiconductor base material to reduce costs in the manufacturing process as taught by Padmanathan ([0035]).
Response to Arguments
Applicant’s arguments, see Remarks pg. 1, para. 3 to pg. 5, para. 2, filed 5/9/2025, with respect to the rejection(s) of claim(s) 14, 20, and 26 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Winslow, Padmanathan, Noma, and Tang under 35 U.S.C. 103. Applicant’s arguments with respect to claim(s) 14, 20, and 26 have been reconsidered under the new rejections but are moot because the new ground(s) of rejection do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
