DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/12/2026 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 8/12/2026. Claims 1-15 and 21-25 are pending in this application. Claims 1-2, 4, 6, 8-12, 14-15, and 21-24 are amended.
Information Disclosure Statement
Applicant is suggested/reminded to disclose relevant prior art(s) or other information that may be material to the patentability of the invention in a pending application. The prior art information must be submitted in the form of an Information Disclosure Statement (“IDS”) (see MPEP 609 & 2001 and 37 CFR 1.56).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor, at the time the application was filed, had possession of the claimed invention.
Claim 10 has been amended to recite limitation “the second seal ring including a corresponding odd number of turning points conformal to the corner” in lines 5-6. However, the originally filed specification does not reasonably convey to a person of ordinary skill in the art that the inventor had possession of a semiconductor device in which the second seal ring has an odd number of turning points, as now claimed.
The Specification discloses that the corner of the chip 20J may have an odd number of turning points, for example, three turning points as illustrated in FIG. 25A [0050]. However, the Specification does not disclose that the seal ring structure 135 has a corresponding odd number of turning points. Rather, with respect to turning points of the seal ring structure, the Specification states that the seal ring structure 135 “includes at least two turning points near the corner of the chip 20A” [0048].
The Specification further discloses that the seal ring structure 135 is “in a form of multiple continuous polylines conformal to the continuous polylines surrounding the chip 20J” [0049]. This disclosure describes the conformal relationship between the seal ring structure and the continuous polylines surrounding the chip, but does not disclose that the seal ring structure has the same, or a corresponding odd number of turning points as the corner of the chip.
Accordingly, the originally filed disclosure does not reasonably convey to one of ordinary skill in the art that the inventor had possession of a second seal ring including a corresponding odd number of turning points conformal to the corner, as presently claimed.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2010/0140749) in view of Yang et al. (US 2014/0327151; hereinafter ‘Yang’) and Yamada et al. (US 2019/0051620; hereinafter ‘Yamada’).
Regarding claim 1, Kuo teaches a semiconductor device (3D package structure, FIG. 1, [0007]), comprising:
a first chip (1, [0008]); and
a second chip (2, [0009]),
bonded over and electrically connected to the first chip (2 bonded over and electrically connected to 1 through solder balls 26 and contact pads 15, FIG. 1, [0009]), and
including a central region (an internal region of 2 including circuit area 331, TSV 34, and connecting circuit 333, FIG. 3, [0024-0025]; hereinafter ‘2CR’) surrounded by a seal ring (an outermost shelter 332 of a plurality of shelter structures surrounding internal semiconductor structures, wherein each shelter has any combination of a continuous or dispersed configuration and a polygonal configuration, FIGS. 8 and 11, [0030-0032]; hereinafter ‘332outer’),
wherein the seal ring is disposed within the second chip (332outer being formed within 2 as part of metal interconnect layers 33, FIGS. 3 and 11, [0024-0025, 0031-0032]),
wherein the central region of the second chip (2CR) comprises:
a layer (circuit area 331, FIG. 3, [0024]);
a transistor (transistor included in 331, [0025]; hereinafter ‘Tr’) disposed in the layer (Tr disposed in 331, FIG. 3);
at least one through silicon via (TSV) (34, FIG. 3, [0024]) extending from a substrate (31, FIG. 3, [0024]; 34 penetrating 31, FIG. 3); and
an interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 3, [0024]; hereinafter ‘IS’) disposed over the circuit area (IS disposed over 331) and including a conductive line (horizontal metal layers of IS; hereinafter ‘IS-L’) and a conductive via (vertical interconnections of IS; hereinafter ‘IS-V’) electrically connecting to the transistor (IS-L and IS-V electrically connecting to Tr, FIG. 3, [0024-0025]), and
wherein the transistor (Tr), the TSV (34) and the interconnect structure (IS) are located in the central region surrounded by the seal ring (Tr in 331, 34, and IS being disposed in 2CR and surrounded by 332outer, FIGS. 3, 8, 10, [0024-0025, 0030-0032]).
Kuo does not teach that the layer including the transistor in the second chip is an insulating layer and the TSV extends through the insulating layer.
Yang teaches a semiconductor device (100, FIG. 4, [0013]) wherein the second chip comprises an insulating layer (14 is insulating layer, [0017]) including a transistor (transistor 140, [0016, 0022]) and a TSV (25, [0022]) extending through the insulating layer (25 extending through 14, FIG. 4).
As taught by Yang, one of ordinary skill in the art would utilize and modify the above teaching into Kuo to obtain and achieve the semiconductor device wherein the second chip comprises an insulating layer including a transistor and a TSV extending through the insulating layer as claimed, because the insulating layer electrically isolates conductive features associated with the transistor while accommodating a TSV extending through the layer for vertical electrical connection [0016-0019].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Yang in combination with Kuo due to the above reason.
Kuo in view of Yang does not teach the semiconductor device wherein the seal ring is disposed at a periphery of the second chip; wherein the second chip, from a top view, includes a first number of sides, the seal ring includes a second number of sides from the top view, the first number is greater than four, and the second number is equal to or greater than the first number.
Yamada teaches a semiconductor device (FIG. 16, [0256])
wherein the seal ring (3, FIG. 16, [0043]) is disposed at a periphery of the second chip (3 disposed within the semiconductor chip at the boundary between central element region 8a and outer peripheral region 8c, FIG. 16, [0035-0036, 0043]);
wherein the second chip (the chip defined along the scribe line corresponding to 1, [0092]; hereinafter ‘SCYamada’), from a top view (a plane view), includes a first number of sides from the top view (SCYamada includes at least 5 sides),
the seal ring (3) includes a second number of sides from the top view (3 includes at least 5 sides),
the first number is greater than four (the first number is 5), and
the second number is equal to or greater than the first number (shown in FIG. 16).
As taught by Yamada, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yang to obtain and achieve the semiconductor device wherein the seal ring is disposed at a periphery of the second chip; wherein the second chip, from a top view, includes a first number of sides, the seal ring includes a second number of sides from the top view, the first number is greater than four, and the second number is equal to or greater than the first number as claimed, because a peripheral frame-shaped shield prevents moisture and other undesirable agents from entering and damaging semiconductor components in the central region [0005, 0043-0044], while a chamfered polygonal chip configuration reduces stress concentration and suppresses crack propagation at the chip corner [0049, 0255].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Yamada in combination with Kuo in view of Yang due to the above reason.
Regarding claim 3, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 1, Kuo in view of Yang does not teach the semiconductor device wherein the sides of the second chip include a beveled edge, a chamfered edge or a fillet edge.
Yamada teaches the semiconductor device wherein the sides of the second chip include a beveled edge, a chamfered edge or a fillet edge (SCYamada includes a chamfered edge, FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the sides of the second chip include a beveled edge, a chamfered edge or a fillet edge as claimed, because a chamfered corner locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Regarding claim 5, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 1, Kuo in view of Yang does not teach the semiconductor device wherein the second chip includes a buffer region at a corner intersected by two adjacent sides.
Yamada teaches the semiconductor device wherein the second chip includes a buffer region (SCYamada includes the locally recessed corner region, FIG. 16; hereinafter ‘BRYamada’) at a corner intersected by two adjacent sides (shown in FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Yamada to obtain and the semiconductor device wherein the second chip includes a buffer region at a corner intersected by two adjacent sides as claimed, because the buffer region locally reduces stress concentration and suppresses straight-line crack propagation at the chip corner, thereby improving the protection of internal structures [0255].
Regarding claim 7, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 5, Kuo in view of Yang does not teach the semiconductor device wherein the seal ring extends across the buffer region.
Yamada teaches the semiconductor device wherein the seal ring extends across the buffer region (3 extends across BRYamada, FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the seal ring extends across the buffer region as claimed, because it prevents a discontinuity of the protection at the buffer region, thereby improving crack blocking and moisture protection [0264, 0266].
Regarding claim 8, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 5, Kuo in view of Yang does not teach the semiconductor device wherein the buffer region is in a triangular shape from the top view, a longest side of the triangular buffer region facing the corner, and the seal ring including a turning point overlapping the buffer region.
Yamada teaches the semiconductor device wherein
the buffer region is in a triangular shape from the top view (BRYamada is in a triangular shape, FIG. 16), a longest side of the triangular buffer region facing the corner (the longest side of BRYamada faces the chip corner, FIG. 16), and
the seal ring including a turning point overlapping the buffer region (the moisture resistant frame shaped shield 3 includes a turning point located within BRYamada, FIG. 16, [0256]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yamada to obtain and achieve the semiconductor device wherein the buffer region is in a triangular shape from the top view, a longest side of the triangular buffer region facing the corner, and the seal ring including a turning point overlapping the buffer region as claimed, because chamfering the corners reduces stress concentration by dispersing stress at the corners [0048-0049].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2010/0140749) in view of Yang (US 2014/0327151) and Yamada (US 2019/0051620) as applied to claim 1 above, and further in view of MICCOLI (US 2018/0096952).
Regarding claim 2, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 1,
wherein the seal ring (Kuo: 332outer) extends continuously along the sides of the second chip from the top view (332outer having a continuous, closed polygonal configuration, FIGS. 6, 8, 10, and 11, [0029-0032]),
wherein the seal ring comprises
a plurality of metal layers vertically stacked over and electrically coupled to one another (332outer comprising a plurality of vertically stacked metal interconnect layers 33 electrically coupled through conductive vias, FIG. 3, [0024]),
a bottommost one of the metal layers contacting the substrate (a bottommost one of 33 of 332outer contacting 31, FIG. 3).
Kuo in view of Yang and Yamada does not teach the semiconductor device wherein the seal ring is electrically connected to a first pad that is separate from a second contact pad electrically connected to the interconnect structure.
MICCOLI teaches a semiconductor device (FIG. 3A, [0022])
wherein the seal ring (seal rings 160a and 160b, [0058]) is electrically connected to a first pad (M6 contact pad layer portion electrically connected to 160a and 160b, FIG. 3A, [0077-0079]; hereinafter ‘160CP’)
that is separate from a second contact pad (160CP being separate from contact pads 240 and 242, FIG. 3A, [0079]) electrically connected to the interconnect structure (240 and 242 being electrically connected to the respective metallization layers M1-M5 and via contacts V1-V5 associated with transistor 230a and 230b, FIG. 3A, [0059, 0075, 0079]).
As taught by MICCOLI one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yang and Yamada to obtain and achieve the semiconductor device wherein the seal ring is electrically connected to a first pad that is separate from a second contact pad electrically connected to the interconnect structure as claimed, because the separate contact pad permit independent external electrical access to the seal ring and the functional circuitry of the chip [0079, 0135].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by MICCOLI in combination with Kuo in view of Yang and Yamada due to above reason.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2010/0140749) in view of Yang (US 2014/0327151) and Yamada (US 2019/0051620) as applied to claim 1 above, and further in view of Mariani et al. (US 2015/0069576; hereinafter ‘Mariani’).
Regarding claim 4, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein the second chip has a plurality of substantially rounded corners from the top view, each of the substantially rounded corners having a round surface spaced apart from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer (μm).
Mariani teaches a semiconductor device (11, FIGS. 4A and 4B, [0039-0040]) wherein
the second chip (12, [0040]) has a plurality of substantially rounded corners from the top view (12 has 4 rounded corners from the top view, FIG. 4B),
each of the substantially rounded corners having a round surface spaced apart from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 μm (each rounded corner includes an arc-shaped surface spaced apart from an intersection point of extension lines of the corresponding two sides; for a 90º rounded corner with a radius of about 80-90 μm, the shortest distance from that intersection point to the arc is about 33.1-37.3 μm, FIG. 4B, [0042-0044]).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yang ad Yamada to obtain and achieve the semiconductor device wherein the second chip has a plurality of substantially rounded corners from the top view, each of the substantially rounded corners having a round surface spaced apart from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 μm as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) and it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Mariani in combination with Kuo in view of Yang and Yamada due to the above reason.
Regarding claim 6, Kuo in view of Yang and Yamada teaches the semiconductor device of claim 5, but Kuo in view of Yang and Yamada does not teach the semiconductor device wherein the buffer region has a longest side distant from the corner by at least 1 micrometer (μm), the longest side being spaced apart from an intersection point of extension lines of the two adjacent sides by said at least 1 micrometer.
Mariani teaches a semiconductor device (11, FIGS. 4A and 4B, [0039-0040]) wherein
the buffer region (the portion of chip 12 adjacent to beveled corner 15 is the buffer region, FIG. 3A, [0045]) has a longest side distant from the corner by at least 1 μm (the beveled edge is the longest side; for a 90º beveled corner extending about 80-90 μm along each adjacent side, its distance from the corner is about 56.6-63.6 μm, FIG. 3A, [0043-0045]) ,
the longest side being spaced apart from an intersection point of extension lines of the two adjacent sides by said at least 1 micrometer (the same 56.6-63.6 μm distance from the intersection point of the extended sides to the beveled edge, FIG. 3A).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Kuo in view of Yang and Yamada to obtain and achieve the semiconductor device wherein the buffer region has a longest side distant from the corner by at least 1 μm as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) and it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Mariani in combination with Kuo in view of Yang and Yamada due to the above reason.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2015/0125994; hereinafter ‘Lin’) in view of Kuo (US 2010/0140749), Yang (US 2014/0327151), and Rostoker et al. (US 5808330; hereinafter ‘Rostoker’).
Regarding claim 9, Lin teaches a semiconductor device (70, Figure 3A, [0024]), comprising:
a bottom chip (an active die used in place of interposer 12, Figure 3A, [0019, 0024]);
a first chip (18, Figure 3A, [0024]), bonded over and electrically connected to the bottom chip (18 mechanically coupled over and electrically connected to the active die replacing 12, [0018]); and
a second chip (20, Figure 3A, [0024]), disposed at a same level as the first chip (20 disposed at the same level as 18, Figure 3A), bonded over and electrically connected to the bottom chip (20 mechanically coupled over and electrically connected to the active die replacing 12, [0018]),
the first chip (18 having the structure of left die 90, Figures 3A-3B and 6, [0043]) further includes a first central region (left active region 92, Figure 6, [0029]) surrounded by a first seal ring (left 94, Figure 6, [0029]) inside the first chip (18) and wherein the first central region of the first chip is surrounded by the first seal ring (92 of 18 is surrounded by 94, Figure 6);
the second chip (20 having the structure of right die 90, Figures 3A-3B and 6, [0043]) further includes a second central region (right active region 92, Figure 6, [0029]) surrounded by a second seal ring (right 94, Figure 6, [0029]) inside the second chip (20) and wherein the second central region of the second chip is surrounded by the first seal ring (92 of 20 is surrounded by 94, Figure 6).
Lin does not teach the semiconductor device comprising: the first chip comprising an insulating layer including a transistor; at least one through silicon via (TSV) extending through and above the insulating layer; and an interconnect structure disposed over the insulating layer and including a conductive line and a conductive via electrically connecting to the transistor; and the second chip comprising an insulating layer including a transistor; at least one through silicon via (TSV) extending through and above the insulating layer; and an interconnect structure disposed over the insulating layer and including a conductive line and a conductive via electrically connecting to the transistor; wherein the transistor, the TSV and the interconnect structure are located in the first central region of the first chip and are surrounded by the first seal ring; and wherein the transistor, the TSV and the interconnect structure are located in the second central region of the second chip and are surrounded by the second seal ring.
Kuo teaches a semiconductor device (3D package structure, FIG. 1, [0007]), comprising:
the first chip (2, [0009]) comprising
a layer (circuit area 331, FIG. 3, [0024]) including a transistor (transistor included in 331, [0025]; hereinafter ‘Tr’);
at least one TSV (34, FIG. 3, [0024]) extending above the layer (34 extending above 331, FIG. 3); and
an interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 3, [0024]; hereinafter ‘IS’) disposed over the layer (IS disposed over 331, FIG. 3), and including a conductive line (horizontal metal layers of IS; hereinafter ‘IS-L’) and a conductive via (vertical interconnections of IS; hereinafter ‘IS-V’) electrically connecting to the transistor (IS-L and IS-V electrically connecting to Tr, FIG. 3, [0024-0025]); and
the second chip (another chip having the structure of chip 2, [0009]) comprising
a layer (circuit area 331, FIG. 3, [0024]) including a transistor (transistor included in 331, [0025]; hereinafter ‘Tr’);
at least one TSV (34, FIG. 3, [0024]) extending above the layer (34 extending above 331, FIG. 3); and
an interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 3, [0024]; hereinafter ‘IS’) disposed over the layer (IS disposed over 331, FIG. 3) and including a conductive line (horizontal metal layers of IS; hereinafter ‘IS-L’) and a conductive via (vertical interconnections of IS; hereinafter ‘IS-V’) electrically connecting to the transistor (IS-L and IS-V electrically connecting to Tr, FIG. 3, [0024-0025])
wherein the transistor, the TSV and the interconnect structure are located in the first central region of the first chip (an internal region of 2 including circuit area 331 with transistor, TSV 34, and connecting circuit 333, FIG. 3, [0024-0025]; hereinafter ‘2CR’) and are surrounded by the first seal ring (an outermost shelter 332 of a plurality of shelter structures surrounding internal semiconductor structures, wherein each shelter has any combination of a continuous or dispersed configuration and a polygonal configuration, FIGS. 8 and 11, [0030-0032]; hereinafter ‘332outer’); and
wherein the transistor, the TSV and the interconnect structure are located in the second central region of the second chip (an internal region of 2 including circuit area 331 with transistor, TSV 34, and connecting circuit 333, FIG. 3, [0024-0025]; hereinafter ‘2CR’) and are surrounded by the second seal ring (an outermost shelter 332 of a plurality of shelter structures surrounding internal semiconductor structures, wherein each shelter has any combination of a continuous or dispersed configuration and a polygonal configuration, FIGS. 8 and 11, [0030-0032]; hereinafter ‘332outer’).
As taught by Kuo, one of ordinary skill in the art would utilize and modify the above teaching into Lin to obtain and achieve the semiconductor device comprising: the first chip comprising a layer including a transistor; at least one TSV extending above the layer; and an interconnect structure disposed over the layer and including a conductive line and a conductive via electrically connecting to the transistor; and the second chip comprising a layer including a transistor; at least one TSV extending above the layer; and an interconnect structure disposed over the layer and including a conductive line and a conductive via electrically connecting to the transistor; wherein the transistor, the TSV and the interconnect structure are located in the first central region of the first chip and are surrounded by the first seal ring; and wherein the transistor, the TSV and the interconnect structure are located in the second central region of the second chip and are surrounded by the second seal ring as claimed, because TSVs provide shorter interconnection routes between chips thereby increasing operating speed and improving package efficiency, and the surrounding shelter structures can be formed simultaneously with the connecting circuits using existing metal interconnect fabrication processes [0006-0007, 0032]. Further, it has been held that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Kuo in combination with Lin due to the above reason.
Lin in view of Kuo does not teach that the layer including the transistor in each of the first and second chips is an insulating layer and the TSV extends through the insulating layer.
Yang teaches a semiconductor device (100, FIG. 4, [0013]) wherein each of the first and second chips comprises an insulating layer (14 is insulating layer, [0017]) including a transistor (transistor 140, [0016, 0022]) and a TSV (25, [0022]) extending through the insulating layer (25 extending through 14, FIG. 4).
As taught by Yang, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo to obtain and achieve the semiconductor device wherein each of the first and second chips comprises an insulating layer including a transistor and a TSV extending through the insulating layer as claimed, because the insulating layer electrically isolates conductive features associated with the transistor while accommodating a TSV extending through the layer for vertical electrical connection [0016-0019].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Yang in combination with Lin in view of Kuo due to the above reason.
Lin in view of Kuo and Yang does not teach the semiconductor device wherein the second chip includes a corner having an interior angle less than 90 degrees from a top view, the first chip includes a first number of sides from the top view, the second chip includes a second number of sides from the top view, the second number is greater than the first number.
Rostoker teaches a semiconductor device (93, FIG. 1, col. 4, lines 31-32) wherein
the second chip (logic gate 96 which is the larger diamond-shaped megafunction cell, FIGS. 1 and 18, col. 4, line 41, col. 24, lines 62-63; hereinafter ‘SCRostoker’) includes a corner having an interior angle less than 90 degrees from a top view (interior angle of SCRostoker is 60 degree, FIG. 18),
the first chip (96 which is the larger triangular-shaped megafunction cell 207, FIGS. 1 and 19, col. 4, line 41, col. 24, lines 64-65; hereinafter ‘FCRostoker’) includes a first number of sides from the top view (FCRostoker has 3 sides),
the second chip includes a second number of sides from the top view (SCRostoker has 4 sides),
the second number is greater than the first number (4 is greater than 3).
As taught by Rostoker, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo and Yang to obtain and achieve the semiconductor device wherein the second chip includes a corner having an interior angle less than 90 degrees from a top view, the first chip includes a first number of sides from the top view, the second chip includes a second number of sides from the top view, the second number is greater than the first number as claimed, because selecting die shapes compatible with the circuit topology and the required functional area to I/O area ratio would accommodate the circuitry and package constraints (col. 84, lines 32-35 and col. 85, lines 21-26). Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Rostoker in combination with Lin in view of Kuo and Yang due to the above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Kuo (US 2010/0140749), Yang (US 2014/0327151), and Rostoker (US 5808330) as applied to claim 9 above, and further in view of Mariani (US 2015/0069576), Cadouri (US 2006/0278956), and Chien et al. (US 2014/0264710; hereinafter ‘Chien’).
Regarding claim 10, Lin in view of Kuo, Yang, and Rostoker teaches the semiconductor device of claim 9, the corner of the second chip includes a vertex (Lin: 20 includes a vertex, Figures 4A and 4B).
Lin in view of Kuo, Yang, and Rostoker does not teach the semiconductor device wherein the vertex is away from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer.
Mariani teaches a semiconductor device (11, FIGS. 4A and 4B, [0039-0040]) wherein the vertex is away from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer (each rounded corner includes an arc-shaped surface spaced apart from an intersection point of extension lines of the corresponding two sides; for a 90º rounded corner with a radius of about 80-90 μm, the shortest distance from that intersection point to the arc is about 33.1-37.3 μm, FIG. 4B, [0042-0044]).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, and Rostoker to obtain and achieve the semiconductor device wherein the vertex is away from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Mariani in combination with Lin in view of Kuo, Yang, and Rostoker due to the above reason.
Lin in view of Kuo, Yang, Rostoker, and Mariani does not teach the semiconductor device wherein the corner having an odd number of turning points.
Cadouri teaches a semiconductor device (FIG. 4, [0014]) wherein the corner having an odd number of turning points (the corner of dice 121-124 having 3 turning points, FIG. 4, [0027]).
As taught by Cadouri, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, Rostoker, and Mariani to obtain and achieve the semiconductor device wherein the corner having an odd number of turning points as claimed, because it provides increased spacing between adjacent die corners for accommodating sacrificial structures while maintaining a smaller minimum spacing between adjacent dies [0008, 0023, 0027]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Cadouri in combination with Lin in view of Kuo, Yang, Rostoker, and Mariani due to the above reason.
Lin in view of Kuo, Yang, Rostoker, Mariani, and Cadouri does not teach the semiconductor device wherein the second seal ring including a corresponding odd number of turning points conformal to the corner.
Chien teaches a semiconductor device (FIG. 1, [0008]) wherein the second seal ring (10, FIG. 1, [0014]) including a corresponding odd number of turning points conformal to the corner (10 including 5 turning points at corner junction 13 corresponding to 5 junctions formed between sides 50 and line segments 142, 144, 146, and 148, Fig. 3G, [0028]).
As taught by Chien, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, Rostoker, Mariani, and Cadouri to obtain and achieve the semiconductor device wherein the second seal ring including a corresponding odd number of turning points conformal to the corner as claimed, because multiple turning points provides a smoother transition between adjacent sides of the seal ring, thereby reducing stress and charge concentration at the corner [0005, 0015]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chien in combination with Lin in view of Kuo, Yang, Rostoker, Mariani, and Cadouri due to the above reason.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Kuo (US 2010/0140749), Yang (US 2014/0327151), and Rostoker (US 5808330) as applied to claim 9 above, and further in view of Grivna et al. (US 2011/0177675; hereinafter ‘Grivna’).
Regarding claim 11, Lin in view of Kuo, Yang, and Rostoker teaches the semiconductor device of claim 9,
wherein the second chip (Lin: 20, Figures 3A and 3B) has a substantially L-shaped, U-shaped, star-shaped, cross-shaped, lightning-shaped, diamond, kite, chamfered, trapezoidal, parallelogrammatic, triangular, pentagonal, hexagonal, heptagonal or octagonal profile from the top view (20 having a parallelogrammatic profile from the top view, Figure 3B), and
the semiconductor device further comprises a third chip (22, Figure 3A, [0024]) disposed at the same level as the first chip and the second chip over the bottom chip (22 disposed at the same level as 18 and 20 over 12, Figures 3A and 3B),
wherein each of the first, second and third chips includes a respective seal ring inside the chip (each die 90 including a respective seal ring 94 inside the die and such feature being applicable to dies 18, 20, and 22, Figures 3B and 6, [0043]).
Lin in view of Kuo, Yang, and Rostoker does not teach the semiconductor device wherein the first chip, the second chip and the third chip have three different numbers of sides from the top view.
Grivna teaches a semiconductor device (FIG. 2, [0026]) wherein the first chip, the second chip and the third chip have three different numbers of sides from the top view (die 41, 42, and 67 have three different numbers of sides from the top view, FIG. 2, [0034, 0037]).
As taught by Grivna, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, and Rostoker to obtain and achieve the semiconductor device wherein the first chip, the second chip and the third chip have three different numbers of sides from the top view as claimed, because arranging dies having different peripheral shapes allows the dies to be arranged to maximize wafer utilization and increase the number of dies that can be formed in a given wafer area [0033-0034]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Grivna in combination with Lin in view of Kuo, Yang, and Rostoker due to the above reason.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Kuo (US 2010/0140749), Yang (US 2014/0327151), and Rostoker (US 5808330) as applied to claim 9 above, and further in view of Chien (US 2014/0264710).
Regarding claim 12, Lin in view of Kuo, Yang, and Rostoker teaches the semiconductor device of claim 9, but does not teach the semiconductor device wherein the first seal ring includes at least two turning points near the corner, and the second seal ring includes at least two turning points near a corresponding corner of the second chip, the turning points of the first seal ring and the second seal ring being respectively conformal to corners of the first chip and the second chip.
Chien teaches a semiconductor device (FIG. 1, [0008]) wherein
the first seal ring includes at least two turning points near the corner (10 of the first chip includes at least two turning points near the corner, FIGS. 3A-3F, [0022]) and
the second seal ring includes at least two turning points near a corresponding corner of the second chip (10 of the second chip includes at least two turning points near the corner, FIGS. 3A-3F, [0022]),
the turning points of the first seal ring and the second seal ring being respectively conformal to corners of the first chip and the second chip (the turning points of respective seal rings 10 extending along and conforming to the corresponding corners of the respective chips, FIGS. 3A-3F, [0022]).
As taught by Chien, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, and Rostoker to obtain and achieve the semiconductor device wherein the first seal ring includes at least two turning points near the corner, and the second seal ring includes at least two turning points near a corresponding corner of the second chip, the turning points of the first seal ring and the second seal ring being respectively conformal to corners of the first chip and the second chip as claimed, because forming the seal ring with multiple turning points conforming to the chip corner provides a smoother transition between adjacent sides of the seal ring, thereby reducing stress and charge concentration at the corner [0005, 0015]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chien in combination with Lin in view of Kuo, Yang, and Rostoker due to the above reason.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Kuo (US 2010/0140749), Yang (US 2014/0327151), and Rostoker (US 5808330) as applied to claim 9 above, and further in view of Mariani (US 2015/0069576).
Regarding claim 13, Lin in view of Kuo, Yang, and Rostoker teaches the semiconductor device of claim 9, but does not teach the semiconductor device wherein the corner of the second chip has a plurality of continuous first polylines.
Mariani teaches a semiconductor device (300A, FIS. 3A, [0034]) wherein the corner of the second chip has a plurality of continuous first polylines (the beveled corner 15 being defined by a polygonal line including two line segments joined together, [0035, 0045]).
As taught by Mariani, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, and Rostoker to obtain and achieve the semiconductor device wherein the corner of the second chip has a plurality of continuous first polylines as claimed, because forming the chip with beveled corners reduces break-off and damage at the edges or corners of the semiconductor chip during separation [0059]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Mariani in combination with Lin in view of Kuo, Yang, and Rostoker due to the above reason.
Regarding claim 14, Lin in view of Kuo, Yang, Rostoker and Mariani teaches the semiconductor device of claim 13, Lin in view of Kuo, Yang, and Rostoker does not teach the semiconductor device wherein the corner has a substantially rounded profile from the top view, the substantially rounded profile including a round surface spaced apart from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer.
Mariani teaches the semiconductor device wherein the corner has a substantially rounded profile from the top view (the corner 16 of semiconductor chip 12 having a rounded profile, FIG. 3B, [0035]; see also rounded corners 14, FIG. 4B, [0042-0044]), the substantially rounded profile including a round surface spaced apart from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer (each rounded corner 14 including an arc-shaped surface spaced apart from the intersection point of extension lines of the corresponding two sides; for a 90º rounded corner with a radius of about 80-90 μm, the shortest distance from that intersection point to the arc is about 33.1-37.3 μm, FIG. 4B, [0042-0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Mariani to obtain and achieve the semiconductor device wherein the corner has a substantially rounded profile from the top view, the substantially rounded profile including a round surface spaced apart from an intersection point of extension lines of two farthest edges corresponding to the corner by at least 1 micrometer as claimed, because rounding the corners of the semiconductor chip reduces the concentration of stress at the edges or corners [0059-0060]. Further it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Kuo (US 2010/0140749), Yang (US 2014/0327151), Rostoker (US 5808330), and Mariani (US 2015/0069576) as applied to claim 13 above, and further in view of Chien (US 2014/0264710) and Furusawa et al. (US 2011/0215447; hereinafter ‘Furusawa’).
Regarding claim 15, Lin in view of Kuo, Yang, Rostoker, and Mariani teaches the semiconductor device of claim 13, Lin in view of Kuo, Yang, and Mariani does not teach the semiconductor device wherein the corner of the second chip having an interior angle less than 90 degrees from the top view.
Rostoker teaches the semiconductor device wherein the corner of the second chip (SCRostoker,, FIGS. 1 and 18, col. 4, line 41, col. 24, lines 62-63) having an interior angle less than 90 degrees from the top view (interior angle of SCRostoker is 60 degree, FIG. 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Rostoker to obtain and achieve the semiconductor device wherein the corner of the second chip having an interior angle less than 90 degrees from the top view as claimed, because selecting die shapes compatible with the circuit topology and the required functional area to I/O area ratio would accommodate the circuitry and package constraints (col. 84, lines 32-35 and col. 85, lines 21-26). Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Lin in view of Kuo, Yang, Rostoker, and Mariani does not teach the semiconductor device wherein the second seal ring has a plurality of continuous second polylines conformal to the plurality of continuous first polylines.
Chien teaches a semiconductor device (FIG. 1, [0008]) wherein the second seal ring has a plurality of continuous second polylines conformal to the plurality of continuous first polylines (seal ring 10 having a plurality of continuously connected line segments conforming to the corresponding plurality of line segments defining the chip corner, FIG. 3G, [0028]).
As taught by Chien, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, Rostoker, and Mariani to obtain and achieve the semiconductor device wherein the second seal ring has a plurality of continuous second polylines conformal to the plurality of continuous first polylines as claimed, because forming the seal ring with multiple continuous line segments conforming to the corresponding line segments of the chip corner provides a smoother transition between adjacent sides of the seal ring, thereby reducing stress and charge concentration at the corner [0005, 0015]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chien in combination with Lin in view of Kuo, Yang, Rostoker, and Mariani due to the above reason.
Lin in view of Kuo, Yang, Rostoker, Mariani, and Chien does not teach the semiconductor device wherein a number of the continuous second polylines being equal to a number of the continuous first polylines.
Furusawa teaches a semiconductor device [0013] wherein the seal ring has a polygonal shape along an outer periphery of the chip in the plan view (claims 25 and 32) and the seal ring includes sides corresponding to the chip end surfaces, including first and second sides parallel to respective chip end surfaces [0034].
Although, Furusawa does not explicitly specify that a number of the corresponding seal ring polylines is equal to a number of the chip polylines.
Furusawa, however, teaches forming the polygonal seal ring along the outer periphery of the chip and configuring the seal ring sides in correspondence with the chip end surfaces (claims 25 and 32, [0034]). Furthermore, Furusawa teaches an outer seal ring arrange in a closed loop form along the outer line of the entirety of the semiconductor device [0055].
As taught by Furusawa, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Kuo, Yang, Rostoker, Mariani, and Chien to obtain and achieve the semiconductor device wherein a number of the continuous second polylines being equal to a number of the continuous first polylines as claimed, because providing corresponding seal ring polylines for the respective chip polylines maintains the seal ring along the entire peripheral configuration of the chip while preventing moisture from entering the chip and reducing destruction of the seal ring caused by cracking near the chip corner [0007-0008, 0034, 0038, 0055]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Furusawa in combination with Lin in view of Kuo, Yang, Rostoker, Mariani, and Chien due to the above reason.
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Chien (US 2014/0264710), Kuo (US 2010/0140749), and Yang (US 2014/0327151).
Regarding claim 21, Lin teaches a semiconductor device (70, Figure 3A, [0024]), comprising:
a first chip (an active die used in place of interposer 12, Figure 3A, [0019, 0024]); and
a second chip (18, Figure 3A, [0024]),
bonded over and electrically connected to the first chip (18 mechanically coupled over and electrically connected to the active die replacing 12, [0018]),
wherein from a top perspective of the semiconductor device (shown in Figures 3B and 6), the second chip (18 having the structure of die 90, Figures 3A-3B and 6, [0043]) includes a central region (92, Figure 6, [0029]) surrounded by a first seal ring (94, Figure 6, [0029]) extending continuously along a periphery of the second chip within the second chip (92 surrounded by 94 extending continuously along a periphery of 90(18) within 90(18), Figure 6).
Lin does not teach the semiconductor device comprising: the first seal ring has at least two turning points near a corner of the second chip.
Chien teaches a semiconductor device (FIG. 1, [0008]) comprising the first seal ring has at least two turning points near a corner of the second chip (seal ring 10 of the chip includes at least two turning points near the corner, FIGS. 3A-3F, [0022]).
As taught by Chien, one of ordinary skill in the art would utilize and modify the above teaching into Lin to obtain and achieve the semiconductor device comprising: the first seal ring has at least two turning points near a corner of the second chip as claimed, because forming the seal ring with multiple turning points conforming to the chip corner provides a smoother transition between adjacent sides of the seal ring, thereby reducing stress and charge concentration at the corner [0005, 0015]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Chien in combination with Lin due to the above reason.
Lin in view of Chien does not teach the semiconductor device wherein the central region of the second chip further comprises: a layer; a transistor disposed in the layer; at least one through silicon via (TSV) extending above the layer; and an interconnect structure disposed over the layer and including a conductive line and a conductive via electrically connecting to the transistor, and wherein the transistor, the TSV, and the interconnect structure are located in the central region surrounded by the first seal ring.
Kuo teaches a semiconductor device (3D package structure, FIG. 1, [0007]),
wherein the central region of the second chip (an internal region of 2 including circuit area 331, TSV 34, and connecting circuit 333, FIG. 3, [0024-0025]; hereinafter ‘2CR’) further comprises:
a layer (circuit area 331, FIG. 3, [0024]);
a transistor (transistor included in 331, [0025]; hereinafter ‘Tr’) disposed in the layer (Tr disposed in 331, FIG. 3);
at least one TSV (34, FIG. 3, [0024]) extending above the layer (34 extending above 331, FIG. 3); and
an interconnect structure (portions of connecting circuit 333 coupled to 331, FIG. 3, [0024]; hereinafter ‘IS’) disposed over the layer (IS disposed over 331, FIG. 3) and including a conductive line (horizontal metal layers of IS; hereinafter ‘IS-L’) and a conductive via (vertical interconnections of IS; hereinafter ‘IS-V’) electrically connecting to the transistor (IS-L and IS-V electrically connecting to Tr, FIG. 3, [0024-0025]) and
wherein the transistor, the TSV, and the interconnect structure are located in the central region (2CR) surrounded by the first seal ring (an outermost shelter 332 of a plurality of shelter structures surrounding internal semiconductor structures, [0030-0032]; hereinafter ‘332outer’; 2CR surrounded by 332outer).
As taught by Kuo, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Chien to obtain and achieve the semiconductor device wherein the central region of the second chip further comprises: a layer; a transistor disposed in the layer; at least one through silicon via (TSV) extending above the layer; and an interconnect structure disposed over the layer and including a conductive line and a conductive via electrically connecting to the transistor, and wherein the transistor, the TSV, and the interconnect structure are located in the central region surrounded by the first seal ring as claimed, because TSVs provide shorter interconnection routes between chips thereby increasing operating speed and improving package efficiency, and the surrounding shelter structures can be formed simultaneously with the connecting circuits using existing metal interconnect fabrication processes [0006-0007, 0032]. Further, it has been held that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Kuo in combination with Lin in view of Chien due to the above reason.
Lin in view of Chine and Kuo does not teach that the layer including the transistor in the second chip is an insulating layer and the TSV extends through the insulating layer.
Yang teaches a semiconductor device (100, FIG. 4, [0013]) wherein the second chip comprises an insulating layer (14 is insulating layer, [0017]) including a transistor (transistor 140, [0016, 0022]) and a TSV (25, [0022]) extending through the insulating layer (25 extending through 14, FIG. 4).
As taught by Yang, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Chine and Kuo to obtain and achieve the semiconductor device wherein the second chip comprises an insulating layer including a transistor and a TSV extending through the insulating layer as claimed, because the insulating layer electrically isolates conductive features associated with the transistor while accommodating a TSV extending through the layer for vertical electrical connection [0016-0019].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Yang in combination with Lin in view of Chine and Kuo due to the above reason.
Regarding claim 22, Lin in view of Chine, Kuo, and Yang teaches the semiconductor device of claim 21, further comprising
a third chip (Lin: 20, Figure 3A, [0024]),
bonded over the first chip (20 mechanically coupled over 12, Figure 3A, [0018]),
electrically connected to the first chip (20 electrically connected to 12, Figure 3A, [0018]) and
disposed adjacent to the second chip (20 disposed adjacent to 18, Figure 3A),
wherein from the top perspective (shown in Figures 3B and 6), the third chip (20 having the structure of die 90, Figures 3A-3B and 6, [0043]) includes
a second seal ring (94, Figure 6, [0029]) extending continuously along a periphery of the third chip within the third chip (94 extending continuously along a periphery of 90(20) within 90(20), Figure 6),
the third chip being disposed at a same level as the second chip over the first chip (20 disposed at the same level as 18 over 12, Figures 3A and 3B).
Regarding claim 23, Lin in view of Chine, Kuo, and Yang teaches the semiconductor device of claim 22, wherein
the first seal ring (Lin: 94 of 90(18), Figures 3B and 6) includes a first number of edges from the top perspective (a first number of edges, Figure 6),
the second seal ring (94 of 90(20), Figures 3B and 6) includes a second number of edges from the top perspective (a second number of edges, Figure 6), and
the second number is equal to or different from the first number (the second number is equal to the first number, Figure 6).
Regarding claim 24, Lin in view of Chine, Kuo, and Yang teaches the semiconductor device of claim 23, wherein the first number is equal to or greater than four (Lin: the first number is four, Figure 6).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2015/0125994) in view of Chien (US 2014/0264710), Kuo (US 2010/0140749), and Yang (US 2014/0327151) as applied claim 21 above, and further in view of Cadouri (US 2006/0278956).
Regarding claim 25, Lin in view of Chine, Kuo, and Yang teaches the semiconductor device of claim 21, Lin in view of Kuo, and Yang does not teach the semiconductor device wherein the first seal ring includes at least two turning points conformal to the corner.
Chien teaches the semiconductor device wherein the first seal ring includes at least two turning points conformal to the corner (seal ring 10 of the chip includes at least two turning points conformal to the corner, FIGS. 3A-3F, [0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Chien to obtain and achieve the semiconductor device wherein the first seal ring includes at least two turning points conformal to the corner as claimed, because forming the seal ring with multiple turning points conforming to the chip corner provides a smoother transition between adjacent sides of the seal ring, thereby reducing stress and charge concentration at the corner [0005, 0015]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Lin in view of Chine, Kuo, and Yang does not teaches the semiconductor device, wherein the second chip includes a corner having an interior angle greater than 90 degrees from the top perspective.
Cadouri teaches a semiconductor device (FIG. 3, [0013]) wherein the second chip includes a corner having an interior angle greater than 90 degrees from the top perspective (die 111 includes a corner having an interior angle greater than 90 degrees from the top perspective, FIG. 3, [0024]).
As taught by Cadouri, one of ordinary skill in the art would utilize and modify the above teaching into Lin in view of Chine, Kuo, and Yang to obtain and achieve the semiconductor device wherein the second chip includes a corner having an interior angle greater than 90 degrees from the top perspective as claimed, because forming a non rectangular die with a notched corner increases the distance between corners of adjacent dice at an intersection of saw streets, thereby providing additional space for sacrificial structures [0021-0024]. Further a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Cadouri in combination with Lin in view of Chine, Kuo, and Yang due to the above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Claims 1, 9, and 21
Applicant submits, page 3, “Therefore, Kuo explicitly discloses only one of the TSV and the circuit area 331 can be surrounded by the shelter 332 to prevent EMI on the circuit area 331 and thus teaches away from the recitations "a central region surrounded by a seal ring the central
region comprises an insulating layer, a transistor disposed in the insulating layer; at least
one through silicon via (TSV); and an interconnect structure wherein the transistor, the
TSV and the interconnect structure are located in the central region surrounded by the seal
ring" of the present disclosure” and
“the cited references either individually or in combination, fail to teach or suggest all the recitations cited in the amended Claims 1, 9 and 21”.
The examiner respectfully disagrees.
Applicant’s discussion of Kuo is directed to the localized shelter 332 shown in FIGS. 4 and 5. The rejection maps outer shelter 332outer shown in FIGS. 6, 8, 10, and 11 to the claimed seal ring. Outer shelter 332outer continuously surrounds a region including circuit area 331, TSV 34, and connecting circuit 333. Circuit area 331 includes semiconductor active components such as transistors, and connecting circuit 333 corresponds to the claimed interconnect structure [0025, 0029-0032].
Claim 1 does not require the seal ring to perform a particular sealing function or to comprise a particular material. Thus, the designation of Kuo’s surrounding structure as an “outer shelter” does not distinguish it from the claimed seal ring. Further, the rejection relies on the combined teachings of the cited references, rather than Yamada or Lin individually, for the claimed semiconductor device. Accordingly, applicant’s arguments do not overcome the rejection of claims 1, 9, and 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that You et al. (US 2022/0037521), Yu et al. (US 2016/0240439), Farooq et al. (US 2015/0069609), and Yang et al. (US 2016/0365318) as a semiconductor device having a seal ring structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/28/26
