Listed by the USPTO as OH, JIYOUNG
Tech Center 2800 • Art Units: 2818
This examiner grants 76% of resolved cases
OH, JIYOUNG has resolved 46 cases in Tech Center 2800 and Art Unit 2818. The allowance rate is 76.1%, the interview lift is 15.8%, and the median time to allowance is 1283 days. The allowance rate indicates a favorable resolved record, while the positive interview lift identifies an additional opportunity for prosecution engagement. The smaller case volume supports measured use of the figures in forecasting.
The principal companies are Taiwan Semiconductor Manufacturing Company, Ltd., Samsung Electronics Co., Ltd., and Intel Corporation. The leading firms are CONLEY ROSE, P.C., FISH & RICHARDSON P.C. (TC), and CANTOR COLBURN LLP. These participants provide technology and counsel context for matters handled in Art Unit 2818.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 17799076 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENTS AND METHOD OF MANUFACTURING SAME | Non-Final OA | LG ELECTRONICS INC. |
| 18534997 | CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR STRUCTURE | Final Rejection | SAMSUNG ELECTRONICS CO., LTD. |
| 18138192 | METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18193758 | SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 17968371 | DISPLAY DEVICE HAVING METAL LAYER WITH PROTRUDING PARTS AND RECESSED PARTS | Non-Final OA | Samsung Display Co., LTD. |
| 18712703 | CHIP STRUCTURE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY APPARATUS | Non-Final OA | BOE TECHNOLOGY GROUP CO., LTD. |
| 17855639 | CONTACT ARCHITECTURE FOR 2D STACKED NANORIBBON TRANSISTOR | Non-Final OA | Intel Corporation |
| 17308853 | METAL OXIDE THIN FILM TRANSISTORS WITH MULTI-COMPOSITION GATE DIELECTRIC | Final Rejection | Intel Corporation |
| 18508706 | POWER SEMICONDUCTOR DEVICE | Final Rejection | HYUNDAI MOBIS CO., LTD. |
| 18810032 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE | Non-Final OA | Murata Manufacturing Co., Ltd. |
| 18580785 | SILICON CARBIDE SEMICONDUCTOR DEVICE | Final Rejection | SUMITOMO ELECTRIC INDUSTRIES, LTD. |
| 18194126 | POST-LASER DICING WAFER-LEVEL TESTING | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18508541 | REDUCED GATE EDGE CAPACITANCE | Final Rejection | International Business Machines Corporation |
| 17957194 | HYBRID INSERTED DIELECRIC GATE-ALL-AROUND DEVICE | Non-Final OA | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 18635649 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME | Non-Final OA | SK hynix Inc. |
| 18788538 | PHASE CHANGE RANDOM ACCESS MEMORY (PCRAM) DEVICE WITH INCREASED PACKING DENSITY AND METHOD OF MAKING SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18304350 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 17819482 | POWER VIAS FOR BACKSIDE POWER DISTRIBUTION NETWORK | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 17817249 | SEMICONDUCTOR DEVICE WITH POLYGONAL PROFILES FROM THE TOP VIEW AND METHOD FOR FORMING THE SAME | Non-Final OA | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
| 17858971 | SEMICONDUCTOR PACKAGE WITH INTEGRATED CIRCUIT CHIP COUPLERS | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18775995 | SEMICONDUCTOR DEVICE WITH DOPED REGION DIELECTRIC LAYER | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 17816782 | Trimming Through Etching in Wafer to Wafer Bonding | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy76.1% of resolved applications examined by Jiyoung Oh were allowed (46 resolved cases), compared with 85.2% across Art Unit 2818 over the last five years.
This examiner's interview lift is +15.8 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Jiyoung Oh took 1,283 days on average from filing to allowance.
Jiyoung Oh examines applications in Art Unit 2818 in Tech Center 2800 (Semiconductors, Circuits & Optics).
