Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/29/2026 has been entered.
Acknowledgment
Response filed on 01/29/2026 has been entered. Applicant has amended claims 1 and 10. Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant asserts regarding the 103 combinations of Loy in view of Nardi:
“Nardi teaches an annular cavity that "laterally surrounds the resistive memory material portion 214 for each resistive memory element 180" (see column 12 lines 11-13 of Nardi). Based on the Examiner's combinations of Loy and Nardi, or Loy, Nardi, and Horii, one of ordinary skill in the art, upon reading the disclosure of Nardi, would have been guided to put an annular cavity to surround a resistive memory element in Loy or Loy in combination with Horii. In other words, any resistive memory element would likely be in the center of the annulus of such a cavity. The modification proposed by the Examiner would have resulted in a portion of the annular cavity that fails to be fully bounded by at least the first bottom electrode, the second bottom electrode, and the switching layer. Furthermore, the switching layer would not have been fully positioned over the cavity. For example, an annular cavity surrounding the switching layer 110 in Loy would likely have a portion that ends up between the switching layer 110 and the mask element 108 in Loy, and that very portion would not be bounded by any "bottom electrode". Additionally, the switching layer 110 would not have been fully positioned over that portion of the annular cavity, i.e., the annular cavity would have been positioned over and below the switching layer 110 of Loy”.
Examiner’s response:
Examiner agrees with this assertion. Hence, the prior rejection has been withdrawn. However, an updated search was performed and resulted in a new prior art Philip et al. (US 20230093026 A1) which teaches (figs. 5A-5C, wherein fig. 5C is the final structure) a variable resistance memory device comprising: a cavity (320c, 320d) defined laterally between a first dielectric pillar 310 and a second dielectric pillar 310, wherein the cavity (320c, 320d) includes gas (¶54).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to include a gas filled cavity as disclosed by Philip in the memory device of Loy, to concentrate heat produced by a reset current and to mitigate an amount of heat that escapes from the variable resistance material (¶16 of Philip).
Therefore, the rejections for claims 1-20 stand.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 rejected under 35 U.S.C. 103 as being unpatentable over Loy et al. US 20210020834 (hereinafter Loy) in view of Philip et al. (US 20230093026 A1; hereinafter “Philip”).
Regarding claim 1, Loy discloses (fig. 3) a resistive memory device comprising:
a first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) having an upper surface (near 102 ta, ¶29);
a second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32) adjacent to the first dielectric pillar, the second dielectric pillar having an upper surface (near 102 tc, Loy ¶29);
a first bottom electrode (112, 120, and 116, Loy ¶30-34) having a top segment (112) on the upper surface of the first dielectric pillar (128 left portion), the top segment of the first bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a first bottom electrode top edge (top of 112 in inverted view, fig. 3);
a second bottom electrode (114, 122, and 118, Loy ¶30-34) having a top segment (114) disposed on the upper surface of the second dielectric pillar (128 right portion), the top segment of the second bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a second bottom electrode top edge (top of 114 in inverted view, fig. 3);
a switching layer (110, Loy ¶29-30, 33-35) laterally between the first bottom electrode (112, 120, and 116) and the second bottom electrode (114, 122, and 118), the switching layer is in direct contact with the first bottom electrode top edge (top of 112 in inverted view, fig. 3) and the second bottom electrode top edge (top of 114 in inverted view, fig. 3); and
a cavity (128 below 108, Loy ¶28-30; hereinafter “CV”; also see fig. 3 annotated below) defined laterally between the first dielectric pillar and the second dielectric pillar,
the cavity CV is fully bounded by at least the first bottom electrode (112, 120, and 116), the second bottom electrode (114, 122, and 118), and the switching layer (110),
wherein the switching layer is fully positioned over the cavity (128 between 116 and 118) (inverted view fig. 3 annotated below).
Loy does not disclose wherein the cavity includes gas.
In the same field of endeavor, Philip discloses (figs. 5A-5C, wherein fig. 5C is the final structure) a variable resistance memory device comprising: a cavity (320c, 320d) defined laterally between a first dielectric pillar 310 and a second dielectric pillar 310, wherein the cavity (320c, 320d) includes gas (¶54).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to include a gas filled cavity as disclosed by Philip in the memory device of Loy, to concentrate heat produced by a reset current and to mitigate an amount of heat that escapes from the variable resistance material (¶16 of Philip).
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Regarding claim 2, Loy in view of Philip discloses the resistive memory device of claim 1,
wherein the first bottom electrode top edge and the second bottom electrode top edge form overhangs extending over the cavity (112 and 114 extend inward beyond 120 and 122 above the cavity 128 below 108, fig. 3 Loy ¶30-34).
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Regarding claim 3, Loy in view of Philip discloses the resistive memory device of claim 1,
further comprising a top electrode (302, Loy ¶44) positioned on the switching layer (110, Loy ¶29-30, 33-35).
Regarding claim 4, Loy in view of Philip discloses the resistive memory device of claim 3,
wherein the top electrode (302, Loy ¶44) includes a bottom surface (Loy fig. 3) and a protrusion (124 and 126, Loy ¶34, 52-53) extending from the bottom surface of the top electrode (302) into the switching layer (110, Loy ¶29-30, 33-35).
Regarding claim 5, Loy in view of Philip discloses the resistive memory device of claim 4,
wherein the switching layer (110, Loy ¶29-30, 33-35) and the top electrode (302, Loy ¶44) extend laterally (Loy fig. 3) over the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) and the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32).
Regarding claim 6, Loy in view of Philip discloses the resistive memory device of claim 1,
wherein the switching layer (110, Loy ¶29-30, 33-35) extends laterally (Loy fig. 3) over the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) and the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32).
Regarding claim 7, Loy in view of Philip discloses the resistive memory device of claim 1,
wherein the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) has side surfaces, the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32) has side surfaces, the first bottom electrode (112, 120, and 116, Loy ¶30-34) has a bottom segment (116) on the side surfaces of the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32), and the second bottom electrode (114, 122, and 118, ¶30-34) has a bottom segment (118) of the side surfaces of the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32).
Regarding claim 8, Loy in view of Philip discloses the resistive memory device of claim 1,
further comprising an interlayer dielectric below the first dielectric pillar and the second dielectric pillar, wherein the first dielectric pillar and the second dielectric pillar are integrally formed with the interlayer dielectric (Loy ¶41-42, where dielectric layer 128 is formed by depositing insulating material over the switching element and electrodes, then smoothing the surface).
Regarding claim 9, Loy in view of Philip discloses the resistive memory device of claim 1,
wherein the side surface of the top segment of the first bottom electrode (112, 120, and 116, Loy ¶30-34) forms an acute angle with the upper surface of the top segment (112) of the first bottom electrode and the side surface of the top segment of the second bottom electrode (114, 122, and 118, ¶30-34) forms an acute angle with the upper surface of the top segment of the second bottom electrode (Loy ¶29, where an angle between the second portion 110 b and the third portion 110 c may range from about 85 degrees to about 95 degrees and Loy ¶30 discloses top segments of bottom electrodes 112, 114 are in contact with these portions of the switching layer).
Claims 10-20 rejected under 35 U.S.C. 103 as being unpatentable over Loy in view of Horii et al. US PGPUB 20180047899 (hereinafter Horii) and Philip et al. (US 20230093026 A1; hereinafter “Philip”).
Regarding claim 10, Loy discloses (fig. 3) a resistive memory device comprising:
a first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) having an upper surface (near 102 ta, ¶29);
a second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32) adjacent to the first dielectric pillar, the second dielectric pillar having an upper surface (near 102 tc, Loy ¶29);
a first bottom electrode (112, 120, and 116, Loy ¶30-34) having a top segment (112), the top segment of the first bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a first bottom electrode top edge (top of 112 in inverted view, fig. 3);
a second bottom electrode (114, 122, and 118, Loy ¶30-34) having a top segment (114), the top segment of the second bottom electrode includes an upper surface and a side surface, the side surface of the top segment meets the upper surface of the top segment to provide a second bottom electrode top edge (top of 114 in inverted view, fig. 3);
a switching layer (110, Loy ¶29-30, 33-35) laterally between the first bottom electrode (112, 120, and 116) and the second bottom electrode (114, 122, and 118), the switching layer is in direct contact with the first bottom electrode top edge (top of 112 in inverted view, fig. 3) and the second bottom electrode top edge (top of 114 in inverted view, fig. 3); and
a cavity (128 below 108, Loy ¶28-30) defined laterally between the first dielectric pillar and the second dielectric pillar, the cavity is fully bounded by at least the first bottom electrode (112, 120, and 116), the second bottom electrode (114, 122, and 118), and the switching layer (110), wherein the switching layer is fully positioned over the cavity (128 between 116 and 118) (inverted view fig. 3).
Loy does not disclose a first dielectric cap on the upper surface of the first dielectric pillar; a second dielectric cap on the upper surface of the second dielectric pillar;
a first bottom electrode having a top segment covering the first dielectric cap, and
a second bottom electrode having a top segment covering the second dielectric cap.
In the same field of endeavor, Horii discloses (figs. 25-27) a dielectric cap (300, Horii ¶83-84) formed over dielectric pillars (152 and 192, Horii ¶83). It would have been obvious to one of ordinary skill in the art at the time of filing to use a dielectric cap over the dielectric pillar as disclosed by Horii in the device of Loy resulting in the left and right regions of 128 in fig. 3 of Loy to include a dielectric cap, improving device performance by tuning the dielectric properties near the interface of the electrode and switching element.
Loy in view of Horii does not disclose wherein the cavity includes gas.
In the same field of endeavor, Philip discloses (figs. 5A-5C, wherein fig. 5C is the final structure) a variable resistance memory device comprising: a cavity (320c, 320d) defined laterally between a first dielectric pillar 310 and a second dielectric pillar 310, wherein the cavity (320c, 320d) includes gas (¶54).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to include a gas filled cavity as disclosed by Philip in the memory device of Loy as modified by Horii, to concentrate heat produced by a reset current and to mitigate an amount of heat that escapes from the variable resistance material (¶16 of Philip).
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Regarding claim 11, Loy in view of Horii and Philip discloses the resistive memory device of claim 10,
wherein the first bottom electrode top edge and the second bottom electrode top edge form overhangs extending over the cavity (112 and 114 extend inward beyond 120 and 122 above the cavity 128 below 108, fig. 3 Loy ¶30-34).
Regarding claim 12, Loy in view of Horii and Philip discloses the resistive memory device of claim 10,
wherein the first dielectric cap includes an upper surface and a side surface, the side surface of the first dielectric cap forms an acute angle with the upper surface of the first dielectric cap, and the second dielectric cap includes an upper surface and a side surface, the side surface of the second dielectric cap forms an acute angle with the upper surface of the second dielectric cap (Loy ¶29, where an angle between the second portion 110 b and the third portion 110 c may range from about 85 degrees to about 95 degrees and Loy ¶30 discloses top segments of bottom electrodes 112, 114 are in contact with these portions of the switching layer, and Loy ¶41-42, where dielectric layer 128 is formed by depositing insulating material over the switching element and electrodes, resulting in the dielectric cap in 128 of Loy as modified by Horii to also have this angle).
Regarding claim 13, Loy in view of Horii and Philip discloses the resistive memory device of claim 12,
wherein the first bottom electrode (112, 120, and 116, Loy ¶30-34) has a bottom segment (116) on the side surface of the first dielectric cap (128 left portion in an inverted view, Loy fig. 3 ¶32 as modified to be a cap by Horii) and the second bottom electrode (114, 122, and 118, ¶30-34) has a bottom segment (118) of the side surface of the second dielectric cap (128 right portion in an inverted view, Loy fig. 3 ¶32 as modified to be a cap by Horii).
Regarding claim 14, Loy in view of Horii and Philip discloses the resistive memory device of claim 13,
wherein the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) has side surfaces, the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32) has side surfaces, the first bottom electrode (112, 120, and 116, Loy ¶30-34) has a bottom segment (116) on the side surfaces of the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32), and the second bottom electrode (114, 122, and 118, ¶30-34) has a bottom segment (118) of the side surfaces of the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32).
Regarding claim 15, Loy in view of Horii and Philip discloses the resistive memory device of claim 10,
further comprising a top electrode (302, Loy ¶44) positioned on the switching layer (110, Loy ¶29-30, 33-35).
Regarding claim 16, Loy in view of Horii and Philip discloses the resistive memory device of claim 15,
wherein the top electrode (302, Loy ¶44) includes a bottom surface (Loy fig. 3) and a protrusion (124 and 126, Loy ¶34, 52-53) extending from the bottom surface of the top electrode (302) into the switching layer (110, Loy ¶29-30, 33-35).
Regarding claim 17, Loy in view of Horii and Philip discloses the resistive memory device of claim 16, wherein the switching layer (110, Loy ¶29-30, 33-35) and the top electrode (302, Loy ¶44) extend laterally (Loy fig. 3) over the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) and the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32).
Regarding claim 18, Loy in view of Horii and Philip discloses the resistive memory device of claim 10,
wherein the switching layer (110, Loy ¶29-30, 33-35) extends laterally (Loy fig. 3) over the first dielectric pillar (128 left portion in an inverted view, Loy fig. 3 ¶32) and the second dielectric pillar (128 right portion in an inverted view, Loy fig. 3 ¶32).
Regarding claim 19, Loy in view of Horii and Philip discloses the resistive memory device of claim 10,
further comprising an interlayer dielectric below the first dielectric pillar and the second dielectric pillar, wherein the first dielectric pillar and the second dielectric pillar are integrally formed with the interlayer dielectric (Loy ¶41-42, where dielectric layer 128 is formed by depositing insulating material over the switching element and electrodes, then smoothing the surface).
Regarding claim 20, Loy in view of Horii and Philip discloses the resistive memory device of claim 10,
wherein the side surface of the top segment of the first bottom electrode (112, 120, and 116, Loy ¶30-34) forms an acute angle with the upper surface of the top segment (112) of the first bottom electrode, and the side surface of the top segment of the second bottom electrode (114, 122, and 118, ¶30-34) forms an acute angle with the upper surface of the top segment (114) of the second bottom electrode (Loy ¶29, where an angle between the second portion 110 b and the third portion 110 c may range from about 85 degrees to about 95 degrees and Loy ¶30 discloses top segments of bottom electrodes 112, 114 are in contact with these portions of the switching layer).
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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