DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 25, 2026, has been entered.
Response to Arguments
New ground(s) of rejection is made in light of the amended claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-7, 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mohr et al. (US 20190045639 A1) in view of Kim et al. (US 20220304147 A1)
Regarding Claim 1 - Regarding Claim 1 – Mohr teaches a component carrier (Shown in annotated Fig 9B below) comprising a stack (shown in Fig 9B) with at least one electrically conductive layer structure (shown in Fig 9B; 901/903/905) and at least one electrically insulating layer structure (shown in Fig 9B; 902/904), the stack of the component carrier, comprising: at least one central stack section (shown in Fig 9B); and at least one vertical opening formed in the cavity stack section (shown in Fig 9B); wherein the cavity stack section at least partially surrounds the central stack section (shown in Fig 9B); and wherein the thickness of the central stack section is larger than the thickness of the cavity stack section(shown in Fig 9B); wherein a component is embedded in or mounted on the component carrier (Fig 9B; Mohr [0074]); and wherein the component carrier is a laminate-type component carrier comprising multiple layer structures (Fig 9B; Mohr [0017]).
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Mohr does not explicitly disclose at least one cavity stack section arranged with a through connection.
Kim teaches at least one cavity stack section arranged with a through connection (shown in annotated Fig 24).
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It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Mohr with at least one cavity stack section arranged with a through connection as taught by Kim because Kim [0311] expressly states “vias 441, 442, 443, 444, 445, 446, 446, 448, and 449 for electrically connecting circuit patterns disposed on different layers may be disposed in each insulating layer” and that such vias “may be disposed through each insulating layer, thereby, circuit patterns disposed on the surfaces of different insulating layers may be electrically connected to each other”.
Regarding Claim 2 – Mohr in view of Kim teaches the component carrier according to claim 1, wherein the central stack section is arranged between at least two cavity stack sections (Mohr Fig 9B); wherein a portion of one of the cavity stack sections arranged between the at least one central stack section and the at least one vertical opening includes at least one vertical through connection (Kim Fig 24).
Regarding Claim 3 – Mohr in view of Kim teaches the component carrier according to claim 1, wherein the at least one vertical opening is at least partially void (shown in Mohr Fig 9B).
Regarding Claim 6 – Mohr in view of Kim teaches the component carrier according to claim 1, further comprising at least one of the following features: wherein the at least one electrically conductive layer structure comprises a plurality of vertical through connections extending through the central stack section to an external surface of the central stack section (Figs 9A, 9B; Mohr [0071] states “three vias (906, 908, 910) defined in the layers of electrical insulation (902, 904)… blind vias that are exposed to one side of the PCB”; Mohr [0072] states “leave a portion… to form two… vias (906, 908)… filled… to form two separate barrels (907, 909)” and Mohr [0073] states “leave a portion… to form the third of the three vias (910)… to form a third barrel (911)” Accordingly Mohr teaches a plurality of vertical connections i.e. vias with barrels that terminate at an external surface i.e. blind vias exposed to one side); wherein the at least one electrically conductive layer structure comprises a plurality of vertical through connections extending through the cavity stack section[[,]] to an external surface of the cavity stack section.
Regarding Claim 7 – Mohr in view of Kim teaches the component carrier according to claim 1, wherein a portion of the cavity stack section furthest removed from the central stack is free of vertical through connections. (shown in Mohr Fig 9B).
Regarding Claim 9 – Mohr in view of Kim teaches the component carrier according to claim 1, wherein the component carrier is configured as one of the group which consists of a printed circuit board and a substrate (Fig 9B; Mohr [0074]).
Regarding Claim 10 – Mohr teaches an arrangement, comprising: a component carrier including a stack (Shown in annotated Fig 9B above); wherein the stack of the component carrier has at least one central stack section (shown in Fig 9B), and at least one vertical opening formed in the cavity stack section (shown in Fig 9B); wherein the cavity stack section at least partially surrounds the central stack section (shown in Fig 9B); and wherein the thickness of the central stack section is larger than the thickness of the cavity stack section (shown in Fig 9B); wherein a component is embedded in or mounted on the component carrier (Fig 9B; Mohr [0074]), wherein at least a part of the electronic element extends through at least part of the at least one vertical opening (Fig 9B; Mohr [0074]); and wherein the component carrier is a laminate-type component carrier comprising multiple layer structures (Fig 9B; Mohr [0017]).
Mohr does not explicitly disclose at least one cavity stack section with at least one through connection.
Kim teaches at least one cavity stack section with at least one through connection (shown in Fig 24).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Mohr with at least one cavity stack section with at least one through connection as taught by Kim because Kim [0311] expressly states “vias 441, 442, 443, 444, 445, 446, 446, 448, and 449 for electrically connecting circuit patterns disposed on different layers may be disposed in each insulating layer” and that such vias “may be disposed through each insulating layer, thereby, circuit patterns disposed on the surfaces of different insulating layers may be electrically connected to each other”.
Regarding Claim 11 – Mohr in view of Kim teaches the arrangement according to claim 10, wherein the electronic element is not integrally formed with the component carrier (Fig 9B, Mohr [0074]).
Regarding Claim 12 – Mohr in view of Kim teaches the arrangement according to claim 10, wherein the electronic element is physically separate from the component carrier (Fig 9B; Mohr [0074]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mohr et al. (US 20190045639 A1) in view of Kim et al. (US 20220304147 A1) and in further view of Elenga et al. (US 20150076929 A1)
Regarding Claim 4 – Mohr in view of Kim teaches the component carrier according to claim 1, but fails to teach wherein the component carrier further comprises: a functional coating layer covering at least one vertical side wall delimiting the vertical opening.
Elenga teaches a functional coating layer covering at least one vertical side wall delimiting the vertical opening (Fig 5, Elenga [0060] states “the side of the opening is coated with a low friction coating such as teflon.” This is done so as to allow a component to be inserted more freely in to the opening).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the component carrier as taught by Mohr in view of Kim with a functional coating layer covering at least one vertical side wall delimiting the vertical opening as taught by Elenga, since, this would allow for easier insertion of the camera, which is not attached to the substrate, into the substrate of Mohr.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mohr et al. (US 20190045639 A1) in view of Kim et al. (US 20220304147 A1) and in further view of Weichslberger et al. (US 20110272177 A1)
Regarding Claim 4 – Mohr in view of Kim teaches the component carrier according to claim 1, but fails to teach wherein the component carrier further comprises: a functional coating layer covering at least one vertical side wall delimiting the vertical opening.
Weichslberger teaches a functional coating layer covering at least one vertical side wall delimiting the vertical opening (Fig 5, Weichslberger [0048] states “an adhesion-preventing material according to the invention is provided or applied in the region of… the milling edges”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the component carrier as taught by Mohr in view of Kim with a functional coating layer covering at least one vertical side wall delimiting the vertical opening as taught by Weichslberger because Weichslberger [0073] states “The removal of the adhesion-preventing layer, moreover, enables the attachment of electronic components as well as mechanical parts… in the thus produced cavity, and the thermal or electrical or thermal and electrically conductive connection of the same.”
Regarding Claim 5 – Mohr in view of Weichslberger teaches the component carrier according to claim 1, wherein the functional coating layer comprises at least one of the following features: wherein the functional coating layer comprises a black coating; wherein the functional coating layer has a thickness of 25 μm or less (Weichslberger [0098] states “the adhesion-preventing material 8 is applied in a layer thickness of less than 25 μm”); wherein the functional coating layer is configured to prevent light scattering or wherein the functional coating layer is configured to enhance light scattering; wherein the functional coating layer is optically opaque or transparent; wherein the functional coating layer is electrically insulating or electrically conductive; wherein the functional coating layer is magnetic or non-magnetic; wherein the protective coating layer is anticorrosive.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mohr et al. (US 20190045639 A1) in view of Kim et al. (US 20220304147 A1) and in further view of Gottwald et al. (US 20130329370 A1)
Regarding Claim 8 – Mohr in view of Kim teaches the component carrier according to claim 1, but fails to teach wherein an angle between one vertical side wall delimiting the vertical opening and a first main surface of the cavity stack section is in the range between 80° and 100°.
Gottwald teaches an angle between one vertical side wall delimiting the vertical opening and a first main surface of the cavity stack section is in the range between 80° and 100° (Gottwald [0022] states “the cutout has right angles and vertical surfaces”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the component carrier as taught by Mohr in view of Kim wherein an angle between one vertical side wall delimiting the vertical opening and a first main surface of the cavity stack section is in the range between 80° and 100° as taught by Gottwald to get the benefit of manufacturing advantage as shown in paragraph [0022].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mohr et al. (US 20190045639 A1) in view of Kim et al. (US 20220304147 A1) in further view of Hashimoto (US 20050040510 A1)
Regarding Claim 13 – Mohr in view of Kim teaches the arrangement according to claim 10, but fails to teach wherein the electronic element is an optical element.
Hashimoto teaches the electronic element is an optical element (Hashimoto [0137] states “examples of electronic components fabricated by using such electronic elements include optical elements”)
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the arrangement as taught by Mohr in view of Kim with the electronic element is an optical element as taught by Hashimoto because Hashimoto [0137] states “electronic elements (either active elements or passive elements) can be mounted on a substrate to fabricate an electronic component, in a manner similar to that of semiconductor chips”
Conclusion
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/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847