Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/6/2026 has been entered.
Status of Claims
The following is in response to the communication filed 2/6/2026.
Claims 1, 3-8, 10, 11, 14, 15, 19-26 are currently pending.
Claims 1, 5, 6, 8, 11, 14, 15, and 25 have been amended.
Claims 11, 14, and 15 have been withdrawn.
Claims 2, 9, 12, 13, 16, and 17 have previously been canceled.
Claim 26 is new.
Claims 1, 3-8, 10, and 19-26 have been examined.
Response to Arguments
Applicant’s arguments, see starting on page 10, filed 2/06/2026, in conjunction with the examiner initiated interview with Sherry Gourlay (Reg. No. 39422) on 2/26/2026 with respect to Claims 1 and 26 regarding the language “the first elongated cooling trench is not configured to convey current from the first current terminal to the backside of the semiconductor substrate, and the first elongated cooling trench is not configured to be in electrical communication with the backside of the semiconductor substrate” have been fully considered and are persuasive. In particular the language is understood to describe a horizontal HEMT device and not a vertical device as described in the Moens. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chang et. al US 20180212047 A1. See below for more detail.
Claims 11, 14, 15, have been amended but not been substantively reviewed in light of the fact that these claims are currently withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, 8, 10, 19-22, 24 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et. al US 20180212047 A1 (hereinafter Chang).
Annotated Fig. 6E will be used in discussion with some claims.
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Regarding Claim 1, Chang discloses:
A transistor(Fig. 1L, a group III-V device 100.) comprising:
a semiconductor substrate having a top surface and a backside; (Fig. 1L, substrate 102.)
a first current terminal that has a first contact, wherein the first current terminal is selected from one of a source terminal and a drain terminal; (See Fig. 1L, a source electrode 162.)
a second current terminal that has a second contact, wherein the second current terminal is selected from another one of the source terminal and the drain terminal; (See Fig. 1L, drain electrode 164.)
a semiconductor heterostructure (Fig. 1L, active layer 130, channel layer 120, buffer layer 110, transition layer 106, and nucleation layer 104.) including a channel region formed on the top surface of the semiconductor substrate, (The channel layer 120 is formed on the substrate 102.) wherein the semiconductor heterostructure has a top surface, (The heterostructure has a top surface at the top of the active layer 130.) wherein the first and second contacts are supported by and located at the top surface of the semiconductor heterostructure, (The source electrode 162 and drain electrode 164 are at the top surface of the active layer 130.) and wherein the channel region is configured to provide an electrically conductive path between the first current terminal and the second current terminal; (The channel region 120 provides a conductive path between the source and drain electrodes.)
an elongated gate electrode (gate electrode 166) at the top surface of the semiconductor heterostructure between the first and second contacts, wherein the gate electrode extends laterally from a first end of the gate electrode to a second end of the gate electrode in a first direction that is parallel to the top surface of the semiconductor substrate; and (See Fig. 1L.)
a first elongated cooling trench coupled to the first current terminal, (Fig. 1L, via structure 150 coupled to source electrode 162.) wherein the first elongated cooling trench extends laterally from a first end of the first elongated cooling trench to a second end of the first elongated cooling trench along the first direction, and the first elongated cooling trench also extends vertically from the first current terminal through the channel region and through the semiconductor heterostructure, through the top surface of the semiconductor substrate and toward, but not to, the backside of the semiconductor substrate; (See Fig. 1L, via structure 150 has a horizontal and vertical direction and does not extend to the backside of the substrate 102.)
wherein the first elongated cooling trench is filled throughout with a thermally- conductive material configured to dissipate heat from the channel region into the semiconductor substrate, (See Fig. 1L, [0037], via structure 150 includes tungsten which is configured to dissipate heat.) the first elongated cooling trench is not configured to convey current from the first current terminal to the backside of the semiconductor substrate, and the first elongated cooling trench is not configured to be in electrical communication with the backside of the semiconductor substrate. (Fig. 1L is a horizontal HEMT device therefore there is no intentional electrical communication between the via structure 150 and the backside of the substrate 102.)
Regarding claim 3, Chang further discloses:
wherein the thermally-conductive material of the first elongated cooling trench is a metal. ([0037], via structure 150 includes tungsten in the conductive structure 154.)
Regarding claim 5, Chang discloses:
A transistor (Fig. 6E, a group III-V device 600.) comprising:
a semiconductor substrate having a top surface and a backside; (Fig. 6E, substrate 102)
a source terminal that has a first contact; (See annotated Fig. 6E, a source electrode 162 and conductive layer 566a.)
a drain terminal that has a second contact; (See annotated Fig. 6E, drain electrode 164 and conductive layer 566b.)
a semiconductor heterostructure (Fig. 6E, active layer 130, channel layer 120, buffer layer 110, transition layer 106, and nucleation layer 104.) including a channel region formed on the top surface of the semiconductor substrate, (The channel layer 120 is formed on the substrate 102.) wherein the semiconductor heterostructure has a top surface, (The source electrode 162 and drain electrode 164 are at the top surface of the active layer 130.) wherein the source and drain contacts are supported by and located at the top surface of the semiconductor heterostructure, (The source electrode 162 and drain electrode 164 are at the top surface of the active layer 130.) and wherein the channel region is configured to provide an electrically conductive path between the source terminal and the drain terminal; (The channel region 120 provides a conductive path between the source and drain electrodes.)
an elongated gate electrode (gate electrode 166) at the top surface of the semiconductor heterostructure between the source and drain contacts, wherein the gate electrode extends laterally from a first end of the gate electrode to a second end of the gate electrode in a first direction that is parallel to the top surface of the semiconductor substrate; (See Fig. 6E.)
a first elongated cooling trench (annotated Fig. 6E, via structure 150a on the left side of the device) coupled to the source terminal (in direct contact with 566a), wherein the first elongated cooling trench extends laterally from a first end of the first elongated cooling trench to a second end of the first elongated cooling trench along the first direction, and the first elongated cooling trench also extends vertically from the source terminal through the channel region and through an entire thickness of the semiconductor heterostructure, through the top surface of the semiconductor substrate and toward, but not to, the backside of the semiconductor substrate; and (See Fig. 6E.)
a second elongated cooling trench(annotated Fig. 6E, via structure 150b on the right side of the device) coupled to the drain terminal (in direct contact with 566a), wherein the second elongated cooling trench extends laterally from a first end of the second elongated cooling trench to a second end of the second elongated cooling trench along the first direction, and the second elongated cooling trench also extends vertically from the drain terminal through the channel region and through the entire thickness of the semiconductor heterostructure, through the top surface of the semiconductor substrate and toward, but not to, the backside of the semiconductor substrate, (See Fig. 6E.)
wherein the first and second elongated cooling trenches are filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate. (See Fig. 6E, [0037], conductive layer 154 includes tungsten which is configured to dissipate heat.)
Regarding claim 8, Chang further discloses:
wherein the transistor is a high electron- mobility transistor (HEMT) (Chang, [0003], III-V devices such as described can be used for HEMTs.) and the channel region comprises the semiconductor heterostructure, ([0017], the channel is heterojunction.) which is configured to form a two-dimensional electron gas (2DEG) at a buried semiconductor heterojunction within the semiconductor heterostructure between the top surface of the channel region and the top surface of the semiconductor substrate. ([0031], the active layer 120 over the channel layer causes a 2DEG to be formed in the channel layer 120.)
Regarding claim 10, Chang further discloses:
wherein, when the transistor is biased in an on state in which electrical current flows between the first current terminal and the second terminal via the channel region, at least a portion of the electrical current flows from the first current terminal to the channel region through the first elongated cooling trench. (Chang, [0032] the device is a in an on state that would have current flow from the first current terminal to the second through via the channel region and as the via structure is connected to the first current terminal it would by necessity have a portion of the current flowing from the via structure.)
Regarding claim 19, Chang further discloses:
the first elongated cooling trench is directly physically coupled to the first current terminal. (Chang, Fig. 1L via structure 150 is directly and physically coupled to source electrode 162.)
Regarding claim 20, Chang further discloses:
the first contact is formed from an electrically-conductive material (Fig. 1L, source electrode 162, [0040] is made with titanium (Ti).) that is different from the thermally-conductive material of the first elongated cooling trench. (via structure 150 includes conductive layer 154 which is made of tungsten (W) which is different from titanium (Ti).)
Regarding claim 21, Chang further discloses:
wherein the thermally-conductive material of the first elongated cooling trench is a solid mass that provides a high thermal conductivity path from the channel region to the semiconductor substrate. ([0037] the conductive layer 154 can be a deposited material and is shown in Fig. 1L as a solid mass which would by necessity provide a thermal conductive path as the material has conductive properties. – Note on claim interpretation: the term “high” in “high thermal conductivity” is not given a particular weight as the specification does not give particle range or value as to denote what the high represents.)
Regarding claim 22, Chang further discloses:
wherein the thermally-conductive material of the first elongated cooling trench includes multiple layers. (Fig. 1L, via structure 150 includes both conductive layer 154 and diffusion barrier 152, therefore is by necessity multiple layers.)
Regarding claim 24, Chang further discloses:
the thermally-conductive material of the first elongated cooling trench includes one or more materials selected from a group consisting of gold, tungsten, copper, aluminum, titanium, and alloys thereof. ([0037], the conductive layer is made of tungsten.)
Regarding claim 25, Chang further discloses:
wherein the first elongated cooling trench extends to a depth of at least 100 nanometers beyond the top surface of the semiconductor substrate. (See, Fig. 1L, [0026], via structure 150 is shown to pass through the buffer layer 110 which is at least .5 micrometers ( 500nm) therefore the depth would be greater than 100 nanometers.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 1 above, and further in view of Radulescu et al. US 20230075505 A1. (hereinafter Radulescu)
Regarding claim 4, Chang discloses all the elements of claim 1 above.
Chang does not appear to disclose “further comprising a backside metallization layer on the backside of the semiconductor substrate” and “wherein the first elongated cooling trench does not physically contact the backside metallization layer.”
Radulescu, which teaches an RF transistor amplifier that may be a HEMT transistor (Radulescu, [0003]), discloses:
a transistor (Fig. 2A, [0068], transistor structure 200a semiconductor structure of a HEMT device.)
further comprising a backside metallization layer (metal contact 345) on the backside of the semiconductor substrate; (Fig. 2A, metal contact 345 is on the back side of substrate 322.)
wherein the first elongated cooling trench (source or drain contact 315 which may function as an elongated cooling trench underneath metal contacts 365.) does not physically contact the backside metallization layer. (See Fig. 2A, source/drain contact 315 is not in contact with the metal contact 345.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have a backside metallization layer on the backside of the semiconductor substrate and the first elongated cooling trench does not physically contact the backside metallization layer as taught by Radulescu for purposes of provide electrical connections on the backside. (Radulescu, [0064].)
Claim 5 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Chang.
Regarding claim 5, Chang discloses:
A transistor (Fig. 6E, a group III-V device 600.) comprising:
a semiconductor substrate having a top surface and a backside; (Fig. 6E, substrate 102)
a source terminal that has a first contact; (See Fig. 6E.)
a drain terminal that has a second contact; (See Fig. 6E, drain electrode 164 and conductive layer 566b.)
a semiconductor heterostructure (Fig. 6E, active layer 130, channel layer 120, buffer layer 110, transition layer 106, and nucleation layer 104.) including a channel region formed on the top surface of the semiconductor substrate, (The channel layer 120 is formed on the substrate 102.) wherein the semiconductor heterostructure has a top surface, (The source electrode 162 and drain electrode 164 are at the top surface of the active layer 130.) wherein the source and drain contacts are supported by and located at the top surface of the semiconductor heterostructure, (The source electrode 162 and drain electrode 164 are at the top surface of the active layer 130.) and wherein the channel region is configured to provide an electrically conductive path between the source terminal and the drain terminal; (The channel region 120 provides a conductive path between the source and drain electrodes.)
an elongated gate electrode (gate electrode 166) at the top surface of the semiconductor heterostructure between the source and drain contacts, wherein the gate electrode extends laterally from a first end of the gate electrode to a second end of the gate electrode in a first direction that is parallel to the top surface of the semiconductor substrate; (See Fig. 6E.)
a first elongated cooling trench (annotated Fig. 6E, via structure 150a on the left side of the device)…, wherein the first elongated cooling trench extends laterally from a first end of the first elongated cooling trench to a second end of the first elongated cooling trench along the first direction, and the first elongated cooling trench also extends vertically from the source terminal through the channel region and through an entire thickness of the semiconductor heterostructure, through the top surface of the semiconductor substrate and toward, but not to, the backside of the semiconductor substrate; and (See Fig. 6E.)
a second elongated cooling trench(annotated Fig. 6E, via structure 150b on the right side of the device) …), wherein the second elongated cooling trench extends laterally from a first end of the second elongated cooling trench to a second end of the second elongated cooling trench along the first direction, and the second elongated cooling trench also extends vertically from the drain terminal through the channel region and through the entire thickness of the semiconductor heterostructure, through the top surface of the semiconductor substrate and toward, but not to, the backside of the semiconductor substrate, (See Fig. 6E.)
wherein the first and second elongated cooling trenches are filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate. (See Fig. 6E, [0037], conductive layer 154 includes tungsten which is configured to dissipate heat.)
Chang in the embodiment of 6E could be argued that does not show that the first elongated cooling structure is “coupled to the source terminal” and the second elongated cooling structure is “coupled to the drain terminal.”
However, a second embodiment of Chang in Fig. 1LA shows the via structure 150 that is electrically connected to the source electrode 162. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang embodiment of Fig. 6E to have the first or second elongated cooling structure is “coupled to the source or drain terminal” by Chang embodiment of 1L for purposes of direct the electric current in such a way to reduce the background noise. (Chang, [0049].) Combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 5 above, and further in view of Lee et all. US 20230411461 A1 (hereinafter Lee).
Regarding claim 6, Chang further discloses:
wherein the thermally-conductive material of the first elongated cooling trench extends vertically into the semiconductor substrate to a first depth that does not reach the backside of the semiconductor substrate, (See Fig. 6E, via structure 150b has a horizontal and vertical direction and does not extend to the backside of the substrate 102.) and
Change also discloses that the thermally conductive material of the second elongated cooling trench extends vertically into the semiconductor substrate (See Fig. 6E.).
Change however does appear to disclose that “thermally conductive material of the second elongated cooling trench extends vertically into the semiconductor substrate to a second depth that is less than the first depth.”
Lee, which teaches a GaN semiconductor device (Lee, [0006]), discloses:
thermally conductive material of the second elongated cooling trench extends vertically into the semiconductor substrate to a second depth that is less than the first depth.(Lee et al. US 20230411461 A1, Fig. 2, contact structure 212 which extends into the substrate including AlGaN layer 208, which is less than the contact structure 214 which extends into the substrate including AlGaN layer 208 and GaN layer 206a but does not reach substrate 204.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have thermally conductive material of the second elongated cooling trench extends vertically into the semiconductor substrate to a second depth that is less than the first depth as taught by Lee for purposes of reducing the time-dependent gate oxide breakdown (TDDB) lifetime of the GaN layer 206. (Lee, [0033].)
Claims 7 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chang and Lee as applied to claim 6 above, and further in view of Radulescu et al. US 20230075505 A1. (hereinafter Radulescu).
Regarding claim 7, Chang and Lee disclose all the elements of claim 6.
Change Fig. 6E shows that neither conductive layer 154 contact the backside of the substrate 102, therefore there is no physical contact with the back of the substrate and there would not be any contact with any material on the back of the suberate. between the conductive layer 154 and backside metallization layer.
Change and Lee do not appear to disclose a backside metallization on the bottom surface of the substrate.
However, Radulescu, which teaches an RF transistor amplifier that may be a HEMT transistor (Radulescu, [0003]), discloses:
a backside metallization layer on a bottom surface of the semiconductor substrate (Fig. 2A, metal contact 345 is on the back side of substrate 322.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have a backside metallization layer on a bottom surface of the semiconductor substrate as taught by Radulescu for purposes of provide electrical connections on the backside. (Radulescu, [0064].)
Regarding claim 26, Chang, Lee and Radulescu disclose all the elements of claim 7.
Chang further discloses:
the first elongated cooling trench is not configured to convey current from the source terminal to the backside metallization layer, and the first elongated cooling trench is not configured to be in electrical communication with the backside metallization layer; and (Fig. 6E is a horizontal HEMT device therefore there is no intentional electrical communication between the via structure 150a and the backside of the substrate 102 and therefore no electrical communication between the conductive layer 154 and backside metallization layer.)
the second elongated cooling trench is not configured to convey current from the drain terminal to the backside metallization layer, and the second elongated cooling trench is not configured to be in electrical communication with the backside metallization layer. (Fig. 6E is a horizontal HEMT device therefore there is no intentional electrical communication between the via structure 150b and the backside of the substrate 102 and therefore no electrical communication between the via structure 150b and backside metallization layer.)
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chang.
Annotated Fig. 1L will be used in discussion of claim 23.
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Regarding claim 23, Chang discloses all the elements of claim 1.
While Chang does not directly disclose the aspect ratio of the trench. A representative aspect ratio can be measured by looking at the relative height and width of via structure in Fig. 1L which is about 20 blocks high and 4 blocks wide. See annotated Fig. 1L. Giving an aspect ratio of 5 height to width. Therefore Chang discloses at least indirectly “wherein the first elongated cooling trench has an aspect ratio of at least 5.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang to have the first elongated cooling trench has an aspect ratio of at least 5 as taught by Fig. 1L of Chang directly because absent persuasive evidence that the particular aspect ratio of the trench was significant the trench would have the desired height and width as claimed in the device of Chang, MPEP 2144.04.IV.B.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812