DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on 11/12/2025 are being considered by the examiner.
Response to Arguments
The examiner acknowledges the applicant’s arguments. Regarding applicants’ argument, “However, in Huang, the conductive interconnect features 157a, 157b - allegedly equivalent to the claimed lower source and drain contacts - are in substrate 144. They are not in the ILD layer 137. In other words, Huang does not disclose "a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer”, the prior art discloses examples of other embodiments in [0047] which states, “However, in another example, the conductive interconnect feature 157a (or another source contact between the conductive interconnect feature 157a and the source region 105c) may extend within the source region 105c (e.g., at least in part similar to the source contact 118b). Similarly, in another example, the conductive interconnect feature 157b (or another drain contact between the conductive interconnect feature 157b and the drain region 105d) may extend within the drain region 105d (e.g., at least in part similar to the drain contact 118b).” Therefore, the prior art does disclose the limitation “a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer” because the conductive interconnect features can extend into the source and drain (105d/105c) and therefore be within the IMD layer 137.
Regarding applicant’s argument, “However, the Office alleges that the lower device 140 is equivalent to the claimed lower GAA gate region. It is noted that the entirety of the lower device 140 is above the conductive interconnect features 157a, 157b. In short, Huang does not disclose "a lower gate-all-around (GAA) gate region in the IMD layer between the lower source and drain contacts." As stated above, another example the prior art discloses in [0047] which states, “However, in another example, the conductive interconnect feature 157a (or another source contact between the conductive interconnect feature 157a and the source region 105c) may extend within the source region 105c (e.g., at least in part similar to the source contact 118b). Similarly, in another example, the conductive interconnect feature 157b (or another drain contact between the conductive interconnect feature 157b and the drain region 105d) may extend within the drain region 105d (e.g., at least in part similar to the drain contact 118b).” Therefore, the prior art does disclose the limitation “a lower source contact and a lower drain contact in an intermetal dielectric (IMD) layer” because the conductive interconnect features can extend into the source and drain (105d/105c) and therefore be within the IMD layer 137.
The examiner acknowledges the addition of new claims 31-35 for which are incorporated into the action below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-9, 11-15, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230420460 A1) and further in view of Li et al. (US 20200235098 A1).
Regarding claim 1, Huang discloses a complementary field effect transistor (CFET) structure, comprising:
a lower source contact (157a) and a lower drain contact (157b) in an intermetal dielectric (IMD) layer (137); ([0047] discloses “However, in another example, the conductive interconnect feature 157a (or another source contact between the conductive interconnect feature 157a and the source region 105c) may extend within the source region 105c (e.g., at least in part similar to the source contact 118b). Similarly, in another example, the conductive interconnect feature 157b (or another drain contact between the conductive interconnect feature 157b and the drain region 105d) may extend within the drain region 105d (e.g., at least in part similar to the drain contact 118b).” but e.g. see Fig. 1A)
a lower gate-all-around (GAA) gate region (140) in the IMD layer (137) between the lower source and drain contacts (157a/157b), the lower GAA gate region (140) being a first conductivity type (per [0053]) and comprising one or more lower channel structures (103b per [0035]), (similarly, another example is disclosed in [0047] where (157a and 157b) may extend into the source/drain (105d and 105c) similarly to 118b and 118a).
an upper source contact (118a) and an upper drain contact (118b) in the IMD layer (137) above the lower source and drain contacts (157a/157b); (Fig. 1A)
an upper GAA gate region (101) in the IMD layer (157) above the lower GAA gate region (140) and between the upper source and drain contacts (118a/118b), the upper GAA gate region (101) being a second conductivity type opposite the first conductivity type (per [0053]) and comprising one or more upper channel structures (103a per [0035]), (Fig. 1A)
and
a common gate (127+177) in the IMD layer (137) between the lower source and drain contacts (157a/157b) and between the upper source and drain contacts (118a/118b), the common gate (127+177) being configured to apply a common voltage to the lower and upper channel structures (103a/103b). (Fig. 1A)
Huang does not disclose:
each lower channel structure comprising:
a lower transition metal dichalcogenide (TMD) channel electrically coupled with the lower source contact and with the lower drain contact; and
first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel;
each upper channel structure comprising:
an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact; and
first and second upper gate oxide layers respectively on lower and upper surfaces of the upper TMD channel;
However, Li discloses:
each lower channel structure (206L) comprising: ([0040]Fig. 2A)
a lower transition metal dichalcogenide (TMD) channel (210N per [0041]) electrically coupled with the lower source contact (230LS) and with the lower drain contact (230LD); ([0044], Fig. 2A) and
first and second lower gate oxide layers (426L top/bottom) respectively on lower and upper surfaces of the lower TMD channel (410N); ([0061], Fig. 4E)
each upper channel structure (206U) comprising:
an upper TMD channel (210P per [0041]) electrically coupled with the upper source contact (230US) and with the upper drain contact (230UD); ([0047], Fig. 2A) and
first and second upper gate oxide layers (426U top and bottom) respectively on lower and upper surfaces of the upper TMD channel (410P); ([0068], Fig. 4L)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang and Li for each lower channel structure comprising: a lower transition metal dichalcogenide (TMD) channel electrically coupled with the lower source contact and with the lower drain contact; and first and second lower gate oxide layers respectively on lower and upper surfaces of the lower TMD channel; and each upper channel structure comprising: an upper TMD channel electrically coupled with the upper source contact and with the upper drain contact; and first and second upper gate oxide layers respectively on lower and upper surfaces of the upper TMD channel in order to obtain “ a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.” (Li, [0038])
Regarding claim 4, Li discloses the CFET structure of claim 1, wherein
the lower TMD channel (210N) is formed from tungsten diselenide (WSe2) (per [0042]), and the upper TMD channel (210P) is formed from molybdenum disulfide (MoS2) (per [0045]). (Fig. 2A)
Regarding claim 5, Li discloses the CFET structure of claim 4, wherein
the lower TMD channel (210N) is formed from one or two layers of WSe2 (per [0042]), and wherein the upper TMD channel (210P) is formed from one or two layers of MoS2 (per [0045]). (Fig. 2A)
Regarding claim 6, Huang discloses the CFET structure of claim 1, wherein
the common gate (127+177) spans from an upper surface of the IMD layer (137) to a lower surface of the IMD layer (137). ([0065], Fig. 1A)
Regarding claim 7, Huang discloses the CFET structure of claim 1, wherein
the common gate (127+177) is formed from tungsten (W), (per [0067]) titanium nitride (TiN), or both.
Regarding claim 8, Huang discloses the CFET structure of claim 1, further comprising:
a source spacer (132) between the lower source contact (157a) and the common gate (127+177) and between the upper source contact (118a) and the common gate (127+177), the source spacer (132 right) spanning from an upper surface to a lower surface of the IMD layer (137); (Fig. 1A) and
a drain spacer (132 left) between the lower drain contact (157b) and the common gate (127+177) and between the upper drain contact (118b) and the common gate (127+177), the drain spacer (132 left) spanning from the upper surface to the lower surface of the IMD layer (137). (Fig. 1A)
Regarding claim 9, Li discloses the CFET structure of claim 1, wherein
the first lower gate oxide layer or the second lower gate oxide layer (426L top/bottom) or both are high-k dielectric layers (per [0061]), (Fig. 4E) or wherein
the first upper gate oxide layer or the second upper gate oxide layer(426U top/bottom) or both are high-k dielectric layers (per [0068]), (Fig. 4L) or both.
Regarding claim 11, Li discloses the CFET structure of claim 1, further comprising:
a lower inner source contact (224LS) between the lower source contact (230LS) and the lower GAA gate region (208L); (Fig. 2A) and
a lower inner drain contact (224LD) between the lower GAA gate region (208L) and the lower drain contact (230LD). (Fig. 2A)
Regarding claim 12, Li discloses the CFET structure of claim 11, wherein
the lower TMD channel (210N) extends into the lower inner source contact (224LS) and/or into the lower inner drain contact (224LD), (Fig. 2A) or (the examiner has met the first option as required limitation)
wherein the upper TMD channel extends into the upper source contact and/or into the upper drain contact, or both.
Regarding claim 13, Li discloses the CFET structure of claim 11, wherein
the lower TMD channel (210N) is formed from one of tungsten diselenide (WSe2) (per [0042]) and molybdenum disulfide (MoS2), and wherein
the upper TMD channel (210P) is formed from other one of WSe2 and MoS2. (per [0045])
Regarding claim 14, Li discloses the CFET structure of claim 1, further comprising:
a lower source terminal (214LS) in a lower IMD layer (228L) and electrically coupled with the lower source contact (230LS), the lower IMD layer (228LD) being on a lower surface of the IMD layer (207U); (Fig. 2A)
a lower drain terminal (214LD) in the lower IMD layer (228L) and electrically coupled with the lower drain contact (230LD); (Fig. 2A)
an upper source terminal (214US) in an upper IMD layer (228U) and electrically coupled with the upper source contact (214US), the upper IMD layer (228U) being on an upper surface of the IMD layer (207U); (Fig. 2A)
an upper drain terminal (214 UD) in the upper IMD layer (228U) and electrically coupled with the upper drain contact (230UD); (Fig. 2A) and
an upper gate terminal (230UG) in the upper IMD layer (228U) and
Li does not disclose:
Upper gate terminal… electrically coupled with the common gate.
However, Huang discloses:
Upper gate terminal (125b)… electrically coupled with the common gate (127+177). (Fig. 1A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Li and Huang for the upper gate terminal… electrically coupled with the common gate in order to “provide contacts to respective three gate structures 122 of the device 101” (Huang, [0066]) so as to “increase transistor density” (Huang, [0002])
Regarding claim 15, Li discloses the CFET structure of claim 14, further comprising:
a source via (MSD) in the upper IMD layer (228U) between and electrically coupling the upper source terminal (214US) with the upper source contact (230US); (Fig. 2A)
a drain via (MDS) in the upper IMD layer (228U) between and electrically coupling the upper drain terminal (214UD) with the upper drain contact (230UD); (Fig. 2A) and
a gate via (MG) in the upper IMD layer (228U) between and electrically coupling the upper gate terminal (230UG)
Li does not explicitly disclose:
The source via, drain via and gate via being in between the upper source/drain terminals and source/drain contacts
However, it would have been obvious to one in the art before the effective filing date to use the teachings of Li to position the source, drain and gate vias between the source drain and gate in order to “to minimize a footprint of the CFET cell circuit” (Li, [0052]) also since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Li does not disclose:
the common gate.
However, Huang discloses:
The common gate (127+177). (Fig. 1A)
Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Li and Huang to use a common gate in order to “ to scale to smaller feature dimensions and higher transistor densities” (Huang, [0002])
Regarding claim 20, Huang discloses the CFET structure of The CFET structure of claim 1, wherein
the lower source contact (157a) is formed from palladium (Pd), nickel (Ni), gold (Au), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), bismuth (Bi), antimony (Sb), molybdenum (Mo), ruthenium (Ru), or any combination thereof, (per [0050]) and/or wherein
the lower drain contact is formed from Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof, and/or wherein the upper source contact is formed from Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof, and/or wherein the upper drain contact is formed from Pd, Ni, Au, W, Ta, TaN, Ti, TiN, Bi, Sb, Mo, Ru, or any combination thereof.
Regarding claim 21, Huang discloses the CFET structure of claim 1, wherein
the CFET structure (inside 1004) is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle. (per [0098])
Claims 2, 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230420460 A1) in view of Li et al. (US 20200235098 A1) as applied to claim 1 above and further in view of Xie et al. (US 20210265345 A1).
Regarding claim 2, Huang in view of Lee discloses the CFET structure of claim 1. Huang in view of Lee do not disclose wherein each lower channel structure further comprises:
a first lower work function layer on a lower surface of the first lower gate oxide layer; and
a second lower work function layer on an upper surface of the second lower gate oxide layer, and wherein
each upper channel structure further comprises: a first upper work function layer on a lower surface of the first upper gate oxide layer; and
a second upper work function layer on an upper surface of the second upper gate oxide layer.
However, Xie discloses
each lower channel structure (210 and 214 below 1502) further comprises: a first lower work function layer (annotated 2002 below) on a lower surface of the first lower gate oxide layer (annotated 1804 below); ([0078], Fig. 21) and
a second lower work function layer (annotated 2002 below) on an upper surface of the second lower gate oxide layer (annotated 1804 below), and wherein each upper channel structure (222 and 226 above 1502) further comprises:
a first upper work function layer (annotated 2002 below) on a lower surface of the first upper gate oxide layer (annotated 1804 below); and
a second upper work function layer (annotated 2002 below) on an upper surface of the second upper gate oxide layer (annotated 1804 below). (Fig. 21)
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It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Xie for each lower channel structure further comprises: a first lower work function layer on a lower surface of the first lower gate oxide layer; and a second lower work function layer on an upper surface of the second lower gate oxide layer, and wherein each upper channel structure further comprises: a first upper work function layer on a lower surface of the first upper gate oxide layer; and a second upper work function layer on an upper surface of the second upper gate oxide layer in order to provide “stacked nanosheet CFET designs with improved workfunction-setting metal patterning techniques”(Xie, [0004])
Regarding claim 3, Xie discloses the CFET structure of claim 2, wherein
the first lower work function (annotated 2002 above) or the second lower work function layer (annotated 2002 above) or both are formed from one or both of titanium nitride (TiN) or titanium alumina (TiAl), (per [0079], Fig. 21) or
wherein the first upper work function layer (annotated 2002 above) or the second upper work function layer (annotated 2002 above) or both are formed from one or both of TiN or TiAl, or both. (per [0079], Fig. 21)
Regarding claim 10, Li discloses the CFET structure of claim 9. Li does not disclose wherein
the first lower gate oxide layer or the second lower gate oxide layer or both are formed from a combination of hafnium oxide (HfO2) and aluminum oxide (A1203) or a combination of Hf, HfO2, and A1203, or
wherein the first upper gate oxide layer or the second upper gate oxide layer or both are formed from a combination of HfO2 and A1203 or a combination of Hf, HfO2, and A1203, or both.
However, Xie discloses:
the first lower gate oxide layer (annotated 1804 above) or the second lower gate oxide layer (annotated 1804 above) or both are formed from a combination of hafnium oxide (HfO2) and aluminum oxide (A1203) (per [0076]), (the examiner has met the first option as required by the limitation), or a combination of Hf, HfO2, and A1203, or
wherein the first upper gate oxide layer (annotated 1804 above) or the second upper gate oxide layer (annotated 1804 above) or both are formed from a combination of HfO2 and A1203 (per [0076]), (the examiner has met the first option as required by the limitation), or a combination of Hf, HfO2, and A1203, or both.
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Li and Xie for the first lower gate oxide layer or the second lower gate oxide layer or both are formed from a combination of hafnium oxide (HfO2) and aluminum oxide (A1203) or a combination of Hf, HfO2, and A1203, or wherein the first upper gate oxide layer or the second upper gate oxide layer or both are formed from a combination of HfO2 and A1203 or a combination of Hf, HfO2, and A1203, or both in order to provide “stacked nanosheet CFET designs with improved workfunction-setting metal patterning techniques”(Xie, [0004])
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20200235098 A1) in view of Huang et al. (US 20230420460 A1) as applied to claim 14 above and further in view of Lu et al. (US 20210280582 A1).
Regarding claim 16, Li discloses the CFET structure of claim 14, further comprising:
a tail via (232 LG) in the IMD layer (207U) and in the upper IMD layer (228U), ([0050], Fig. 2B)
Li does not disclose:
the tail via electrically coupling the lower drain terminal with the upper drain terminal, wherein the CFET structure is configured to function as an inverter.
However, Lu discloses:
the tail via (426A) electrically coupling the lower drain terminal (D/S 424-1) with the upper drain terminal (VOUT), (Fig. 4H) wherein
the CFET structure (100) is configured to function as an inverter (per [0004]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Li and Lu for the tail via electrically coupling the lower drain terminal with the upper drain terminal, wherein the CFET structure is configured to function as an inverter because “reducing the number of metal traces reduces congestion of routing tracks above the 3D CMOS cell circuit, allowing the 3D CMOS cell circuits in an IC to be more densely arranged and reduce an area of the IC.” (Lu, [0034]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20200235098 A1) in view of Huang et al. (US 20230420460 A1) as applied to claim 14 above and further in view of Lu et al. (US 20210280582 A1).
Regarding claim 17, Huang discloses the CFET structure of claim 14, further comprising:
a second lower source contact (annotated 157a) and a second lower drain contact (annotated 157b below) in the IMD layer (137); ([0046], Fig. 1A)
a second lower GAA gate region (140) in the IMD layer (137) between the second lower source and drain contacts (157a/157b), the second lower GAA gate region (140) being the first conductivity type (per [0053]) and comprising one or more second lower channel structures (103b per [0035]) each second lower channel structure comprising:
a second lower TMD channel (per [0068], “a p-channel device may include a work function metal having titanium, and an n-channel device may include a work function metal having tungsten or aluminum, although other material and combination may also be possible.” Tungsten and titanium are transition metals) electrically coupled with the second lower source contact (157a) and with the second lower drain contact (157b); and
second-first and second-second lower gate oxide layers (120) respectively on lower and upper surfaces of the second lower TMD channel (103b); ([0070], Fig. 1A)
a second upper source contact (annotated 118a below) and a second upper drain contact (annotated 118b below) in the IMD layer (137) above the second lower source and drain contacts (annotated 157a/157b below); (Fig. 1A)
a second upper GAA gate region (101) in the IMD layer (137) above the second lower GAA gate region (140) and between the second upper source and drain contacts (annotated 120a/120b), the second upper GAA gate region (101) being the second conductivity type (per [0053]) and comprising one or more second upper channel structures (103a), each second upper channel structure (103a) comprising:
a second upper TMD channel (103a) electrically coupled with the second upper source contact (annotated 120a) and with the second upper drain contact (annotated 120b); (Fig. 1A) and
second-first and second-second upper gate oxide layers (120) respectively on upper and lower surfaces of the second upper TMD channel (103a); ([0070], Fig. 1A)
a second common gate (127+177) in the IMD layer (137) between the second lower source and drain contacts (annotated 157a/157b) and between the second upper source and drain contacts (annotated 120a/120b), the second common gate (127+177) being configured to apply a second common voltage to the second lower and upper channel structures (103a/103b); (Fig. 1A)
a second lower drain terminal (annotated 105d) in the lower IMD layer (lower portion 137) and electrically coupled with the second lower drain contact (annotated 157b); (Fig. 1A)
a second upper drain terminal (annotated 105b) in the upper IMD layer (upper portion of 137) and electrically coupled with the second upper drain contact (annotated 120b); (Fig. 1A)
the upper drain terminal (105b) is also electrically coupled with the second upper source contact (118b), (Fig. 1A)
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Huang does not disclose:
a tail via in the IMD layer and in the upper IMD layer,
However, Li discloses:
a tail via (232LG) in the IMD layer (207U) and in the upper IMD layer (228U), ([0050], Fig. 2B)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang and Li for a tail via in the IMD layer and in the upper IMD layer because “reducing the number of metal traces reduces congestion of routing tracks above the 3D CMOS cell circuit, allowing the 3D CMOS cell circuits in an IC to be more densely arranged and reduce an area of the IC.” (Lu, [0008]).
Huang and Li do not disclose:
the tail via electrically coupling the second lower drain terminal with the second upper drain terminal, wherein
the CFET structure is configured to function as a NAND logic.
However, Lu discloses:
the tail via (426A) electrically coupling the second lower drain terminal (D/S 424-1) with the second upper drain terminal (VOUT), (Fig. 4H) wherein
the CFET structure (100) is configured to function as a NAND logic. (per [0078])
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Lu for the tail via electrically coupling the second lower drain terminal with the second upper drain terminal, wherein the upper drain terminal is also electrically coupled with the second upper source contact, and wherein the CFET structure is configured to function as a NAND logic because “reducing the number of metal traces reduces congestion of routing tracks above the 3D CMOS cell circuit, allowing the 3D CMOS cell circuits in an IC to be more densely arranged and reduce an area of the IC.” (Lu, [0034]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20200235098 A1) in view of Huang et al. (US 20230420460 A1) as applied to claim 14 above and further in view of Lu et al. (US 20210280582 A1).
Regarding claim 18, Huang discloses the CFET structure of claim 14, further comprising:
a third lower source contact (annotated 157a) and a third lower drain contact (annotated 157b below) in the IMD layer (137); ([0046], Fig. 1A)
a third lower GAA gate region (140) in the IMD layer (137) between the third lower source and drain contacts (157a/157b), the third lower GAA gate region (140) being the first conductivity type (per [0053]) and comprising one or more third lower channel structures (103b per [0035]) each third lower channel structure comprising:
a third lower TMD channel (per [0068], “a p-channel device may include a work function metal having titanium, and an n-channel device may include a work function metal having tungsten or aluminum, although other material and combination may also be possible.” Tungsten and titanium are transition metals) electrically coupled with the third lower source contact (157a) and with the third lower drain contact (157b); and
third-first and third-second lower gate oxide layers (120) respectively on lower and upper surfaces of the third lower TMD channel (103b); ([0070], Fig. 1A)
a third upper source contact (annotated 118a below) and a third upper drain contact (annotated 118b below) in the IMD layer (137) above the third lower source and drain contacts (annotated 157a/157b below); (Fig. 1A)
a third upper GAA gate region (101) in the IMD layer (137) above the third lower GAA gate region (140) and between the third upper source and drain contacts (annotated 120a/120b), the third upper GAA gate region (101) being the second conductivity type (per [0053]) and comprising one or more third upper channel structures (103a), each third upper channel structure (103a) comprising:
a third upper TMD channel (103a) electrically coupled with the third upper source contact (annotated 120a) and with the third upper drain contact (annotated 120b); (Fig. 1A) and
third -first and third -second upper gate oxide layers (120) respectively on upper and lower surfaces of the third upper TMD channel (103a); ([0070], Fig. 1A)
a third common gate (127+177) in the IMD layer (137) between the third lower source and drain contacts (annotated 157a/157b) and between the third upper source and drain contacts (annotated 120a/120b), the third common gate (127+177) being configured to apply a third common voltage to the third lower and upper channel structures (103a/103b); (Fig. 1A)
a third lower drain terminal (annotated 105d) in the lower IMD layer (lower portion 137) and electrically coupled with the third lower drain contact (annotated 157b); (Fig. 1A)
a third upper drain terminal (annotated 105b) in the upper IMD layer (upper portion of 137) and electrically coupled with the third upper drain contact (annotated 120b); (Fig. 1A)
the upper drain terminal (105b) is also electrically coupled with the third upper source contact (118b), (Fig. 1A)
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Huang does not disclose:
a tail via in the IMD layer and in the upper IMD layer,
However, Li discloses:
a tail via (232LG) in the IMD layer (207U) and in the upper IMD layer (228U), ([0050], Fig. 2B)
the CFET structure is configured to function as a NOR logic. ([0002])
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang and Li for a tail via in the IMD layer and in the upper IMD layer because “reducing the number of metal traces reduces congestion of routing tracks above the 3D CMOS cell circuit, allowing the 3D CMOS cell circuits in an IC to be more densely arranged and reduce an area of the IC.” (Lu, [0008]) and “To automate the process of designing IC components which may contain millions of transistors, standardized CMOS logic cell circuits (e.g., inverters, NAND, NOR, etc.) have been developed for use with design automation software tools. Design automation tools are able to generate physical layouts of circuits in which the standardized CMOS circuits are optimally positioned to minimize a total circuit area.”
Huang and Li do not disclose:
the tail via electrically coupling the third lower drain terminal with the third upper drain terminal, wherein
However, Lu discloses:
the tail via (426A) electrically coupling the third lower drain terminal (D/S 424-1) with the third upper drain terminal (VOUT), (Fig. 4H) wherein
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Lu for the tail via electrically coupling the second lower drain terminal with the second upper drain terminal, wherein the upper drain terminal is also electrically coupled with the second upper source contact because “reducing the number of metal traces reduces congestion of routing tracks above the 3D CMOS cell circuit, allowing the 3D CMOS cell circuits in an IC to be more densely arranged and reduce an area of the IC.” (Lu, [0034]).
Claims 19 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20200235098 A1) in view of Huang et al. (US 20230420460 A1) as applied to claim 14 above and further in view of Alzate Vinasco et al. (US 20200194434 A1).
Regarding claim 19, Li and Huang disclose the CFET structure of claim 14. Li and Huang do not disclose further comprising:
a lower protection layer between the lower IMD layer and the IMD layer; and an upper protection layer on the upper IMD layer.
However, Alzate Vinasco discloses
a lower protection layer (181) between the lower IMD layer (under 175) and the IMD layer (175); (Fig. 1C) and
an upper protection layer (183) on the upper IMD layer (177). (Fig. 1C)
It would have been obvious to ones killed in the art before the effective filing date to combine the teachings of Li, Huang and Alzate Vinasco to have a lower protection layer between the lower IMD layer and the IMD layer; and an upper protection layer on the upper IMD layer in order to “protect underlying materials from unwanted etching during specific processing steps.”
Regarding claim 35, Alzate Vinasco disclose the CFET structure of claim 19 wherein the lower protection layer (181) is on a lower surface of the IMD layer (under 175), (Fig. 1C)
Alzate Vinasco Fig. 1C does not disclose:
and wherein the upper protection layer is on an upper surface of the upper IMD layer.
However, Fig. 2a shows
and wherein the upper protection layer (annotated below) is on an upper surface of the upper IMD layer (260). (Fig. 1C)
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It would have been obvious to ones killed in the art before the effective filing date to combine the teachings of Li, Huang and Alzate Vinasco for the lower protection layer is on a lower surface of the IMD layer, and wherein the upper protection layer is on an upper surface of the upper IMD layer for similar reasons as stated above.
Claims 31-34 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20230420460 A1) in view of Li et al. (US 20200235098 A1) as applied to claims 1 and 11 above (respectively) and further in view of Dorow et al. (US 20220199838 A1).
Regarding claim 31, Huang in view of Li disclose the CFET structure of claim 1. Huang in view of Li do not disclose wherein the lower TMD channel is in physical contact with the lower source contact and with the lower drain contact, or wherein the upper TMD channel is in physical contact with the upper source contact and with the lower drain contact, or both.
However, Dorow discloses:
wherein the lower TMD channel (204) is in physical contact with the lower source contact (208) and with the lower drain contact (210), ([0074], Fig. 2A), (the examiner is treating additional limitations past “or” as optional), or wherein the upper TMD channel is in physical contact with the upper source contact and with the lower drain contact, or both.
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Dorow for wherein the lower TMD channel is in physical contact with the lower source contact and with the lower drain contact, or wherein the upper TMD channel is in physical contact with the upper source contact and with the lower drain contact, or both in order to “advantageously reduce a Schottky barrier height between each of the TMD channel layers 202 and 204 and the respective source contact 208 and drain contact 210.” (Dorow, [0084])
Regarding claim 32, Huang in view of Li disclose the CFET structure of claim 1. Huang in view of Li do not disclose wherein the first lower gate oxide layer and the second lower gate oxide layer are in physical contact with the lower source contact and with the lower drain contact, or wherein the first upper gate oxide layer and the second upper gate oxide layer are in physical contact with the upper source contact and with the upper drain contact, or both.
However, Dorow discloses:
wherein the first lower gate oxide layer (206 below 204) and the second lower gate oxide layer (206 above 204) are in physical contact with the lower source contact (208) and with the lower drain contact (210), ([0074], [0097] Fig. 2A), (the examiner is treating additional limitations past “or” as optional) or wherein the first upper gate oxide layer and the second upper gate oxide layer are in physical contact with the upper source contact and with the upper drain contact, or both
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Dorow for wherein the first lower gate oxide layer and the second lower gate oxide layer are in physical contact with the lower source contact and with the lower drain contact, or wherein the first upper gate oxide layer and the second upper gate oxide layer are in physical contact with the upper source contact and with the upper drain contact, or both in order to “advantageously reduce a Schottky barrier height between each of the TMD channel layers 202 and 204 and the respective source contact 208 and drain contact 210.” (Dorow, [0084])
Regarding claim 33, Huang in view of Li disclose the CFET structure of claim 11. Huang in view of Li do not disclose wherein the lower TMD channel is in physical contact the lower inner source contact and with the lower inner drain contact, or wherein the upper TMD channel is in physical contact with the upper source contact and with the lower drain contact, or both.
However, Dorow discloses:
wherein the lower TMD channel (204) is in physical contact with the lower source contact (208) and with the lower drain contact (210), ([0074], Fig. 2C), (the examiner is treating additional limitations past “or” as optional), or wherein the upper TMD channel is in physical contact with the upper source contact and with the lower drain contact, or both.
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Dorow for disclose wherein the lower TMD channel is in physical contact the lower inner source contact and with the lower inner drain contact, or wherein the upper TMD channel is in physical contact with the upper source contact and with the lower drain contact, or both in order to “advantageously reduce a Schottky barrier height between each of the TMD channel layers 202 and 204 and the respective source contact 208 and drain contact 210.” (Dorow, [0084])
Regarding claim 34, Huang in view of Li disclose the CFET structure of claim 11. Huang in view of Li do not disclose wherein the first lower gate oxide layer and the second lower gate oxide layer are in physical contact with the lower inner source contact and with the lower inner drain contact, or wherein the first upper gate oxide layer and the second upper gate oxide layer are in physical contact with the upper source contact and with the upper drain contact, or both.
However, Dorow discloses:
wherein the first lower gate oxide layer (206 below 204) and the second lower gate oxide layer (206 above 204) are in physical contact with the lower source contact (208) and with the lower drain contact (210), ([0074], [0097] Fig. 2A), (the examiner is treating additional limitations past “or” as optional), or wherein the first upper gate oxide layer and the second upper gate oxide layer are in physical contact with the upper source contact and with the upper drain contact, or both.
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Huang, Li and Dorow for wherein the first lower gate oxide layer and the second lower gate oxide layer are in physical contact with the lower inner source contact and with the lower inner drain contact, or wherein the first upper gate oxide layer and the second upper gate oxide layer are in physical contact with the upper source contact and with the upper drain contact, or both because “encapsulation layer 206 may advantageously reduce a Schottky barrier height between each of the TMD channel layers 202 and 204 and the respective source contact 208 and drain contact 210. Reduction in Schottky barrier height may facilitate reduction in contact resistance.” (Dorow, [0084])
Pertinent Art
The examiner wants to disclose that another prior art Lin et al. (20220216340 A1) discloses some limitations such as “a lower source contact (286) and a lower drain contact (288) in an intermetal dielectric (IMD) layer (280).” See e.g. [0038], Fig. 20 but does not disclose all the limitations as required by the claim.
Conclusion
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897