Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1-2,4,6-9,11-12,14,16-18 and 20-24 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20100103570 A1 (Song).
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Regarding claim 1, Song shows (Fig. 6) an electrostatic discharge protection circuit (para 32), comprising:
a first N type region (93+99);
a first P type region (95+104);
a second P type region (100) in the first N type region;
second N type region (101) in the first P type region;
a first conductive terminal (VDD) electrically connected to the first N type region;
a second conductive terminal (VSS) electrically connected to the first P type region (through 104) and the second N type region;
a power clamp circuit (17) electrically connected between the first conductive terminal and the second conductive terminal;
a conductive pad (PAD) electrically connected to the second P type region; and
a third N type region (103) in the first P type region, wherein the conductive pad is electrically connected to the third N type region.
Regarding claim 2, Song shows (Fig. 6) wherein the second P type region (100), the first N type region (93+99), the first P type region (95+104) and the second N type region (101) form a silicon controlled rectifier (para 45).
Regarding claim 4, Song shows (Fig. 6) wherein the first N type region (93) and the second P type region (100) form a diode.
Regarding claim 6, Song shows (Fig. 6) wherein the first conductive terminal is a power input terminal (VDD), the second conductive terminal (VSS) is a ground terminal.
Regarding claim 7, Song shows (Fig. 6) wherein the first N type region comprises:
a N type well (93); and
a fourth N type region (99) in the N type well, wherein the second P type region (100) is in the N type well, the first conductive terminal (VDD) is electrically connected to the fourth N type region.
Regarding claim 8, Song shows (Fig. 6) wherein the first P type region comprises:
a P type well (95); and
a third P type region (104) in the P type well, wherein the second conductive terminal (VSS) is electrically connected to the third P type region.
Regarding claim 9, Song shows (Fig. 6) further comprising a fourth P type region (102) in the first N type region, wherein the first conductive terminal (VDD) is electrically connected to the fourth P type region.
Regarding claim 11, Song shows (Fig. 6) an electrostatic discharge protection circuit, comprising:
a first P type region (95+104);
a first N type region (93+99);
a second N type region (103) in the first P type region;
a second P type region (102) in the first N type region;
a first conductive terminal (VDD) electrically connected to the second P type region and the first N type region;
a second conductive terminal (VSS) electrically connected to the first P type region;
a power clamp circuit (17) electrically connected between the first conductive terminal and the second conductive terminal;
a conductive pad (PAD) electrically connected to the second N type region; and
a third P type region (100) in the first N type region, wherein the conductive pad is electrically connected to the third P type region.
Regarding claim 12, Song shows (Fig. 6) wherein the first P type region (95) and the second N type region (103) form a diode.
Regarding claim 14, Song shows (Fig. 6) wherein the second P type region (102), the first N type region (93), the first P type region (95) and the second N type region (103) form a silicon controlled rectifier (para 45).
Regarding claim 16, Song shows (Fig. 6) wherein the first P type region comprises:
a P type well (95); and
a fourth P type region (104) in the P type well, wherein the second N type region (101) is in the P type well, the second conductive terminal (VSS) is electrically connected to the fourth P type region.
Regarding claim 17, Song shows (Fig. 6) wherein the first conductive terminal is a power input terminal (VDD), the second conductive terminal (VSS) is a ground terminal.
Regarding claim 18, Song shows (Fig. 6) wherein the first N type region comprises: a N type well (93); and
a third N type region (99) in the N type well, wherein the first conductive terminal (VDD) is electrically connected to the third N type region.
Regarding claim 20, Song shows (Fig. 6) further comprising a fourth N type region (101), wherein the first P type region comprises:
a P type well (95); and
a fourth P type region (104) in the P type well, wherein the fourth N type region is in the P type well, the second conductive terminal (VSS) is electrically connected to the fourth N type region.
Regarding claim 21, Song shows (Fig. 6) wherein an electrostatic discharge current flows through the conductive pad (PAD), the second P type region (102), the first N type region (93+99), the first conductive terminal (VDD) and the power clamp circuit in sequence.
Regarding claim 22, Song shows (Fig. 6) wherein an electrostatic discharge current flows through the conductive pad (PAD), the second P type region (102), the first N type region (93), the first P type region (95) and the second N type region (101) the second conductive terminal (VSS) in sequence.
Regarding claim 23, Song shows (Fig. 6) wherein an electrostatic discharge current flows through the first conductive terminal (VDD), the power clamp circuit (17), the second conductive terminal (VSS), the first P type region (95+104), the second N type region (103) and the conductive pad (PAD) in sequence.
Regarding claim 24, Song shows (Fig. 6) wherein an electrostatic discharge current flows through the first conductive terminal (VDD), the second P type region (102), the first N type region (93,99), the first P type region (95,104), the second N type region (103) and the conductive pad (PAD) in sequence.
Conclusion
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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