DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OTSU (US 20200402992).
Regarding claim 1, OTSU discloses an electronic device, comprising:
a stack (the stack of materials comprising at least 132, 146, 232 and 246, see fig 32, para 210-214) comprising an alternating sequence of conductive structures (electrically conductive layers 146 and 246, see fig 32, para 214) and insulative structures (insulating layers 132, 132', 232 and 232', see fig 32, para 215) arranged in tiers (the layers 132, 146, 232 and 246 are in tiers, see fig 32D);
at least one dielectric-filled slot (the slot full of dielectric 376, see fig 32E, para 256) extending vertically through the stack (376 extends vertically through the stack, see fig 32D) and extending in a first horizontal direction (376 extends in direction hd2, see fig 32E), the at least one dielectric-filled slot defined between two internal sidewalls of the stack (376 is located between sidewalls of the stack materials 132, 146, 232 and 246, see fig 32D);
additional dielectric-filled slots (dielectric fill structures 76, see fig 32E, para 256) extending vertically through the stack (76 extends through the stack, see fig 32D) and extending in a second horizontal direction transverse to the first horizontal direction (76 extends in direction hd1, see fig 32E);
separation regions (regions of the device between 376 and 76, see fig 32E and figure I below) adjacent at least some of the conductive structures (the regions comprise and will be adjacent to portions of the conductive layers 146 and 246, see fig 32D, para 210) and between the at least one dielectric-filled slot and the additional dielectric-filled slots (lines can be drawn from 376 to 76 that pass through the separation regions, see fig 32E and figure I below); and
isolation structures (isolation structures 72, see fig 32, para 218) laterally interposed in the separation regions (72 are at least partially in the separation regions, see fig 32E and figure I below) between the at least one dielectric-filled slot and the additional dielectric-filled slots (a line can be drawn from 376 to 76 that passes through 72, see fig 32E), the isolation structures laterally adjacent to the conductive structures of the stack (72 passes through and thus will be adjacent to the conductive layers 146 and 246, see para 218), and at least some of the isolation structures vertically adjacent to the insulative structures of the stack (72 passes through and thus will be adjacent to the conductive layers 132 and 232, see para 218).
Regarding claim 2, OTSU discloses the electronic device of claim 1, wherein the additional dielectric- filled slots divide the stack into blocks (76 divides the stack into pieces, see fig 32, para 256) comprising memory pillars (the memory pillars 58, see fig 32, para 242 and fig 9D, para 178), the isolation structures external to the at least one dielectric-filled slot (72 are not located inside 376, see fig 32E) and horizontally overlapping ends of the additional dielectric-filled slots (both 72 and 76 extend through the stack, and they will thus overlap along a horizontal direction, see fig 22 and 32).
Regarding claim 3, OTSU discloses the electronic device of claim 1, wherein the additional dielectric- filled slots directly contact the isolation structures without contacting the at least one dielectric- filled slot (72 directly contacts 376 and does not directly contact 76, see fig 32E).
Regarding claim 5, OTSU discloses the electronic device of claim 1, wherein the isolation structures directly contact the conductive structures of the stack along vertical interfaces therebetween (72 directly contacts 246, see fig 22 and para 218), and the isolation structures directly contact the insulative structures of the stack along horizontal interfaces therebetween (72 directly contacts 232, see fig 22 and para 218).
Regarding claim 6, OTSU discloses the electronic device of claim 1, wherein a material composition of the isolation structures (72 can be silicon oxide, see para 216-220) is substantially the same as a material composition of one or more of the at least one dielectric-filled slot, the additional dielectric-filled slots, and the insulative structures of the stack (132 can also be silicon oxide, see para 132).
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Figure I: OTSU figure 32E with added annotations.
Claim(s) 7-8 and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KAI (US 20200235120).
Regarding claim 7, KAI discloses an electronic device, comprising:
a stack (the stack of 132, 146, 232 and 246, see fig 24, para 148 and 95) comprising tiers of alternating conductive structures (conductive layers 146 and 246, see fig 24, para 148) and insulative structures (insulating layers 132 and 232, see fig 24, para 70 and 96) overlying a source (source layer 10, see fig 24, para 53);
pillars (the memory opening fill structure 58 including 55, see fig 9D, para 118) extending vertically through the stack and to the source (55 extends through the stack and to source 10, see fig 24A), at least some of the pillars comprising a channel material (channel 60 is included in 55, see fig 9D, para 111);
dielectric block structures (dielectric slot 76 that extends through layers 132, 146, 232 and 246, see fig 24, para 153) extending vertically through the stack, the dielectric block structures defined between two internal sidewalls of the stack and spaced apart from one another in a first horizontal direction (the structures 76 extend between sidewalls of 132, 232, 146 and 246, and the different walls 76 are separated in direction hd2, see fig 24B);
dielectric-filled slots (dielectric slots 176, see fig 24, para 130) extending vertically through the stack and extending in a second horizontal direction that is substantially orthogonal to the first horizontal direction (176 extend in direction hd1, see fig 24B); and
isolation structures (fig 24, 72, para 103) separating the dielectric block structures from the dielectric-filled slots (a line can be drawn from 76 to 176 that passes through 72, see fig 24B), the isolation structures at an elevational level of the conductive structures of the stack (72 is on the same vertical level as a conductive layer 246, see fig 24A).
Regarding claim 8, KAI discloses the electronic device of claim 7, further comprising support structures (fig 9 and 24, 62, para 115) extending vertically through the stack and laterally adjacent to the dielectric-filled slots (62 extends through the stack and is part of 58 which is close to 176, see fig 9 and 24, para 115) , the support structures and the isolation structures comprising an oxide material (62 and 72 can both be SiO2, see fig 9 and 24, para 115 and 103).
Regarding claim 10, KAI discloses the electronic device of claim 7, wherein one of the dielectric-filled slots is adjacent to one of the dielectric block structures in the second horizontal direction (176 and 76 are close to each other and next to each other in direction hd2, see fig 24B).
Regarding claim 11, KAI discloses the electronic device of claim 7, wherein a width of individual dielectric block structures in the first horizontal direction is greater than a width of individual dielectric-filled slots in the first horizontal direction (76 has a larger width0 in hd1 than 176, see fig 24B and 24C).
Regarding claim 12, KAI discloses the electronic device of claim 7, wherein an outer boundary of an isolation region including the isolation structures is relatively wider than outer boundaries of the dielectric block structures in the second horizontal direction (a region including isolation structure 72 can be defined that has a larger width in hd2 than does 76, see fig 24C).
Claim(s) 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KAI (US 20200235120).
Regarding claim 7, KAI discloses an electronic device, comprising:
a stack (the stack of 132, 146, 232 and 246, see fig 24, para 148 and 95) comprising tiers of alternating conductive structures (conductive layers 146 and 246, see fig 24, para 148) and insulative structures (insulating layers 132 and 232, see fig 24, para 70 and 96) overlying a source (source layer 10, see fig 24, para 53);
pillars (the memory opening fill structure 58 including 55, see fig 9D, para 118) extending vertically through the stack and to the source (55 extends through the stack and to source 10, see fig 24A), at least some of the pillars comprising a channel material (channel 60 is included in 55, see fig 9D, para 111);
dielectric block structures (dielectric slots 176, see fig 24, para 130) extending vertically through the stack, the dielectric block structures defined between two internal sidewalls of the stack and spaced apart from one another in a first horizontal direction (the structures 176 extend between sidewalls of 132, 232, 146 and 246, and the different walls 176 are separated in direction hd2, see fig 24B);
dielectric-filled slots (dielectric slot 76 that extends through layers 132, 146, 232 and 246, see fig 24, para 153) extending vertically through the stack and extending in a second horizontal direction that is substantially orthogonal to the first horizontal direction (76 extend in direction hd1, see fig 24B); and
isolation structures (fig 24, 72, para 103) separating the dielectric block structures from the dielectric-filled slots (a line can be drawn from 76 to 176 that passes through 72, see fig 24B), the isolation structures at an elevational level of the conductive structures of the stack (72 is on the same vertical level as a conductive layer 246, see fig 24A).
Regarding claim 9, KAI discloses the electronic device of claim 7, wherein sidewalls of the isolation structures abut portions of the conductive structures of the stack at a location external to vertical interfaces between the dielectric block structures and the isolation structures (sidewalls of 72 directly contact sidewalls of conductive structures 246 at locations outside 176, see fig 24), the dielectric block structures directly contacting the isolation structures along the vertical interfaces therebetween (72 directly contacts 176, see fig 24).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSU (US20200402992) in view of N J LEE (US 20220077182).
Regarding claim 4, OTSU discloses the electronic device of claim 1, wherein the at least one dielectric- filled slot tapers in width from a broadest width at a top of the stack to a narrowest width at a bottom of the stack (376 narrows from the top of the stack to the bottom of the stack, see fig 32B, para 256).
OTSU fails to explicitly disclose a device wherein a thickness of the isolation structures at the bottom of the stack is relatively greater than a thickness of the isolation structures at the top of the stack.
N J LEE teaches a device wherein a thickness of the isolation structures at the bottom of the stack is relatively greater than a thickness of the isolation structures at the top of the stack (the thickness of isolation insulating layer SG near the bottom of stack G1 is larger than its thickness near the top of stack G1, see fig 3A, para 34).
OTSU and N J LEE are analogous art because they both are directed towards 3D memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OTSU with the isolation structure geometry of N J LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OTSU with the isolation structure geometry of N J LEE in order to improve the alignment margin (see N J LEE para 89).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAI (US 20200235120) in view of LEE (US 20150318301).
Regarding claim 13, KAI discloses the electronic device of claim 7, wherein end surfaces of the isolation structures and the insulative structures of the stack proximal the dielectric block structures are substantially aligned with one another (vertical end surfaces of 72 and 242 are in direct contact and thus aligned with each other, see fig 24A).
KAI fails to explicitly disclose a device wherein end surfaces of the conductive structures of the stack proximal the dielectric block structures are horizontally recessed relative to the end surfaces of the insulative structures.
LEE teaches a device wherein end surfaces of the conductive structures of the stack proximal the dielectric block structures are horizontally recessed relative to the end surfaces of the insulative structures (end surfaces of the conductive layers 172 proximate to the dielectric layers 180 are recessed relative to the end surfaces of the insulating layers 110, see fig 2A, para 63, 44).
KAI and LEE are analogous art because they both are directed towards 3D memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KAI with the conductive structure shape of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KAI with the conductive structure shape of LEE in order to improve stability and reliability (see LEE para 71).
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAI (US 20200235120) in view of CHANDOLU (US 20210043504).
Regarding claim 25, KAI discloses a system, comprising:
one or more electronic device,
the one or more electronic devices comprising: strings of memory cells (the columns of memory fill material 55 and 58, see fig 24 and 9D, para 118) extending vertically through a tiered stack (the stack of 132, 146, 232 and 246, see fig 24, para 148 and 95) comprising a vertically alternating sequence of insulative structures (insulating layers 132 and 232, see fig 24, para 70 and 96) and conductive structures (conductive layers 146 and 246, see fig 24, para 148);
slot structures (fig 24, 76, para 153) extending vertically through the tiered stack and separating the tiered stack into blocks (76 separates the stack into blocks, see fig 24), each of the blocks comprising some of the strings of memory cells (come of 58 are in each block, see fig 24B);
at least one additional slot structure (fig 24, 176, para 130) extending vertically through the tiered stack and extending in a horizontal direction that is substantially orthogonal to another horizontal direction in which the slot structures extend (176 extends in hd2 which is perpendicular to hd1 in which 76 extends, see fig 24B); and
opposing isolation regions (fig 24, 72, para 103) laterally separating the at least one additional slot structure from the conductive structures of the tiered stack (a line can be drawn from 172 to a part of 246 that passes through 72, see fig 24C), the opposing isolation regions comprising a barrier material (72 can be made of SiO2, see para 103) between vertically neighboring insulative structures of the tiered stack (72 can be between portions of insulating layer 232, see fig 24A, para 96) and located outside of a horizontal area of the at least one additional slot structure (72 extends outside the area of 176, see fig 24B).
KAI fails to explicitly disclose a device comprising a processor operably coupled to an input device and an output device; and
the one or more electronic devices operably coupled to the processor.
CHANDOLU teaches a device comprising a processor (processor 304, see fig 3, para 60) operably coupled to an input device (input device 306, see fig 3, para 60) and an output device (output device 308, see fig 3, para 60); and
one or more electronic devices operably coupled to the processor (the memory device 200 with the tiered stack can be the memory device 302 which is coupled to the processor 304, see fig 3, para 60).
KAI and CHANDOLU are analogous art because they both are directed towards 3D memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KAI with the device being linked to a processor, and input device and an output device of CHANDOLU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KAI with the device being linked to a processor, and input device and an output device of CHANDOLU in order to facilitate one or more of improved performance, reliability, and durability, lower costs, increased miniaturization of components, improved pattern quality, and greater packaging density (see CHANDOLU para 62).
Regarding claim 26, KAI and CHANDOLU disclose the system of claim 25.
KAI further discloses a device, wherein the barrier material comprises a material that is non-reactive with a conductive material of the conductive structures (72 can be SiO2 and the conductive structures can be metal or metal nitrides, see para 148, and these are noted as being non-reactive in the applicants specification, see applicants paragraph 86)).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 and 5-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12/3/2025 regarding claims 4, 7-13 and 25-26 have been fully considered but they are not persuasive.
Regarding claim 4, the applicant argues that N J LEE does not disclose a device wherein “a thickness of the isolation structures at the bottom of the stack is relatively greater than a thickness of the isolation structures at the top of the stack” because the cited element SG of N J LEE is not an isolation structure. This argument is unpersuasive because SG is referred to in LEE as a “gate isolation insulating layer” and is an insulating layer that is capable of isolating other layers. Since SG is explicitly referred to as an isolation layer, and it has a structure, it is not clear how it would not be an isolation structure.
Regarding claim 7, the applicant argues that KAI fails to disclose every element of the claimed invention because KAI does not disclose a device comprising “isolation structures separating the dielectric block structures from the dielectric-filled slots, the isolation structures at an elevational level of the conductive structures of the stack” because the isolation structures 72 of KAI does not completely electrically isolate the dielectric block structures from the dielectric-filed slots, does not go through all of the conductive material levels, and does not completely separate the dielectric block structures from the dielectric-filed slots. This argument is not persuasive because none of those things are required by the limitations of claim 7. Claim 7 requires only that the isolation structure separate the dielectric block structures from the dielectric-filled slots, and that it be at an elevational level of the conductive structures. To separate is to form a border or barrier between, and the isolation structure 72 a barrier and is between 176 and 76 (see KAI fig 24) because a line can be drawn from 176 to 76 that passes through 72. At least some of the conductive structures 242 of KAI are located at the same elevational level as the isolation structure 72. For at least these reasons, and those given in the rejection above, KAI discloses every element of claim 7 which is not patentable over KAI. There is no requirement in the claim that the isolation structure extend to every elevational level of every conductive structure of the stack, and it does not require that it completely separate or electrically insulate the dielectric block structures from the dielectric-filled slots.
Regarding claim 25, the applicant argues the applicant argues that KAI in view of CHANDOLU fails to disclose every element of the claimed invention because KAI does not disclose a device comprising “at least one additional slot structure… and opposing isolation regions laterally separating the at least one additional slot structure from the conductive structures of the tiered stack” because the isolation structures 72 of KAI does not completely electrically isolate the additional slot structure 176 from the conductive layers 246. This argument is unpersuasive because that is not required in the claim. The only requirement in the claim is that the isolation region separate the additional slot structure from the conductive structures. As can be seen in KAI figure 24C, a line can be drawn from 176 to 246 that passes through 72. 72 is thus between and separating 178 from 246. For at least these reasons, and those given in the rejection above, KAI discloses this element of claim 25 which is not patentable over KAI in view of CHANDOLU.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811