DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-10 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OTSU (US 20200402992).
Regarding claim 1, OTSU discloses an electronic device, comprising:
a stack (the top two alternating layers 232 and 246, see fig 21A and F, para 156 and 210) comprising an alternating sequence of conductive structures (fig 21A and F, 246, para 210) and insulative structures (fig 21A and F, 232, para 156) arranged in tiers (232 and 246 are arranged in a tiered shape, see fig 21A);
at least one dielectric-filled slot (76 are slots filled with dielectric, see fig 21A, para 256) extending vertically through the stack (76 extends through 232 and 246, see fig 21A) and extending in a first horizontal direction (76 has an extension in direction hd1, see fig 21F, para 125), the at least one dielectric-filled slot defined between two internal sidewalls of the stack (76 is located between sidewalls of 232 and 246 which face other sidewalls of 232 and 246, see fig 21A);
additional dielectric-filled slots (276 are also slots filled with dielectric, see fig 21A and F, 276, para 218) extending vertically through the stack (276 extends through 232 and 246, see fig 21A) and extending in a second horizontal direction transverse to the first horizontal direction (276 have an extension in direction hd2 which is perpendicular to Hd1, see fig 21F, para 125);
separation regions (the regions of the device located between the additional dielectric filled slots 276 and the dielectric filled slot 76, see fig 21A and figure I below) adjacent at least some of the conductive structures (the separation regions are adjacent to portions of 246, see fig 21A and F, and figure I below) and between the at least one dielectric-filled slot and the additional dielectric-filled slots (lines can be drawn between 276 to 76 that pass through the separation regions, see fig 21A and F and figure I below); and
isolation structures (isolation structures 72 that are in direct contact with 276, see fig 21A and F, para 218 and figure I below) laterally interposed in the separation regions between the at least one dielectric-filled slot and the additional dielectric-filled slots (a line can be drawn from 276 to 76 that passes through 72, see fig 21F and figure I below), the isolation structures laterally adjacent to the conductive structures of the stack (246 are laterally beside conductive layers 246, see fig 21A), and at least some of the isolation structures vertically adjacent to the insulative structures of the stack (72 is located vertically above at least two insulating layers 232, see fig 21A).
Regarding claim 2, OTSU discloses the electronic device of claim 1, wherein the additional dielectric- filled slots divide the stack into blocks comprising memory pillars (there are regions of the device on either side of the additional dielectric-filled slots 276, see fig 21F), the isolation structures external to the at least one dielectric-filled slot and horizontally overlapping ends of the additional dielectric-filled slots (72 are outside 276, and overlaps along a horizontal axis with ends of 176, see fig 21F).
Regarding claim 3, OTSU discloses the electronic device of claim 1, wherein the additional dielectric- filled slots directly contact the isolation structures (276 and 72 are in direct contact, see fig 21F) without contacting the at least one dielectric- filled slot (72 and 76 are not in direct contact, see fig 21F).
Regarding claim 5, OTSU discloses the electronic device of claim 1, wherein the isolation structures directly contact the conductive structures of the stack along vertical interfaces therebetween (the interface between 72 and 246 is horizontal, see fig 21A), and the isolation structures directly contact the insulative structures of the stack along horizontal interfaces therebetween (the interface between 72 and 232 is along a horizontal direction at the bottom of 72, see fig 21A).
Regarding claim 6, OTSU discloses the electronic device of claim 1, wherein a material composition of the isolation structures (72 can be silicon oxide, see para 216-220) is substantially the same as a material composition of one or more of the at least one dielectric-filled slot (76 can be SiO, see para 217 and 256), the additional dielectric-filled slots, and the insulative structures of the stack (132 can also be silicon oxide, see para 132).
Regarding claim 7, OTSU discloses an electronic device, comprising:
a stack (the top two alternating layers 232 and 246, see fig 21A and F, para 156 and 210) comprising tiers of alternating conductive structures (fig 21A and F, 246, para 210) and insulative structures (fig 21A and F, 232, para 156) overlying a source (232 and 246 are arranged above a source material layer 10 that includes the source contact 114, see fig 15E, 21A and 21F, para 199 and 118);
pillars (the memory pillars 58, see fig 21A and 10, para 182) extending vertically through the stack and to the source, at least some of the pillars comprising a channel material (the memory openings 49 are filled with 55 to make 58, which includes the channel 60, see fig 8-9 and 21, para 173);
dielectric block structures (fig 21A and F, 276, para 218) extending vertically through the stack (see fig 21A and F, para 218), the dielectric block structures defined between two internal sidewalls of the stack (276 is located between two sidewalls of 246 that face other sidewalls of 246, see fig 21F) and spaced apart from one another in a first horizontal direction (276 are spaced apart from each other in direction hd1, see fig 21F);
dielectric-filled slots (dielectric trenches 76, see fig 21A and 21F, para 256) extending vertically through the stack (76 extend through 232 and 246, see fig 21A and para 256) and extending in a second horizontal direction (76 has an extension in direction hd2, see fig 21F) that is substantially orthogonal to the first horizontal direction (see fig 21F, para 125); and
isolation structures (isolation structure 72, see fig 21A and F, para 218) separating the dielectric block structures from the dielectric-filled slots (a line can be drawn from 276 to 72 that passes through 72, see fig 21F), the isolation structures at an elevational level of the conductive structures of the stack (72 and the top two levels of 246 are located at overlapping vertical elevations, see fig 21A).
Regarding claim 8, OTSU discloses the electronic device of claim 7, further comprising support structures (fig 21A-F, 176, para 217) extending vertically through the stack and laterally adjacent to the dielectric-filled slots (176 extends through 232 and 246 and is located besides 76, see fig 21F), the support structures and the isolation structures comprising an oxide material (76 and 176 can be oxides, see para 217 and 256).
Regarding claim 9, OTSU discloses the electronic device of claim 7, wherein sidewalls of the isolation structures abut portions of the conductive structures of the stack (sides of 72 are in direct contact with sidewalls of 246, see fig 21A and F) at a location external to vertical interfaces between the dielectric block structures and the isolation structures (the interface between 72 and 246 is located at different positions form the interface between 276 and 72, see fig 21F), the dielectric block structures directly contacting the isolation structures along the vertical interfaces therebetween (276 and 72 are in direct contact, see fig 21F).
Regarding claim 10, OTSU discloses the electronic device of claim 7, wherein one of the dielectric-filled slots is adjacent to one of the dielectric block structures in the second horizontal direction (76 and 276 are next to and close to each other in hd2, see fig 21A and F).
Regarding claim 12, OTSU discloses the electronic device of claim 7, wherein an outer boundary of an isolation region including the isolation structures (the region of the device between trenches 76, surrounding 176 and containing 72, see fig 21F) is relatively wider than outer boundaries of the dielectric block structures in the second horizontal direction (the regions of 232 and 246 between 176 are wider in direction hd2 than 276 which is contained therein, see fig 21F).
PNG
media_image1.png
446
908
media_image1.png
Greyscale
Figure I: OTSU figure 21F with added annotations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSU (US 20200402992) in view of LEE (US 20220077182).
Regarding claim 4, a first embodiment of OTSU discloses the electronic device of claim 1.
The first embodiment of OTSU fails to explicitly disclose a device, wherein the at least one dielectric- filled slot tapers in width from a broadest width at a top of the stack to a narrowest width at a bottom of the stack,
a thickness of the isolation structures at the bottom of the stack is relatively greater than a thickness of the isolation structures at the top of the stack.
A second embodiment of OTSU teaches a device, wherein the at least one dielectric- filled slot tapers in width from a broadest width at a top of the stack to a narrowest width at a bottom of the stack (376 narrows from the top of the stack to the bottom of the stack, see fig 32B, para 256),
The two embodiments of OTSU are analogous art because they both are directed towards semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of the first embodiment of OTSU with the dielectric layer geometry of the second embodiment of OTSU with the because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of the first embodiment of OTSU with the dielectric layer geometry of the second embodiment of OTSU in order to enhance device performance (see OTSU para 242).
The two embodiments of OTSU fails to explicitly disclose a device wherein a thickness of the isolation structures at the bottom of the stack is relatively greater than a thickness of the isolation structures at the top of the stack.
LEE teaches a device wherein a thickness of the isolation structures at the bottom of the stack is relatively greater than a thickness of the isolation structures at the top of the stack (the thickness of isolation insulating layer SG near the bottom of stack G1 is larger than its thickness near the top of stack G1, see fig 3A, para 34).
OTSU and LEE are analogous art because they both are directed towards semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OTSU with the insulating layer geometry of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OTSU with the insulating layer geometry of LEE in order to improve the alignment margin (see N J LEE para 89).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSU (US 20200402992) in view of KAI (US 20200235120).
Regarding claim 11, OTSU discloses the electronic device of claim 7.
OTSU fails to explicitly disclose a device, wherein a width of individual dielectric block structures in the first horizontal direction is greater than a width of individual dielectric-filled slots in the first horizontal direction.
KAI teaches a device, wherein a width of individual dielectric block structures in the first horizontal direction is greater than a width of individual dielectric-filled slots in the first horizontal direction (76 has a larger width0 in hd1 than 176, see fig 24B and 24C).
OTSU and KAI are analogous art because they both are directed towards semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OTSU with the dielectric block geometry of KAI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OTSU with the dielectric block geometry of KAI in order to reduce processing cost and time (see KAI para 44).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over OTSU (US 20200402992) in view of LEE (US 20150318301).
Regarding claim 13, OTSU discloses the electronic device of claim 7.
OTSU further discloses, wherein end surfaces of the isolation structures and the insulative structures of the stack proximal the dielectric block structures are substantially aligned with one another (the stack comprising 232 and the isolation 72 have sidewalls aligned with a sidewall of 276, see fig 21F).
OTSU fails to explicitly disclose a device wherein end surfaces of the conductive structures of the stack proximal the dielectric block structures are horizontally recessed relative to the end surfaces of the insulative structures.
KAI teaches a device wherein end surfaces of the conductive structures of the stack proximal the dielectric block structures are horizontally recessed relative to the end surfaces of the insulative structures (end surfaces of the conductive layers 172 proximate to the dielectric layers 180 are recessed relative to the end surfaces of the insulating layers 110, see fig 2A, para 63, 44).
OTSU and KAI are analogous art because they both are directed towards semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of OTSU with the conductive layer geometry of KAI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of OTSU with the conductive layer geometry of KAI in order to improve stability and reliability (see LEE para 71).
Claim(s) 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAI (US 20200235120) in view of CHANDOLU (US 20210043504).
Regarding claim 25, KAI discloses A system, comprising:
strings of memory cells (fig 24, 58, para 150) extending vertically through a tiered stack (the stack of alternating 232 and 246 surrounding 176, see fig 24, para 150) comprising a vertically alternating sequence of insulative structures (fig 24, 232, para 96) and conductive structures (fig 24, 246, para 148);
slot structures (fig 24, 76, para 153) extending vertically through the tiered stack and separating the tiered stack into blocks (76 separates 232 and 246 into blocks, see fig 24A-C, para 153), each of the blocks comprising some of the strings of memory cells (see fig 24B);
at least one additional slot structure (the slots full of 232 and 242 surrounded by 176, see fig 24A-B, para 95) extending vertically through the tiered stack (the structure of 232 and 242 extends through the tiers of 232 and 246 around 176, see fig 24A-C) and extending in a horizontal direction (the parts of 242 and 232 inside 176 extend in hd2, see fig 24B) that is substantially orthogonal to another horizontal direction in which the slot structures extend (76 extends in hd1, see fig 24B); and
opposing isolation regions (the regions of 176 surrounding 242 and 232, see fig 24A-C) laterally separating the at least one additional slot structure from the conductive structures of the tiered stack (176 separates the portions of 232 and 242 inside 176 from the stack of 232 and 246 outside 176, see fig 24A-C), the opposing isolation regions comprising a barrier material (176 is a dielectric, see para 130) between vertically neighboring insulative structures of the tiered stack (lines can be drawn between different layers of 232 that pass through 176, see fig 24A-C) and located outside of a horizontal area of the at least one additional slot structure (176 extends outside the area of the portions of 232 and 242 inside 176 as seen from the top, see fig 24B-C).
KAI fails to explicitly disclose a device comprising a processor operably coupled to an input device and an output device; and
one or more electronic devices operably coupled to the processor, the one or more electronic devices comprising.
CHANDOLU teaches a device comprising a processor (processor 304, see fig 3, para 60) operably coupled to an input device (input device 306, see fig 3, para 60) and an output device (output device 308, see fig 3, para 60); and
one or more electronic devices operably coupled to the processor (the memory device 200 with the tiered stack can be the memory device 302 which is coupled to the processor 304, see fig 3, para 60).
KAI and CHANDOLU are analogous art because they both are directed towards semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KAI with the processor coupled to the device of CHANDOLU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KAI with the processor coupled to the device of CHANDOLU in order to facilitate one or more of improved performance, reliability, and durability, lower costs, increased miniaturization of components, improved pattern quality, and greater packaging density (see CHANDOLU para 62).
Regarding claim 26, KAI and CHANDOLU disclose the system of claim 25.
KAI further discloses a device, wherein the barrier material comprises a material that is non-reactive with a conductive material of the conductive structures (176 can be SiO2 and the conductive structures 246 can be metal or metal nitrides, see para 170, 148 and 101, and these are noted as being non-reactive in the applicants specification, see applicants paragraph 86).
Response to Arguments
Applicant’s arguments regarding claim 3, see Applicant Arguments/Remarks, filed 5/11/2026, with respect to the rejection(s) of claim(s) 3 under 35 U.S.C. 102(a)(1) in the office action of 3/11/2026 have been fully considered and are persuasive. The examiner appears to have inadvertently confused the elements relied upon as “at least one dielectric-filled slot” and the “additional dielectric-filled slot” of claims 1 and 3 in the rejection of claim 3. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of OTSU as described in the rejection above.
Applicant's arguments filed 3/11/2026 regarding claims 1, 2, 7 and 25 have been fully considered but they are not persuasive.
Regarding claims 1, 7 and 25, the applicant argues that OTSU and KAI do not a device comprising “isolation structures … the isolation structures laterally adjacent to the conductive structures of the stack …” because the isolation structures 72 of OTSU does not extend to be at the level of every conductive structure 246 of the stack, just the top two of them. The examiner does not believe that the claims require the isolation structure be laterally adjacent with each conductive structure of the conductive structures, only “the conductive structures”. For the sake of argument and to advance prosecution, the examiner also notes, as in the rejection above, that the top two sets of 232 and 246 in the device of OTSU figure 21 satisfy all the requirements in the claims regarding the stack, and 72 directly contacts the side surfaces of and extends to be adjacent to both of the top two layers of 246, as can be seen in fig 21A.
Regarding claim 2, the applicant argues that OTSU does not disclose a device “the isolation structures … horizontally overlapping ends of the additional dielectric-filled slots”. This argument is not persuasive because, as noted in the rejection above, the ends of the additional dielectric-filled slots 276 overlap along a horizontal axis with isolation structures 72 .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Prosecution Insights