CTFR 17/819,710 CTFR 100025 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment The Amendment filed on 02/23/2026 has been entered. Claims1-8 and 11-20, remain pending in the application. Claims 9 and 10 have been cancelled. Applicant’s amendments have overcome each and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 12/16/2025 . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1, 3-7 and 11-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liaw et al., (United States Patent Application Publication Number, US 2024/0055433 A1) hereinafter referenced as Liaw . Regarding claim 1, Liaw teaches a semiconductor device, comprising: an integrated circuit chip having a frontside and a backside (Fig.7E, element #120 is the front side and element #110 is the backside, frontside and backside are interchangeable as showed in Fig.7E and 8E), the frontside including a frontside signal delivery line configured to transmit signals to a first terminal of a transistor arranged in the integrated circuit chip (Fig.3A, element #244B, is connected to the drain, element #204SD), and the backside including a backside power delivery line, configured to transmit power to a second terminal of the transistor (Fig.3B, element #222D, is connected to the drain, element #204SD) and a backside signal delivery line (Fig.3C, element #222C is connected to the gate, element #303), a contact configured to connect a gate of the transistor to the backside signal delivery line the backside signal delivery line configured to transmit signals to the gate of the transistor (Fig.3C, element #214A connects gate, element #303A to the backside signal delivery line, element #222C) wherein an adequate spacing is located between the backside power delivery line and the backside signal delivery line (Fig.2A, the spacing between the backside power and backside signal delivery lines is adequate since the transistors of the device function); and a via extending through the frontside and the backside of the integrated circuit chip (Fig.7E, element #712, paragraph [0076], rows 6-14) wherein the via is configured to transmit signals between a lowermost contact on the frontside of the integrated circuit chip and an uppermost backside contact on the backside of the integrated circuit chip (Fig.7E, via, element #712 connects the lowermost frontside contact, element #234, through conductive line, element #244, and connects to the uppermost backside contact, formed by elements #312, #212 and #216, which are is showed in Fig.3B as #312C, #212C and #216C, through the conductive line, element #222, paragraph [0076], rows 6-14), wherein a first upper portion of the uppermost backside contact (see Fig.3B, annotated below, first portion is the portion of element #312C between the dotted lines) is laterally offset from a second lower portion of the uppermost backside contact by a non-zero distance (Fig.3B annotated below, the first portion is laterally offset from the second lower portion, which is element #312C), in order to provide the adequate spacing between the backside power delivery line and the backside signal delivery line (Fig.3B, the backside power delivery line, element #222D is adequately spaced from the backside signal delivery lines, element #222D and #222E), and the second lower portion of the uppermost backside contact is aligned with and in direct contact with a source/drain (S/D) epitaxy material (Fig.3B, element #312C is aligned and in direct contact with a source/drain epitaxy materials, element #204SD, paragraph [0043], rows 1-7). Regarding claim 3, Liaw teaches the device of claim 1 as set forth in the anticipation rejection. Liaw further teaches the semiconductor device of claim 1, wherein the lowermost contact on the frontside of the integrated circuit chip is a back end of line interconnect (Fig.7E, lowermost contact, element #234, is formed in the contact layer #140, of the BEOL interconnect structure, element #120). Regarding claim 4, Liaw teaches the device of claim 1 as set forth in the anticipation rejection. Liaw further teaches he semiconductor device of claim 1, wherein the backside of the integrated circuit chip includes a plurality of interconnect layers arranged so as to extend above the uppermost backside contact and the transistor (Fig.1A, rotated vertically with 180 degrees, element #B-M1). Regarding claim 5, Liaw teaches the device of claim 1 as set forth in the anticipation rejection. Liaw further teaches the semiconductor device of claim 1, wherein the frontside of the integrated circuit chip includes a plurality of interconnect layers arranged so as to extend between the lowermost contact and the transistor (Fig.7E, elements #232 extend between element #234 and the transistors). PNG media_image1.png 1302 1592 media_image1.png Greyscale Regarding claim 6, Liaw teaches a semiconductor component, comprising: an integrated circuit chip having a frontside and a backside (Fig.7E, element #120 is the front side and element #110 is the backside, frontside and backside are interchangeable as showed in Fig.7E and 8E), the integrated circuit chip including a first FET arranged in a first FET region and a second FET arranged in a second FET region (Fig.2A, cell, element #21, includes a first FET associated with active region, element #204 and a second FET associated with active region, element #202, paragraph [0040], rows 1-5), the first FET region and the second FET region separated from one another by a space (Fig.2A, space between elements #204 and #202); a first backside contact connecting a backside power delivery line to a terminal of the first FET (Fig.3B, backside contact, formed by elements #312C, #212C and #216C, connects the power delivery line, element #222D to the source/drain, element #204SD), the backside power delivery line arranged on the backside of the integrated circuit chip (Fig.7E, the contact is arranged in the backside region, element #110); a second contact connecting a frontside signal delivery line to a terminal of the second FET (Fig.3A, contact, element #234A connects frontside signal delivery line, element #244A to the source/drain, element #202SD of the second FET), the frontside signal delivery line arranged on the frontside of the integrated circuit chip (Fig.7A, the frontside contact is arranged in the frontside region, element #120); a third contact connecting a backside signal delivery line to a gate (Fig.3C, element #214A connects backside signal delivery line, element #222C to the gate, element #303A) that connects the first FET and the second FET (Fig.2A, element #214A connects to the gate, and the gate is shared by both FETs, element #206A), the backside signal delivery line arranged on the backside of the integrated circuit chip (Fig.7E, elements #222, including element #222C, are arranged in the backside region, element #110), wherein: the first backside contact (Fig.3B, backside contact, formed by elements #312C, #212C and #216C) includes a first upper portion having a first centerline which is aligned with a centerline of the terminal of the first FET (Fig.3B annotated above, first upper portion is the portion of element #212C between the dotter lines, Fig.2A, the horizontal centerline of the first portion is aligned to the horizontal centerline of element #204), and the first backside contact includes a second lower portion (Fig.3B, element #312C) having a second centerline which is not aligned with the centerline of the terminal of the first FET (Fig.3B, element #312C has a vertical centerline which is perpendicular on the horizontal centerline of element #204), wherein an adequate spacing is located between the backside power delivery line and the backside signal delivery line (Fig.2A, the spacing between the backside power and backside signal delivery lines is adequate since the transistors of the device function) , and the first upper portion of the first backside contact is laterally offset from the second lower portion of the first backside contact by a non- zero distance (Fig.3B annotated above, the first portion is laterally offset from element #312C), in order to provide the adequate spacing between the backside power delivery line and the backside signal delivery line (Fig.3B, the backside power delivery line, element #222D is adequately spaced from the backside signal delivery lines, element #222D and #222E), and the second lower portion of the first backside contact is aligned with, and in direct contact with a source/drain (S/D) epitaxy material (Fig.3B, element #312C is aligned and in direct contact with a source/drain epitaxy materials, element #204SD, paragraph [0043], rows 1-7). Regarding claim 7, Liaw teaches the device of claim 6 as set forth in the anticipation rejection. Liaw further teaches the semiconductor component of claim 6, wherein the first FET is a pFET and the second FET is an nFET (paragraph [0040], rows 1-5). Regarding claim 11, Liaw teaches the device of claim 6 as set forth in the anticipation rejection. Liaw further teaches t he semiconductor component of claim 6, wherein the first centerline of the first upper portion of the first backside contact is arranged nearer to the space than is the second centerline of the second lower portion of the first backside contact (Fig.2A, first upper portion of the first backside contact, element #216C is closer to the space than is the second lower portion of the backside contact, portion of elements #212C and #312C overlapping with element #204, therefore any centerline will be closer to the space). Regarding claim 12, Liaw teaches the device of claim 6 as set forth in the anticipation rejection. Liaw further teaches the semiconductor component of claim 6, further comprising a fourth contact connecting the frontside signal delivery line to a further terminal of the first FET (frontside signal delivery line, element #244A supplies the VSS voltage, paragraph [0058], rows 14-21; first FET is a pFET, therefore it operates with the drain connected to VSS; as such, the frontside signal delivery line and the drain of the pFET must be connected). Regarding claim 13, Liaw teaches the device of claim 6 as set forth in the anticipation rejection. Liaw further teaches the semiconductor component of claim 6, wherein the backside signal delivery line is arranged in the space (Fig.2A, element #222C is arranged in the space between elements #202 and #204) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw, in view of disclosed prior art, Beyne et al., (United States Patent Application Number, US 2018/0145030 A1), hereinafter referenced as Beyne . Regarding claim 2, Liaw teaches the device of claim 1 as set forth in the anticipation rejection. Liaw does not teach wherein the uppermost backside contact on the backside of the integrated circuit chip is an input-output terminal. Beyne teaches the uppermost contact (Fig.9, formed by elements #70 and #72) on the backside of the integrated circuit chip (paragraph [0059], rows 11-15) is an input-output terminal (paragraph [0059], rows 3-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Beyne and disclose the uppermost contact is an input-output terminal. This provides the shortest path for data to be transferred from the frontside to the backside of the device, therefore allowing fast data transfer rates . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw, in view of, Chen et al., (United States Patent Number, US 8993433 B2), hereinafter referenced as Chen . Regarding claim 8, Liaw teaches the device of claim 6 as set forth in the anticipation rejection. Liaw does not teach the semiconductor component of claim 6, wherein the first upper portion and the second lower portion of the first backside contact are integrally formed with one another and are made of a same material. Chen teaches wherein the first upper portion and the second lower portion of the first backside contact are integrally formed with one another and are made of a same material (Fig.11 and Fig.12, drain contact, element #64a, has a lower portion, portion between the bottommost part of element #64a and located below the top side of element #12 in vertical direction, and an upper portion, portion above the bottom portion, both are form integrally, using same material). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen and disclose wherein the first upper portion and the second lower portion of the first backside contact are integrally formed with one another and are made of a same material. As disclosed by Chen, this prevents the formation of a barrier layer between the two portions of the contact, which increases contact conductivity and results in a less complex manufacturing process, therefore increasing yield (column 1, rows 29-37) . 07-21-aia AIA Claim s 14, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, in view of, Guler et al., (United States Patent Application Publication Number, US 2023/0317787 A1), hereinafter referenced as Guler . Regarding claim 14, Liaw teaches the device of claim 6 as set forth in the anticipation rejection. Liaw does not teach the semiconductor component of claim 6, further comprising: a gate metal extension extending into the backside of the integrated circuit chip, the gate metal extension integrally formed with the gate and formed of a same material as the gate. Guler teaches a gate metal extension extending into the backside of the integrated circuit chip, the gate metal extension integrally formed with the gate and formed of a same material as the gate (Fig.1D and Fig.1E, metal extension, element #143 is integrally formed with the gate, from the same material, paragraph [0038], rows 3-7). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Guler and disclose a gate metal extension extending into the backside of the integrated circuit chip, the gate metal extension integrally formed with the gate and formed of a same material as the gate. As disclosed by Guler, the metal gate extension allows powering the gate through the metal extension using a backside contact (Fig.1F, backside contact, element #172, paragraph [0042], rows 1-4) and also allow a “plug-last” approach which reduces the cell height (paragraphs [0044] and [0045]). Regarding claim 15, Liaw teaches the device of claim 6 as set forth in the anticipation rejection and the combination of Liaw and Guler teaches the device of claim 14 as set forth in the obviousness rejection. Liaw further teaches a third backside contact arranged in the space (Fig.2A, element #214 is in the space between element #202 and #204) that connects the gate electrode (Fig.3C, element #303A) with a backside signal line (Fig.3C, element #222C). As noted in the obviousness rejection of claim 14, Guler discloses the metal extension being used to connect the gate electrode to a backside contact, and the metal gate extension is located on bottom of the backside contact (Fig.1F, rotated vertically by 180 degrees, extension element #143A connects the gate electrode, element #142A to the backside contact, element #172). Therefore, the combination of Liaw and Guler teaches wherein the gate metal extension is arranged in the space. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Guler and disclose wherein the gate metal extension is arranged in the space between the two FET regions. As disclosed by Guler, the gate metal extension is used to connect the gate electrode to a backside contact and using the space between the two FET regions for powering the gate saves space, which in turns allows for a smaller footprint of the device. Regarding claim 16, Liaw teaches the device of claim 6 as set forth in the anticipation rejection and the combination of Liaw and Guler teaches the device of claims 14 and 15 as set forth in the obviousness rejection. Liaw further teaches the semiconductor component of claim 15, wherein: the top side of the third contact is in direct contact with the backside signal delivery line (Fig.3C, top side of element #214A is in direct contact with the backside signal delivery line, element #222C) . Guler teaches the bottom side of the third contact is in direct contact with the gate metal extension (Fig.1F, rotated vertically by #180 degrees, bottom side of element #172 is in direct contact with the gate metal extension, element #143A). Thus, the combination of Liaw and Guler teaches the third contact is in direct contact with the gate metal extension and with the backside signal delivery line. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Guler and disclose the third contact is in direct contact with the gate metal extension and with the backside signal delivery line. As disclosed by Guler, this allows powering the gate directly through the metal extension and the backside contact (Fig.1F) which helps reduce device thickness (paragraphs [0044], rows 1-2). Liaw discloses the third contact is made of copper (paragraph [0031], rows 1-3) and the gate material is formed of cobalt (paragraph [0023], rows 7-10). Guler discloses the gate metal extension is formed by the same material as the gate electrode (Fig.1D and Fig.1E, metal extension, element #143 is integrally formed with the gate electrode, from the same material, paragraph [0038], rows 3-7) and the gate electrode can be made of cobalt (paragraph [0109] rows 1-4). Thus, the combination of Liaw and Guler discloses the third contact is made of a different material than the gate metal extension. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Guler and disclose third contact is made of a different material than the gate metal extension. Using different materials for the gate extension and the contact allows independent optimization of the gate and contact formation processes . 07-21-aia AIA Claim s 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shang-Wen Chang et al., (United States Patent Application Publication Number US 2021/0375761 A1), hereinafter referenced as Chang, in view of Injo Ok et al., United States Patent Application Publication Number US 2016/0379893 A1), hereinafter referenced as Ok . Regarding claim 17, Chang teaches a method for forming a semiconductor device, the method comprising: forming a frontside device (structure of Fig.29A), on a wafer (Fig.22B, element #50, paragraph [0080], rows 1-2) such that the frontside device includes a first FET (Fig.29A, comprising elements #92D, paragraph [0094], rows 7-8) in a first FET region (Fig.29A, region located to the right side of the rightmost element #161) a second FET (Fig.29A, comprising elements #92C, paragraph [0094], rows 7-8) in a second FET region (Fig.29A, region between the middle and rightmost element #161), a placeholder that is in direct contact with a terminal of the first FET (Fig.24B, placeholder element #91, paragraph [0046], rows 4-6, in contact with drain element #92) and a frontside contact (Fig.24B, element #112) connected to a frontside signal delivery line (Fig.24B, connected to elements #122, paragraph [0113], rows 4-7 and 15-16); removing the wafer from the frontside device (paragraph [0080], rows 1-2) creating an opening that removes a portion of the placeholder (Fig.25B, element #91 is removed and opening #128 is formed), the opening having a centerline that is offset relative to a centerline of the terminal of the first FET (Fig.25B, centerline of the opening element #128 in the vertical direction is offset relative to the centerline of the terminal of the first FET, which is located between the two element #92D), wherein the creating the opening further comprises forming the opening offset from the centerline of the terminal of the first FET (Fig.25B, centerline of the opening element #128 in the vertical direction is offset relative to the centerline of the terminal of the first FET, which is located between the two element #92D) by a predetermined distance (a predetermined distance is any distance) to enable an adequate spacing between a backside power delivery line and a backside signal delivery line (Fig.29A, backside power delivery line is element #135P located on the right side of the figure, paragraph [0094], row 11-13, and the backside signal delivery line is element #135S located on the right side of the figure, paragraph [0095], rows 3-4. The backside power delivery line is located on the same vertical axis with the opening, now filled with metal #130. The offset of the opening provides adequate spacing between elements #135P and #135S located on the right side of the figure, since the device is functional). Chang teaches removing the placeholder in a single step. Chang does not teach removing a remainder of the placeholder to expose the terminal of the first FET. Ok teaches creating an opening that removes a portion of the placeholder, the opening having a centerline that is offset relative to a centerline of the terminal of the first FET; removing a remainder of the placeholder to expose the terminal of the first FET. (Fig.5D, the forming of opening #138 in placeholder, element #140 is performed in two steps, paragraph [0032] rows 7-12 and paragraph [0033] rows 1-3, where the opening has a centerline that is offset relative to a centerline of the terminal). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Ok and disclose removing the placeholder in two steps to expose the terminal of the FET. As disclosed by Ok, this allows forming or irregular shaped contacts, which helps maintain minimum required wiring level spacing (paragraph [0036], rows 1-4). Chang further teaches forming a backside device including filling the opening with contact material (Fig.26B, the opening is filled with contact material, elements #129 and #130, paragraph [0084], row 4-8) to form a first backside contact that is in direct contact with the terminal of the first FET (Fig.26B, contact made by elements #129 and #130 is in direct contact with element #92), the backside device including a backside power delivery line (Fig.29A, element #135P located on the right side of the figure, paragraph [0094], row 11-13) connected to the first backside contact (Fig.29A, elements #135P and #130 located on the right side of the figure are connected) and a backside signal delivery line (Fig.29A element #135S, paragraph [0095], rows 3-4), connected to a second backside contact (Fig.29A, element #130 corresponding to the right side of the second FET) such that the backside signal delivery line is arranged between the first FET region and the second FET region (Fig.29A, element #135S is arranged between the two FET regions), wherein an adequate spacing is located between the backside power delivery line and the backside signal delivery line (the spacing between elements #135P and #135S is adequate since the device is functional), and the first backside contact is offset from the second backside contact (Fig.29A, the two elements #130 are offset) wherein the second backside contact is aligned with and in direct contact with a source/drain (S/D) epitaxy material (Fig.29A, element #130 are aligned with the source/drain material located on the half right side of elements #92, and is in direct contact with elements #92 which are epitaxially grown, paragraph [0051], rows 1-2). Regarding claim 18, the combination of Chang and Ok teaches the method of claim 17 as set forth in the obviousness rejection. Chang further teaches, wherein the opening (Fig.29A, the opening filled by element #130 located on the right side of the figure) is created such that the centerline of the opening is farther from the second FET region than is the centerline of the terminal (Fig.29A, the centerline of the opening is further from the second FET region, which is region between the middle and rightmost element #161, than is the centerline of the second FET region, the centerline is between the two elements #92D) . 07-21-aia AIA Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chang, in view of Ok and in view of Ohtou et al., (United States Patent Application Publication Number, US 2018/0151494 A1), hereinafter references as Ohtou . Regarding claim 19, the combination of Chang and Ok teaches the method of claim 17 as set forth in the obviousness rejection. Chang further teaches wherein forming the frontside device further includes forming a gate connecting the first FET and the second FET (Fig.33G, element #102, paragraph [0111], row 7). The combination of Chang and Ok does not teach the gate including a gate metal extension that extends toward the backside device and is made of a same material as the gate. Ohtou teaches wherein forming the frontside device further includes forming a gate connecting the first FET and the second FET (Fig.2C, gates elements #205 and #201 are coupled together, paragraph [0058], rows 3-7, also Fig.8A-8E shows the formation of the gate, paragraph [0100], rows 1-4) the gate including a gate metal extension that extends toward the backside device (Fig.8C, the portion of element #760 that fills recess element #755, labeled in Fig.8B, paragraph [0102], rows 1-2, extends towards the backside) and is made of the same material as the gate (Fig.8C, same material, element #760). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Ohtou and disclose wherein the gate including a gate metal extension that extends toward the backside device and is made of a same material as the gate. As disclosed by Ohtou, the extension allows connecting the gates with buried rails . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Ok, Ohtou and in view of Wei, (Unites States Patent Application Publication Number, US 2023/0067354 A1), hereinafter referenced as Wei . Regarding claim 20, the combination of Chang and Ok teaches the method of claim 17 as set forth in the obviousness rejection and the combination of Chang, Ok and Ohtou teaches the method of claim 19 as set forth in the obviousness rejection. Chang teaches forming the second backside contact in direct contact with the source or drain. The combination of Chang and Ok does not teach wherein forming the backside device further includes forming the second backside contact in direct contact with the metal gate metal extension. Wei teaches forming the backside device further includes forming the backside contact in direct contact with the metal gate metal extension (Fig.2M, element #118a, is in direct contact with the metal gate extension, element #122a, note that element #118a reaches the backside of the substrate). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Wei and disclose forming the backside contact in direct contact with the metal gate metal extension. As disclosed by Wei, backside connections free overhead to make room for logic frontside connections and allow for large power rails with lower resistance and power dissipation (paragraph [0002], rows 13-17). The combination of Chang and Ok does not teach the second backside contact is made of a different material than the gate. Wei teaches the second backside contact is made of a different material than the gate (element #118a can be made of aluminum, paragraph [0025], rows 10-11, gate element #116a, can be titanium). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Wei and disclose the second backside contact is made of a different material than the gate. Gate materials may require specialized deposition techniques and deposition conditions and may not form good contacts with materials used for power or signal lines, which require higher conductivity materials for optimal signal transmission. Therefore, making the contact of a different material than the gate allows for an increase in device reliability, by allowing the use of multiple conductive materials that have the best adherence to the different underlying layers, and match the optimum process conditions of their corresponding process steps . Response to Arguments 07-37 Applicant’s arguments filed on 02/23/2026 have been fully considered but they are not persuasive. As noted in the rejection of claims 1 and 6, Liaw teaches the uppermost backside contact, formed by elements #312, and #212, which is showed in Fig.3B annotated below), has a first upper portion (Fig.3B, annotated below, first portion is the portion of element #312C between the dotted lines) is that is laterally offset from a second lower portion of the uppermost backside contact by a non-zero distance (Fig.3B annotated below, the first portion is laterally offset from the second lower portion, which is element #312C), in order to provide the adequate spacing between the backside power delivery line and the backside signal delivery line (Fig.3B annotated below, the backside power delivery line, element #222D is adequately spaced from the backside signal delivery lines, element #222D and #222E). PNG media_image1.png 1302 1592 media_image1.png Greyscale As noted in the rejection of claims 17, Chang teaches creating an opening that removes the placeholder (Fig.25B, element #91 is removed and opening #128 is formed), the opening having a centerline that is offset relative to a centerline of the terminal of the first FET (Fig.25B, centerline of the opening element #128 in the vertical direction is offset relative to the centerline of the terminal of the first FET, which is between the two element #92D), wherein the creating the opening further comprises forming the opening offset from the centerline of the terminal of the first FET (Fig.25B, centerline of the opening element #128 in the vertical direction is offset relative to the centerline of the terminal of the first FET, which is located between the two element #92D) by a predetermined distance (a predetermined distance is any distance) to enable an adequate spacing between a backside power delivery line and a backside signal delivery line (Fig.29A, backside power delivery line is element #135P located on the right side of the figure, paragraph [0094], row 11-13, and the backside signal delivery line is element #135S located on the right side of the figure, paragraph [0095], rows 3-4. The backside power delivery line is located on the same vertical axis with the opening, now filled with metal #130. The offset of the opening provides adequate spacing between elements #135P and #135S located on the right side of the figure, since the device is functional). Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Anderson et al., (United States Patent Number US 10,879,112 B2) teaches a contact with a first upper portion laterally offset from a second lower portion by a non-zero distance (Fig.8). Chang et al., (United States Patent Application Publication Number, US 2017/0170110 A1) teaches a contact with a first upper portion laterally offset from a second lower portion by a non-zero distance (Fig.2E). THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00AM-5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 17/819,710 Page 2 Art Unit: 2899 Application/Control Number: 17/819,710 Page 4 Art Unit: 2899 Application/Control Number: 17/819,710 Page 5 Art Unit: 2899 Application/Control Number: 17/819,710 Page 6 Art Unit: 2899 Application/Control Number: 17/819,710 Page 7 Art Unit: 2899 Application/Control Number: 17/819,710 Page 8 Art Unit: 2899 Application/Control Number: 17/819,710 Page 9 Art Unit: 2899 Application/Control Number: 17/819,710 Page 10 Art Unit: 2899 Application/Control Number: 17/819,710 Page 11 Art Unit: 2899 Application/Control Number: 17/819,710 Page 12 Art Unit: 2899 Application/Control Number: 17/819,710 Page 13 Art Unit: 2899 Application/Control Number: 17/819,710 Page 14 Art Unit: 2899 Application/Control Number: 17/819,710 Page 15 Art Unit: 2899 Application/Control Number: 17/819,710 Page 16 Art Unit: 2899 Application/Control Number: 17/819,710 Page 17 Art Unit: 2899 Application/Control Number: 17/819,710 Page 18 Art Unit: 2899 Application/Control Number: 17/819,710 Page 19 Art Unit: 2899 Application/Control Number: 17/819,710 Page 20 Art Unit: 2899 Application/Control Number: 17/819,710 Page 21 Art Unit: 2899 Application/Control Number: 17/819,710 Page 22 Art Unit: 2899
Prosecution Insights